CN114171392A - 一种制备大面积高性能n型二维碲化钼场效应晶体管阵列的方法 - Google Patents

一种制备大面积高性能n型二维碲化钼场效应晶体管阵列的方法 Download PDF

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CN114171392A
CN114171392A CN202111361183.6A CN202111361183A CN114171392A CN 114171392 A CN114171392 A CN 114171392A CN 202111361183 A CN202111361183 A CN 202111361183A CN 114171392 A CN114171392 A CN 114171392A
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戴伦
程智轩
贾雄辉
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Abstract

本发明公开了一种制备大面积高性能n型二维碲化钼场效应晶体管阵列的方法。该方法先在衬底上生长半导体相碲化钼薄膜,再图案化半导体相碲化钼薄膜并生长钨薄膜,得到金属钨和半导体相碲化钼相间的薄膜,继而通过化学气相沉积法使钨薄膜变为半金属相碲化钨薄膜;再次图案化后得到分立的以半导体相碲化钼为沟道、以半金属相碲化钨为电极的器件阵列;最后通过原子层沉积氧化铪薄膜对器件实现n型掺杂,并制备图案化的顶栅金属电极,获得大面积高性能n型二维碲化钼场效应晶体管阵列。该方法对二维碲化钼n型掺杂效果理想,掺杂程度可调,同时所制备的器件源漏电极接触电阻低,提高了器件性能,为二维半导体材料在集成电路等领域的应用提供了基础。

Description

一种制备大面积高性能n型二维碲化钼场效应晶体管阵列的 方法
技术领域
本发明涉及对二维材料进行n型掺杂、低接触电阻源漏电极制备及大面积场效应晶体管器件制备,具体涉及一种制备大面积高性能n型二维碲化钼场效应晶体管阵列的方法及应用。
背景技术
随着集成电路的发展,传统的硅基晶体管尺寸越来越小,已经接近其量子极限与热力学极限,需要新的材料来延续摩尔定律。二维半导体材料由于其厚度缩小到只有一个或几个原子层厚度尺度,可以使短沟道效应出现的特征沟道长度进一步缩小。作为一种常见的二维材料,碲化钼材料在空气中表现为p型且易于大面积制备,同时易与金属相二维材料如半金属相碲化钼或碲化钨形成面内异质结构,从而有效降低接触电阻。但是,为了在逻辑电路中得以广泛应用,还需要制备大面积n型碲化钼场效应晶体管阵列。现有文献报道的对碲化钼进行n型掺杂的方法主要包括化学掺杂、原子层沉积氧化铝等,但是这些文献报道通常仅限于制备单个器件,且掺杂效果尚不够理想。因此,发明一种制备大面积高性能n型二维碲化钼场效应晶体管阵列的方法极为重要。
发明内容
针对以上现有技术存在的问题,本发明提出一种制备大面积高性能n型二维碲化钼场效应晶体管阵列的方法。
本发明的制备大面积高性能n型二维碲化钼场效应晶体管阵列的方法,包括以下步骤:
1)在衬底上生长一层1-30nm厚的半导体相碲化钼薄膜;
2)通过光刻、显影、刻蚀的方法图案化半导体相碲化钼薄膜,然后磁控溅射一层1-30nm厚的钨薄膜,剥离光刻胶后得到金属钨和半导体相碲化钼彼此相间的薄膜;
3)以碲单质为碲源,通过化学气相沉积法生长半金属相碲化钨薄膜(该过程中,步骤2)沉积的钨薄膜与碲反应生成半金属相碲化钨薄膜),从而在衬底上形成半金属相碲化钨和半导体相碲化钼相间的薄膜;
4)通过光刻、显影和刻蚀的方法图案化步骤3)所形成的半金属相碲化钨和半导体相碲化钼相间的薄膜,得到分立的以二维碲化钼为沟道、以二维碲化钨为电极的器件阵列;
5)通过原子层沉积技术在器件阵列上生长一层10-50nm厚的氧化铪薄膜,在形成电介质层的同时实现对二维碲化钼沟道的n型掺杂;
6)通过光刻和电子束蒸发(或热蒸发)的方法制备图案化的顶栅金属电极,即可获得大面积高性能n型二维碲化钼场效应晶体管阵列。
上述步骤1)中,所述衬底通常是硅/氧化硅衬底,或者是绝缘衬底。
上述步骤1)中,优选的,生长半导体相碲化钼薄膜的方法可以是:1a)在衬底上通过磁控溅射或电子束蒸发的方法制备一层钼薄膜;1b)以碲单质为碲源,通过化学气相沉积法使所述钼薄膜与碲反应,在衬底上生长大面积半导体相碲化钼薄膜。
上述步骤1b)和步骤3)通常在常压管式炉中进行,将前一步骤处理后的样品和适量碲粉末放入石英舟中,再将石英舟推至管式炉内进行化学气相沉积,碲粉末在样品上流。
上述步骤1b)中进行化学气相沉积的温度控制在580~650℃,时间为1~4h,得到半导体相碲化钼薄膜。
上述步骤3)进行化学气相沉积的温度控制在500~700℃,时间在0.5h以上,得到半金属相碲化钨薄膜。
在上述步骤2)和步骤4)图案化的方法中,刻蚀方法可以是反应离子刻蚀(RIE),也可以是电感耦合等离子体刻蚀(ICP);所用刻蚀气体为含氟气体例如六氟化硫、三氟甲烷、四氟化碳等。
上述步骤5)进行原子层沉积的前驱体为四(二甲氨基)铪和水,反应温度为90-250℃。
上述步骤6)中顶栅金属电极采用电子束蒸发或热蒸发的方法制备,金属材料可选用常规金属电极材料,例如:厚度为10nm的钛和50nm的金。
本发明的技术优势主要体现在:
通过本发明方法利用原子层沉积氧化铪对二维碲化钼材料进行的n型掺杂具有较为理想的n型掺杂效果,且通过原子层沉积的温度和厚度可以调控n型掺杂的程度。同时,该方法可以应用于大规模集成化的器件制备,为实现基于二维材料的复杂逻辑电路提供了基础。此外,利用该方法制备的n型碲化钼场效应晶体管源漏电极接触电阻(即碲化钨和碲化钼接触电阻)很低,提高了载流子的注入效率,因而提高了器件的性能。该方法为二维半导体材料在逻辑电路等领域的应用提供了基础。
附图说明
图1.实施例制备大面积高性能n型二维碲化钼场效应晶体管阵列的流程中的薄膜照片,其中:(a)是步骤3)得到的大面积半导体相碲化钼薄膜的光学照片;(b)是半导体相碲化钼薄膜经过光刻、刻蚀、磁控溅射、剥离及二次生长之后得到的半导体相碲化钼与半金属相碲化钨条状相间的结构的光学照片;(c)是步骤6)经过第二次光刻、刻蚀及去胶之后得到的以半导体相碲化钼为沟道以半金属相碲化钨为电极的器件阵列的光学照片;(d)是步骤7)经过原子层沉积氧化铪之后得到的n型掺杂的器件阵列的光学照片。
图2.实施例步骤6)得到的以半导体相碲化钼为沟道、以半金属相碲化钨为电极的器件阵列中半导体相碲化钼(上)和半金属相碲化钨(下)的拉曼光谱。
图3.实施例步骤8)通过光刻、电子束蒸发与剥离过程得到图案化的顶栅金属电极,从而得到的大面积n型碲化钼场效应晶体管阵列的光学照片。
图4.实施例制备的n型碲化钼场效应晶体管的电学表征结果,其中:(a)是器件的伏安特性曲线;(b)是器件的顶栅转移特性曲线。
图5.实施例中原子层沉积相同厚度的氧化铪和氧化铝制备的n型碲化钼场效应晶体管的转移特性曲线对比图。
图6.实施例中半金属相碲化钨与半金属相碲化钼接触的n型碲化钼场效应晶体管的转移特性曲线对比图。
具体实施方式
下面结合附图,通过具体实施例子,进一步阐述本发明。
本实施例制备大面积高性能n型二维碲化钼场效应晶体管阵列的方法包括以下步骤:
1)准备硅/氧化硅衬底,SiO2厚度为285nm。
2)在衬底上通过磁控溅射的方法蒸镀一层厚度约为2nm的钼薄膜。
3)对样品进行化学气相沉积:将适量碲粉和样品置于石英舟中,再将石英舟放入管式炉中,使碲粉在样品上流;保持7sccm氢气和5sccm氩气的气流,加热管式炉使之经过20分钟升温至630℃,保持腔室恒定温度3小时后自然降温至室温,即可得到半导体相碲化钼薄膜,如图1中(a)图所示。
4)对上一步得到的半导体相碲化钼薄膜进行光刻与反应离子刻蚀,使之图案化,而后磁控溅射约5nm厚的钨薄膜,剥离之后得到金属钨与半导体相碲化钼条状相间的结构。其中反应离子刻蚀所用气体为30sccm的六氟化硫气体和5sccm的氩气,刻蚀功率为70W,刻蚀压强10Pa,刻蚀时间1分50秒。
5)将上述样品放到管式炉中进行第二次化学气相沉积生长。生长方法如步骤3)所述,管式炉加热的温度变为560℃,生长时间变为1小时,其他条件保持不变,即可得到半导体相碲化钼与半金属相碲化钨条状相间的结构,如图1中(b)图所示。
6)对上述样品再次进行光刻、反应离子刻蚀等图案化工艺,最后在丙酮中去除光刻胶并经过异丙醇清洗过程,得到如图1中(c)图所示的器件阵列。其中,每个器件的源漏电极均为半金属相碲化钨,中间沟道部分均为半导体相碲化钼。经过拉曼光谱表征,如图2所示,证实得到了半金属相碲化钨接触半导体相碲化钼的结构。
7)对上述样品进行原子层沉积,在其上沉积一层30nm厚的氧化铪层,作为电介质层的同时实现了对沟道区域半导体相碲化钼的n型掺杂,如图1中(d)图所示。其中原子层沉积的温度为90℃,反应前体为四(二甲氨基)铪和水。
8)在上述样品上再次进行光刻、电子束蒸发与剥离过程得到图案化的顶栅金属电极,由此即制备出了大面积n型二维碲化钼场效应晶体管阵列,如图3所示。其中金属电极选择10nm厚的钛与50nm厚的金。
对得到的n型碲化钼场效应晶体管进行电学表征,得到其伏安特性曲线与转移特性曲线如图4所示,可见其基本为欧姆接触且电学行为表现为良好的n型特征。
同时,为了验证原子层沉积氧化铪的掺杂方法对于现有文献报道提到的氧化铝掺杂的优势,对比了相同厚度(30nm)、相同工艺流程下的氧化铪与氧化铝作为掺杂材料与电介质层的顶栅转移特性曲线,如图5所示,氧化铪掺杂的转移曲线开关比更高,且在相同栅压下的源漏电流量级更大,可见本发明方法使用的氧化铪掺杂的掺杂效果更好。
进而,为了进一步验证半金属相碲化钨接触的优势,对比了其与常见的半金属相碲化钼接触的顶栅转移特性曲线,如图6所示,在相同栅压下,半金属相碲化钨接触的器件源漏电流大小数倍高于半金属相碲化钼接触的器件,证明了本发明方法使用的半金属相碲化钨接触的接触电阻更低。
最后需要注意的是,公布实施例的目的在于帮助进一步理解本发明,但是本领域的技术人员可以理解:在不脱离本发明及所附的权利要求的精神和范围内,各种替换和修改都是可能的。因此,本发明不应局限于实施例所公开的内容,本发明要求保护的范围以权利要求书界定的范围为准。

Claims (9)

1.一种制备大面积高性能n型二维碲化钼场效应晶体管阵列的方法,包括以下步骤:
1)在衬底上生长一层1-30nm厚的半导体相碲化钼薄膜;
2)通过光刻、显影、刻蚀的方法图案化半导体相碲化钼薄膜,然后磁控溅射一层1-30nm厚的钨薄膜,剥离光刻胶后得到金属钨和半导体相碲化钼彼此相间的薄膜;
3)以碲单质为碲源,通过化学气相沉积法使步骤2)沉积的钨薄膜与碲反应生成半金属相碲化钨薄膜,从而在衬底上形成半金属相碲化钨和半导体相碲化钼彼此相间的薄膜;
4)通过光刻、显影和刻蚀的方法图案化步骤3)所形成的半金属相碲化钨和半导体相碲化钼彼此相间的薄膜,得到分立的以二维碲化钼为沟道、以二维碲化钨为电极的器件阵列;
5)通过原子层沉积技术在器件阵列上生长一层10-50nm厚的氧化铪薄膜,在形成电介质层的同时实现对二维碲化钼沟道的n型掺杂;
6)通过光刻和电子束蒸发或热蒸发的方法在氧化铪薄膜上制备图案化的顶栅金属电极,即获得大面积高性能n型二维碲化钼场效应晶体管阵列。
2.如权利要求1所述的方法,其特征在于,步骤1)中所述衬底为硅/氧化硅衬底或者绝缘衬底。
3.如权利要求1所述的方法,其特征在于,步骤1)在衬底上生长半导体相碲化钼薄膜的方法是:1a)在衬底上通过磁控溅射或电子束蒸发的方法制备一层钼薄膜;1b)以碲单质为碲源,通过化学气相沉积法使所述钼薄膜与碲反应,在衬底上生长大面积半导体相碲化钼薄膜。
4.如权利要求3所述的方法,其特征在于,步骤1b)在管式炉中进行,将步骤1a)得到的样品和适量碲粉末放入石英舟中,再将石英舟推至管式炉内进行化学气相沉积。
5.如权利要求3所述的方法,其特征在于,步骤1b)中进行化学气相沉积的温度控制在580~650℃,时间为1~4h,得到半导体相碲化钼薄膜。
6.如权利要求1所述的方法,其特征在于,步骤3)在管式炉中进行,将步骤2)得到的样品和适量碲粉末放入石英舟中,再将石英舟推至管式炉内进行化学气相沉积。
7.如权利要求1所述的方法,其特征在于,步骤3)进行化学气相沉积的温度控制在500~700℃,时间在0.5h以上,得到半金属相碲化钨薄膜。
8.如权利要求1所述的方法,其特征在于,步骤2)和步骤4)中刻蚀的方法为反应离子刻蚀或电感耦合等离子体刻蚀。
9.如权利要求1所述的方法,其特征在于,步骤5)进行原子层沉积的前驱体为四(二甲氨基)铪和水,反应温度为90-250℃。
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