CN114121780A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN114121780A
CN114121780A CN202110086521.3A CN202110086521A CN114121780A CN 114121780 A CN114121780 A CN 114121780A CN 202110086521 A CN202110086521 A CN 202110086521A CN 114121780 A CN114121780 A CN 114121780A
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metal layer
substrate
insulating film
semiconductor device
layer
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CN202110086521.3A
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堀内三成
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Kioxia Corp
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Kioxia Corp
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Abstract

本发明的实施方式涉及一种半导体装置及其制造方法。根据一实施方式，半导体装置具备：第1衬底；第1绝缘膜，设置在所述第1衬底上；以及第1插塞，设置在所述第1绝缘膜内。所述装置还具备：第1层，设置在所述第1绝缘膜上；以及第1金属层，在所述第1层内设置在所述第1插塞上，且电连接于所述第1插塞。所述装置还具备第2金属层，所述第2金属层包含设置在所述第1层内的第1部分、及设置在所述第1层上的第2部分，且电连接于所述第1金属层。

Description

半导体装置及其制造方法
相关申请案的引用
本申请案基于2020年08月31日提出申请的在先日本专利申请案第2020-146057号的优先权而主张优先权利益，通过引用将其全部内容并入本文中。
技术领域
本发明的实施方式涉及一种半导体装置及其制造方法。
背景技术
当在插塞上的层内形成开口部，在开口部内露出的插塞上形成金属层时，存在因用来形成开口部的蚀刻而导致插塞被蚀刻的问题。
发明内容
本发明提供一种能够在插塞上适宜地形成金属层的半导体装置及其制造方法。
根据一实施方式，半导体装置具备：第1衬底；第1绝缘膜，设置在所述第1衬底上；以及第1插塞，设置在所述第1绝缘膜内。所述装置还具备：第1层，设置在所述第1绝缘膜上；以及第1金属层，在所述第1层内设置在所述第1插塞上，且电连接于所述第1插塞。所述装置还具备第2金属层，所述第2金属层包含设置在所述第1层内的第1部分、及设置在所述第1层上的第2部分，且电连接于所述第1金属层。
根据所述构成，可提供一种能够在插塞上适宜地形成金属层的半导体装置及其制造方法。
附图说明
图1是表示第1实施方式的半导体装置的构造的剖视图。
图2是表示第1实施方式的半导体装置的构造的放大剖视图。
图3是表示第1实施方式的柱状部的构造的剖视图。
图4(a)、(b)是表示第1实施方式的半导体装置的制造方法的剖视图(1/8)。
图5(a)、(b)是表示第1实施方式的半导体装置的制造方法的剖视图(2/8)。
图6(a)、(b)是表示第1实施方式的半导体装置的制造方法的剖视图(3/8)。
图7是表示第1实施方式的半导体装置的制造方法的剖视图(4/8)。
图8是表示第1实施方式的半导体装置的制造方法的剖视图(5/8)。
图9(a)～(c)是表示第1实施方式的半导体装置的制造方法的剖视图(6/8)。
图10(a)～(c)是表示第1实施方式的半导体装置的制造方法的剖视图(7/8)。
图11(a)～(c)是表示第1实施方式的半导体装置的制造方法的剖视图(8/8)。
图12是表示第1实施方式的半导体装置的制造方法的另一剖视图。
图13是表示第2实施方式的半导体装置的构造的剖视图。
图14是表示第2实施方式的半导体装置的构造的放大剖视图。
图15(a)、(b)是表示第2实施方式的半导体装置的制造方法的剖视图。
图16是表示第2实施方式的半导体装置的制造方法的另一剖视图。
具体实施方式
以下，参考附图对本发明的实施方式进行说明。图1至图16中，对相同构成标附相同符号，省略重复说明。
(第1实施方式)图1是表示第1实施方式的半导体装置的构造的剖视图。图1的半导体装置是阵列区域1与电路区域2贴合而成的三维存储器。
图1示出相互垂直的X方向、Y方向、及Z方向。该说明书中，将+Z方向作为上方向处理，将-Z方向作为下方向处理。-Z方向可与重力方向一致，也可不与重力方向一致。
阵列区域1具备：包含多个存储单元的存储单元阵列11、存储单元阵列11上的衬底12、及存储单元阵列11下的层间绝缘膜13。衬底12例如为硅衬底等半导体衬底。层间绝缘膜13例如为氧化硅膜、或包含氧化硅膜及其它绝缘膜的积层膜。衬底12是第1层或第2衬底的例子。层间绝缘膜13是第1绝缘膜的例子。
电路区域2设置在阵列区域1下。符号S表示阵列区域1与电路区域2的贴合面。电路区域2具备层间绝缘膜14、及层间绝缘膜14下的衬底15。层间绝缘膜14例如为氧化硅膜、或包含氧化硅膜及其它绝缘膜的积层膜。衬底15例如为硅衬底等半导体衬底。衬底15是第1衬底的例子。层间绝缘膜14与层间绝缘膜13同为第1绝缘膜的例子。
阵列区域1具备多条字线WL作为存储单元阵列11内的多个电极层。图1表示存储单元阵列11的阶梯构造部21。各字线WL经由接触插塞22与字配线层23电连接。贯通所述多条字线WL的各柱状部CL经由孔塞24而与位线BL电连接。
电路区域2具备多个晶体管31。各晶体管31具备介隔栅极绝缘膜设置在衬底15上的栅极电极32、及设置在衬底15内的未图示的源极扩散层及漏极扩散层。另外，电路区域2具备：多个接触插塞33，设置在这些晶体管31的栅极电极32、源极扩散层或漏极扩散层上；配线层34，设置在这些接触插塞33上，且包含多条配线；以及配线层35，设置在配线层34上，且包含多条配线。
电路区域2还具备：配线层36，设置在配线层35上，且包含多条配线；多个孔塞37，设置在配线层36上；以及多个金属焊垫38，设置在这些孔塞37上。金属焊垫38例如为包含Cu(铜)层或Al(铝)层的金属层。电路区域2作为控制阵列区域1的动作的控制电路(逻辑电路)发挥功能。该控制电路包含晶体管31等，且电连接于金属焊垫38。
阵列区域1具备设置在金属焊垫38上的多个金属焊垫41、及设置在金属焊垫41上的多个孔塞42。另外，阵列区域1具备：配线层43，设置在这些孔塞42上，且包含多条配线；以及配线层44，设置在配线层43上，且包含多条配线。金属焊垫41例如为包含Cu层或Al层的金属层。所述位线BL包含在配线层44中。另外，所述控制电路经由金属焊垫41、38等电连接于存储单元阵列11，经由金属焊垫41、38等控制存储单元阵列11的动作。
阵列区域1还具备：多个孔塞45，设置在配线层44上；多个孔塞46，设置在这些孔塞45上；以及多个金属层47，设置在这些孔塞46上。孔塞46设置在层间绝缘膜13内，金属层47设置在衬底12内。各金属层47设置在对应的1个孔塞46上，且电连接于该孔塞46。孔塞46是第1插塞的例子，金属层47是第1金属层的例子。孔塞46及金属层47的更多详情将于下文进行叙述。
阵列区域1还具备设置在衬底12上的绝缘膜51、绝缘膜52、金属层53、及钝化膜54。
绝缘膜51形成在衬底12上。绝缘膜51例如为氧化硅膜。绝缘膜52包含形成在衬底12及绝缘膜51侧面的侧方部52a、及形成在绝缘膜51上表面的上方部52b。侧方部52a作为衬底12及绝缘膜51的侧壁绝缘膜发挥功能。绝缘膜52例如为氧化硅膜。绝缘膜51及绝缘膜52与衬底12同为第1层的例子，进而为第2绝缘膜的例子。
衬底12及绝缘膜51具备到达层间绝缘膜13的开口部。绝缘膜52在该开口部内形成在衬底12及绝缘膜51的侧面。金属层47配置在该开口部内。如下所述，本实施方式的金属层47在衬底12及绝缘膜51内通过蚀刻而形成开口部时作为蚀刻终止层发挥功能。由此，能够抑制因用来形成开口部的蚀刻而导致孔塞46被蚀刻。
金属层53包含：上方部53a，形成在层间绝缘膜13及金属层47的上表面；侧方部53b，形成在绝缘膜52的侧面；以及上方部53c，形成在绝缘膜52的上表面。上方部53a及侧方部53b配置在所述开口部内，上方部53c配置在所述开口部外。金属层53电连接于各金属层47。金属层53例如包含Al层。金属层53是第2金属层的例子。另外，上方部53a及侧方部53b是第1部分的例子，金属层53的上方部53c是第2部分的例子。
钝化膜54包含依次形成在绝缘膜52及金属层53上的绝缘膜54a、绝缘膜54b、及绝缘膜54c。绝缘膜54a例如为氧化硅膜。绝缘膜54b例如为氮化硅膜。绝缘膜54c例如为聚酰亚胺膜。
钝化膜54例如具有露出金属层53的上方部53c上表面的开口部P。露出于开口部P内的上方部53c作为图1的半导体装置的外部连接焊垫(接合垫)发挥功能。上方部53c可经由开口部P利用键合线、焊球、金属凸块等连接于安装衬底及其它装置。
图2是表示第1实施方式的半导体装置的构造的放大剖视图。图2示出所述孔塞46、金属层47、金属层53等。
本实施方式的孔塞46与金属层47含有不同的金属元素。各孔塞46例如包含含有W(钨)元素的单质金属层或化合物金属层。各金属层47例如包含含有Al(铝)元素、Hf(铪)元素、或Zr(锆)元素的单质金属层或化合物金属层。本实施方式中，各孔塞46包含W层，各金属层47包含Al层。孔塞46内的金属元素是第1金属元素的例子。金属层47内的金属元素是第2金属元素的例子。此外，当金属层47如下所述将金属原子注入到衬底12内而形成时，各金属层47还包含衬底12中包含的元素(例如硅元素)。
金属层47在衬底12及绝缘膜51内通过蚀刻而形成开口部时作为蚀刻终止层发挥功能。由此，能够抑制因用来形成开口部的蚀刻而导致孔塞46被蚀刻。本实施方式中，孔塞46与金属层47具有不同的金属元素，因此，可使金属层47作为用来抑制孔塞46的蚀刻的蚀刻终止层发挥功能。
此外，金属层47可通过用来形成开口部的蚀刻或之后的蚀刻来完全地去除。在此情况下，金属层53通过以与各孔塞46的上表面相接的方式形成而直接电连接于各孔塞46。另一方面，图2所示的金属层53通过介隔金属层47形成在各孔塞46上，而经由金属层47电连接于各孔塞46。
本实施方式的半导体装置具备N个(N为2以上的整数)孔塞46，且在这些孔塞46上具备N个金属层47。这样，本实施方式的孔塞46与金属层47一一对应。图2示出这些孔塞46与金属层47中的2个孔塞46与2个金属层47。本实施方式的N的值例如为100～10000。本实施方式的金属层47可以任何形态配置，例如在XY平面内以正方格子的形式配置成二维阵列状。本实施方式的各金属层47的平面形状例如为圆形。
图3是表示第1实施方式的柱状部CL的构造的剖视图。
如图3所示，存储单元阵列11具备交替积层在层间绝缘膜13(参考图1)上的多条字线WL及多个绝缘层61。字线WL例如为包含W(钨)层的金属层。绝缘层61例如为氧化硅膜。
柱状部CL依次包含阻挡绝缘膜62、电荷储存层63、隧道绝缘膜64、通道半导体层65、及核心绝缘膜66。电荷储存层63例如为氮化硅膜，介隔阻挡绝缘膜62形成在字线WL及绝缘层61的侧面。电荷储存层63也可为多晶硅层等半导体层。通道半导体层65例如为多晶硅层，介隔隧道绝缘膜64形成在电荷储存层63的侧面。阻挡绝缘膜62、隧道绝缘膜64、及核心绝缘膜66例如为氧化硅膜或金属绝缘膜。
图4至图11是表示第1实施方式的半导体装置的制造方法的剖视图。如下所述，本实施方式的半导体装置是通过将包含多个阵列区域1的阵列晶圆W1与包含多个电路区域2的电路晶圆W2贴合而制造。
首先，准备衬底12，在衬底12上形成存储单元阵列11、及作为层间绝缘膜13的一部分的绝缘膜13a(图4(a))。图4(a)还示出存储单元阵列11中包含的字线WL、柱状部CL、及阶梯构造部21。绝缘膜13a是第1绝缘膜的例子。
接下来，在绝缘膜13a上形成硬质遮罩层71，通过将硬质遮罩层71用作遮罩的RIE(Reactive Ion Etching，反应性离子蚀刻)在绝缘膜13a内形成开口部H1、H2、H3(图4(b))。开口部H1以到达衬底12的方式形成。开口部H2以到达字线WL的方式形成。开口部H3以到达柱状部CL的方式形成。硬质遮罩层71例如为碳层。硬质遮罩层71在之后通过灰化而去除。开口部H1是第2开口部的例子。
接下来，在绝缘膜13a上形成抗蚀层72(图5(a))。抗蚀层72以开口部H1不被抗蚀层72所覆盖的方式形成。接下来，通过将抗蚀层72用作遮罩的离子注入，将金属原子注入到露出于开口部H1内的衬底12内(图5(a))。结果，在露出于开口部H1内的衬底12内形成金属层47。图5(a)例示形成在露出于2个开口部H1内的衬底12内的2个金属层47。所述金属原子例如为Al原子，在此情况下，金属层47成为包含Al原子的层。金属层47内的Al原子的面浓度例如约为1.0×1016个/cm2。所述金属原子也可为Hf原子或Zr原子。抗蚀层72在之后通过灰化而去除。
接下来，在衬底12的整个面形成金属材料层，通过CMP(Chemical MechanicalPolishing，化学机械抛光)将金属材料层的表面平坦化(图5(b))。结果，在开口部H1、H2、H3内分别由所述金属材料层形成孔塞46、接触插塞22、孔塞24。例如在各开口部H1内，在1个金属层47上形成1个孔塞46。所述金属材料层例如为包含阻障金属层及插塞材层的积层膜。阻障金属层例如包含Ti(钛)元素或Ta(钽)元素。插塞材层例如包含W元素，此处为W层。
接下来，在衬底12上，介隔绝缘膜13a等形成作为层间绝缘膜13的一部分的绝缘膜13b、字配线层23、位线BL、孔塞45、配线层44、配线43、孔塞42、金属焊垫41等(图6(a))。以此方式制造阵列晶圆W1。图6(a)示出阵列晶圆W1的上表面S1。
接下来，准备衬底15，在衬底15上形成层间绝缘膜14、晶体管31、栅极电极32、接触插塞33、配线层34、配线层35、配线层36、孔塞37、金属焊垫38等(图6(b))。以此方式制造电路晶圆W2。图6(b)示出电路晶圆W2的上表面S2。
接下来，将阵列晶圆W1与电路晶圆W2贴合(图7)。具体而言，将衬底12与衬底15介隔存储单元阵列11、层间绝缘膜13、层间绝缘膜14、晶体管31、孔塞46、金属层47等而贴合。图7中，使阵列晶圆W1的上下方向反转，将阵列晶圆W1与电路晶圆W2贴合。结果，衬底12配置在衬底15的上方。在该贴合步骤中，层间绝缘膜13与层间绝缘膜14通过机械压力而粘接，金属焊垫41与金属焊垫38通过退火而接合。
接下来，通过背面研磨及湿式蚀刻将衬底12薄化(图8)。结果，衬底12的厚度变薄。
图9(a)至图11(c)是表示所述衬底12、孔塞46、金属层47等的放大剖视图。
接下来，在衬底12上形成绝缘膜51(图9(a))。接下来，通过RIE对金属层47上方的绝缘膜51进行蚀刻(图9(b))。结果，在绝缘膜51内形成开口部H4，在开口部H4内露出衬底12。接下来，通过RIE对露出于开口部H4内的衬底12进行蚀刻(图9(c))。结果，开口部H4也形成在衬底12内，在开口部H4内露出层间绝缘膜13及金属层47。开口部H4是第1开口部的例子。
金属层47在进行图9(c)的RIE时作为蚀刻终止层发挥功能。由此，能够抑制因该RIE而导致孔塞46被蚀刻。本实施方式中，孔塞46与金属层47含有不同的金属元素，因此，可使金属层47作为用来抑制孔塞46的蚀刻的蚀刻终止层发挥功能。
图9(c)的RIE例如使用包含F(氟)元素的蚀刻气体进行。该蚀刻气体的例子为SF6气体或CF4气体(S表示硫，C表示碳)。该蚀刻气体也可包含SF6气体及/或CF4气体、以及O2气体(O表示氧)。
包含F元素的蚀刻气体能够高速蚀刻衬底12。在此情况下，如果在孔塞46上未形成金属层47，那么孔塞46也会与衬底12一起被高速蚀刻。根据本实施方式，通过在进行图9(c)的RIE之前预先在孔塞46上形成金属层47，能够抑制孔塞46的蚀刻。
因此，理想的是，金属层47具有对包含F元素的蚀刻气体较高的耐受性。这种金属层47的例子为包含Al元素、Hf元素、或Zr元素的单质金属层或化合物金属层。由此，既能利用包含F元素的蚀刻气体高速蚀刻衬底12，又能抑制孔塞46的蚀刻。
接下来，在衬底12的整个面形成绝缘膜52(图10(a))。结果，在金属层47、层间绝缘膜13、衬底12、及绝缘膜51的表面形成绝缘膜52。
接下来，去除金属层47及层间绝缘膜13上的绝缘膜52(图10(b))。结果，金属层47及层间绝缘膜13的表面在开口部H4内露出。另外，绝缘膜52被加工成包含侧方部52a及上方部52b的形状。图10(b)的步骤例如通过如下方式进行：用抗蚀层覆盖绝缘膜52的一部分(相当于侧方部52a与上方部52b的部分)，通过蚀刻来去除绝缘膜52的其它部分。
接下来，在衬底12的整个面形成金属层53(图10(c))。结果，在金属层47、层间绝缘膜13、及绝缘膜52的表面形成金属层53。
接下来，去除绝缘膜52的上表面的金属层53的一部分(图11(a))。结果，金属层53被加工成包含上方部53a、侧方部53b及上方部53c的形状。
此外，金属层47可在进行图10(c)的步骤之前完全去除。在此情况下，金属层53通过以与各孔塞46的上表面相接的方式形成而直接电连接于各孔塞46。另一方面，图11(a)所示的金属层53通过介隔金属层47形成在各孔塞46上，而经由金属层47电连接于各孔塞46。
接下来，在衬底12的整个面依次形成钝化膜54的绝缘膜54a、54b、54c(图11(b))。结果，在绝缘膜52及金属层53的表面形成钝化膜54。
接下来，去除上方部53c上表面的钝化膜54的一部分(图11(c))。结果，在钝化膜54内形成开口部P，在开口部P内露出上方部53c的上表面。露出于开口部P内的上方部53c作为接合垫发挥功能。
然后，通过切割将阵列晶圆W1及电路晶圆W2切断成多个芯片。这些芯片以各芯片包含1个阵列区域1及1个电路区域2的方式切断。以此方式制造图1的半导体装置。
图12是表示第1实施方式的半导体装置的制造方法的另一剖视图。
图12是与图9(c)对应的剖视图，表示在衬底12内形成开口部H4的步骤。本实施方式中，在孔塞46上形成有金属层47。
图12的步骤是使用包含SF6气体及O2气体的蚀刻气体来进行。图12示出由SF6气体产生的SF5 +及F＊。该蚀刻气体蚀刻衬底12的速度较快。因此，本实施方式中，在衬底12较厚的情况下，也能够在短时间内在衬底12形成开口部H4。
图12的步骤进而在孔塞46上形成有金属层47的状态下进行。本实施方式的金属层47包含含有Al元素、Hf元素、或Zr元素的单质金属层或化合物金属层，具有对包含F元素的蚀刻气体较高的耐受性。因此，本实施方式中，在衬底12较薄的情况下，也能够抑制孔塞46的蚀刻。
这样，根据本实施方式，能够容易地同时实现在短时间内在衬底12形成开口部H4以及抑制孔塞46的蚀刻。
此外，如图12所示，本实施方式的开口部H4也可以衬底12及绝缘膜51的侧面成为倾斜面的方式进行。
如上所述，本实施方式的衬底12的开口部H4在预先在孔塞46上设置金属层47的状态下形成。因此，根据本实施方式，能够在孔塞46上适宜地形成金属层53。例如，能够在未经用来形成开口部H4的RIE蚀刻的孔塞46上，介隔金属层47形成金属层53。另外，能够在短时间内进行该RIE。
(第2实施方式)图13是表示第2实施方式的半导体装置的构造的剖视图。
本实施方式的半导体装置具备与图1所示的第1实施方式的半导体装置相同的构成要素。但，第1实施方式的半导体装置在多个孔塞46上具备多个金属层47，与此相对，本实施方式的半导体装置在多个孔塞46上具备1个金属层47。本实施方式的金属层53形成在该金属层47上。
图14是表示第2实施方式的半导体装置的构造的放大剖视图。图14示出所述孔塞46、金属层47、金属层53等。
本实施方式的孔塞46及金属层47与第1实施方式同样地，含有不同的金属元素。例如，各孔塞46包含W层，各金属层47包含Al层。本实施方式中，孔塞46与金属层47含有不同的金属元素，因此，可将金属层47作为用来抑制孔塞46的蚀刻的蚀刻终止层发挥功能。
本实施方式的半导体装置具备N个(N为2以上的整数)孔塞46，且在这些孔塞46上具备1个金属层47。本实施方式的N的值与第1实施方式同样地，例如为100～10000。本实施方式的孔塞46可以任何形态配置，例如在XY截面内以正方格子的形式配置成二维阵列状。本实施方式的各金属层47的平面形状例如为正方形或长方形等四边形。
此外，本实施方式的半导体装置也可在N个孔塞46上具备个数少于N个的金属层47。例如，本实施方式的半导体装置也可在k×n个孔塞46上具备n个金属层47(k及n为2以上的整数)。在此情况下，理想的是将各金属层47配置在对应的k个孔塞46上。
图15是表示第2实施方式的半导体装置的制造方法的剖视图。本实施方式的半导体装置也与第1实施方式同样地，是通过将包含多个阵列区域1的阵列晶圆W1与包含多个电路区域2的电路晶圆W2贴合而制造。
首先，准备衬底12，在衬底12内形成金属层47(图15(a))。该金属层47例如通过利用光刻法及RIE在衬底12内形成凹部，并将金属层47嵌埋到该凹部内而形成在衬底12内。金属层47的形成方法例如为等离子体CVD(Chemical Vapor Deposition，化学气相沉积)或溅镀。在此情况下，金属层47例如通过以下方式形成，即，利用CVD或溅镀在衬底12的凹部内部及外部形成金属层47，并利用回蚀来去除衬底12的凹部外部的金属层47。金属层47例如为Al层、Hf层、或Zr层。
接下来，在衬底12及金属层47上形成存储单元阵列11、及作为层间绝缘膜13的一部分的绝缘膜13a(图15(b))。图15(b)还示出存储单元阵列11中包含的字线WL、柱状部CL、及阶梯构造部21。
接下来，在绝缘膜13a上形成硬质遮罩层71，通过将硬质遮罩层71用作遮罩的RIE在绝缘膜13a内形成开口部H1～H3(图15(b))。开口部H1以到达金属层47的方式形成。开口部H2以到达字线WL的方式形成。开口部H3以到达柱状部CL的方式形成。本实施方式中，多个开口部H1以到达1个金属层47的方式形成，在各开口部H1内露出金属层47。
本实施方式中，此后省略图5(a)的步骤，实施图5(b)至图11(b)的步骤。在图5(b)的步骤中，在露出于各开口部H1内的金属层47上形成孔塞46。在图9(c)的步骤中，在开口部H4内露出1个金属层47。在图10(c)的步骤中，在该金属层47上形成金属层53。以此方式制造图13的半导体装置。
图16是表示第2实施方式的半导体装置的制造方法的另一剖视图。
图16是与图9(c)对应的剖视图，表示在衬底12内形成开口部H4的步骤。本实施方式中，在多个孔塞46上形成有1个金属层47。
图16的步骤是使用包含SF6气体及O2气体的蚀刻气体进行。因此，本实施方式中，在衬底12较厚的情况下，也能够在短时间内在衬底12形成开口部H4。
图16的步骤进而在孔塞46上形成有金属层47的状态下进行。因此，本实施方式中，在衬底12较薄的情况下，也能够抑制孔塞46的蚀刻。
这样，根据本实施方式，与第1实施方式同样地，能够容易地同时实现在短时间内在衬底12形成开口部H4、以及抑制孔塞46的蚀刻。
如上所述，本实施方式的衬底12的开口部H4在预先在多个孔塞46上形成1个金属层47的状态下形成。因此，根据本实施方式，与第1实施方式同样地，能够在孔塞46上适宜地形成金属层53。例如，能够在未经用来形成开口部H4的RIE蚀刻的孔塞46上，介隔金属层47形成金属层53。另外，能够在短时间内进行该RIE。
此外，本实施方式中，在图15(a)的步骤中，在衬底12内形成多个金属层47，在图15(b)的步骤中，可在各金属层47上形成对应的1个开口部H1。由此，能够利用等离子体CVD或溅镀而不是离子注入来形成像第1实施方式这样的多个金属层47。反之，本实施方式中，在图15(a)的步骤中，可利用离子注入而不是等离子体CVD或溅镀来形成1个金属层47。
以上，对若干实施方式进行了说明，但这些实施方式只是作为例子提出的，并不意图限定发明的范围。本说明书中说明的新颖的装置及方法能够以其它各种方式实施。另外，对于本说明书中说明的装置及方法的方式，能够在不脱离发明主旨的范围内进行各种省略、替换、变更。随附的权利要求书及其均等的范围意图包括像包含在发明的范围或主旨内这样的方式及变化例。

Claims (19)

1.一种半导体装置，具备：第1衬底；第1绝缘膜，设置在所述第1衬底上；第1插塞，设置在所述第1绝缘膜内；第1层，设置在所述第1绝缘膜上；第1金属层，在所述第1层内设置在所述第1插塞上，且电连接于所述第1插塞；以及第2金属层，包含设置在所述第1层内的第1部分、及设置在所述第1层上的第2部分，且电连接于所述第1金属层。
2.根据权利要求1所述的半导体装置，其中所述第1层包含第2衬底。
3.根据权利要求2所述的半导体装置，其中所述第1层还包含设置在所述第2衬底的上表面及侧面的第2绝缘膜。
4.根据权利要求1至3中任一项所述的半导体装置，其中所述第1插塞包含第1金属元素，所述第1金属层包含与所述第1金属元素不同的第2金属元素。
5.根据权利要求4所述的半导体装置，其中所述第1金属元素为钨(W)元素，所述第2金属元素为铝(Al)元素、铪(Hf)元素、或锆(Zr)元素。
6.根据权利要求1至3中任一项所述的半导体装置，其具备N个(N为2以上的整数)插塞作为所述第1插塞，具备设置在所述N个插塞上的N个金属层作为所述第1金属层。
7.根据权利要求1至3中任一项所述的半导体装置，其具备N个(N为2以上的整数)插塞作为所述第1插塞，具备设置在所述N个插塞上的1个金属层作为所述第1金属层。
8.根据权利要求1至3中任一项所述的半导体装置，其中所述第2金属层的所述第2部分包含接合垫。
9.一种半导体装置，具备：第1绝缘膜；第1插塞，设置在所述第1绝缘膜内；衬底，设置在所述第1绝缘膜上；第1金属层，在所述衬底内设置在所述第1插塞上，且电连接于所述第1插塞；以及第2金属层，包含设置在所述衬底内的第1部分、及设置在所述衬底上的第2部分，且电连接于所述第1金属层。
10.根据权利要求9所述的半导体装置，其还具备设置在所述衬底的上表面及侧面的第2绝缘膜，且所述第1部分设置在所述衬底及所述第2绝缘膜内，所述第2部分设置在所述衬底及所述第2绝缘膜上。
11.一种半导体装置的制造方法，包括：准备第1衬底及第2衬底，在所述第2衬底内形成第1金属层，在所述第1金属层上形成第1插塞，使所述第1衬底与所述第2衬底介隔所述第1插塞及所述第1金属层而贴合，在所述第1衬底的上方配置所述第2衬底，在所述第2衬底内形成第1开口部，在所述第1开口部内露出所述第1金属层，在所述第1开口部内形成第2金属层，使所述第2金属层电连接于所述第1插塞。
12.根据权利要求11所述的半导体装置的制造方法，其中所述第1开口部是使用包含氟(F)元素的气体而形成。
13.根据权利要求11或12所述的半导体装置的制造方法，其中所述第1插塞包含第1金属元素，所述第1金属层包含与所述第1金属元素不同的第2金属元素。
14.根据权利要求13所述的半导体装置的制造方法，其中所述第1金属元素为钨(W)元素，所述第2金属元素为铝(Al)元素、铪(Hf)元素、或锆(Zr)元素。
15.根据权利要求11或12所述的半导体装置的制造方法，其中所述第1金属层是通过将金属原子注入到所述第1衬底内而形成在所述第1衬底内。
16.根据权利要求11或12所述的半导体装置的制造方法，其中所述第1金属层是通过在所述第1衬底内形成凹部，并将所述第1金属层嵌埋到所述凹部内而形成在所述第1衬底内。
17.根据权利要求11或12所述的半导体装置的制造方法，其中所述第1金属层及所述第1插塞是通过如下方式而形成：在所述第2衬底上形成第1绝缘膜，在所述第1绝缘膜内形成第2开口部而在所述第2开口部内露出所述第2衬底，在露出于所述第2开口部内的所述第2衬底内形成所述第1金属层，在所述第2开口部内形成所述第1插塞。
18.根据权利要求11或12所述的半导体装置的制造方法，其中所述第1金属层及所述第1插塞是通过如下方式而形成：在所述第2衬底内形成所述第1金属层，在所述第2衬底及所述第1金属层上形成第1绝缘膜，在所述第1绝缘膜内形成第2开口部而在所述第2开口部内露出所述第1金属层，在露出于所述第2开口部内的所述第1金属层上形成所述第1插塞。
19.根据权利要求11或12所述的半导体装置的制造方法，其中所述第2金属层直接电连接于所述第1插塞，或经由所述第1金属层电连接于所述第1插塞。
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