TW202211423A - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TW202211423A
TW202211423A TW110100986A TW110100986A TW202211423A TW 202211423 A TW202211423 A TW 202211423A TW 110100986 A TW110100986 A TW 110100986A TW 110100986 A TW110100986 A TW 110100986A TW 202211423 A TW202211423 A TW 202211423A
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metal layer
substrate
insulating film
layer
semiconductor device
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TW110100986A
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TWI786514B (zh
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堀內三成
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日商鎧俠股份有限公司
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Abstract

根據一實施方式，半導體裝置具備：第1基板；第1絕緣膜，其設置於上述第1基板上；及第1插塞，其設置於上述第1絕緣膜內。上述裝置進而具備：第1層，其設置於上述第1絕緣膜上；及第1金屬層，其在上述第1層內設置於上述第1插塞上，且電性連接於上述第1插塞。上述裝置進而具備第2金屬層，該第2金屬層包含設置於上述第1層內之第1部分、及設置於上述第1層上之第2部分，且電性連接於上述第1金屬層。

Description

半導體裝置及其製造方法
本發明之實施方式係關於一種半導體裝置及其製造方法。
當於插塞上之層內形成開口部，於開口部內露出之插塞上形成金屬層時，存在因用以形成開口部之蝕刻而導致插塞被蝕刻之問題。
本發明提供一種能夠於插塞上適宜地形成金屬層之半導體裝置及其製造方法。
根據一實施方式，半導體裝置具備：第1基板；第1絕緣膜，其設置於上述第1基板上；及第1插塞，其設置於上述第1絕緣膜內。上述裝置進而具備：第1層，其設置於上述第1絕緣膜上；及第1金屬層，其在上述第1層內設置於上述第1插塞上，且電性連接於上述第1插塞。上述裝置進而具備第2金屬層，該第2金屬層包含設置於上述第1層內之第1部分、及設置於上述第1層上之第2部分，且電性連接於上述第1金屬層。
根據上述構成，可提供一種能夠於插塞上適宜地形成金屬層之半導體裝置及其製造方法。
以下，參照附圖對本發明之實施方式進行說明。圖1至圖16中，對相同構成標附相同符號，省略重複說明。
(第1實施方式) 圖1係表示第1實施方式之半導體裝置之構造之剖視圖。圖1之半導體裝置係陣列區域1與電路區域2貼合而成之三維記憶體。
圖1示出相互垂直之X方向、Y方向、及Z方向。該說明書中，將+Z方向作為上方向處理，將-Z方向作為下方向處理。-Z方向可與重力方向一致，亦可不與重力方向一致。
陣列區域1具備：包含複數個記憶胞之記憶胞陣列11、記憶胞陣列11上之基板12、及記憶胞陣列11下之層間絕緣膜13。基板12例如為矽基板等半導體基板。層間絕緣膜13例如為氧化矽膜、或包含氧化矽膜及其他絕緣膜之積層膜。基板12係第1層或第2基板之例。層間絕緣膜13係第1絕緣膜之例。
電路區域2設置於陣列區域1下。符號S表示陣列區域1與電路區域2之貼合面。電路區域2具備層間絕緣膜14、及層間絕緣膜14下之基板15。層間絕緣膜14例如為氧化矽膜、或包含氧化矽膜及其他絕緣膜之積層膜。基板15例如為矽基板等半導體基板。基板15係第1基板之例。層間絕緣膜14與層間絕緣膜13同為第1絕緣膜之例。
陣列區域1具備複數條字元線WL作為記憶胞陣列11內之複數個電極層。圖1表示記憶胞陣列11之階梯構造部21。各字元線WL經由接觸插塞22與字元配線層23電性連接。貫通上述複數條字元線WL之各柱狀部CL經由貫孔插塞24而與位元線BL電性連接。
電路區域2具備複數個電晶體31。各電晶體31具備介隔閘極絕緣膜設置於基板15上之閘極電極32、及設置於基板15內之未圖示之源極擴散層及汲極擴散層。又，電路區域2具備：複數個接觸插塞33，其等設置於該等電晶體31之閘極電極32、源極擴散層或汲極擴散層上；配線層34，其設置於該等接觸插塞33上，且包含複數條配線；及配線層35，其設置於配線層34上，且包含複數條配線。
電路區域2進而具備：配線層36，其設置於配線層35上，且包含複數條配線；複數個貫孔插塞37，其等設置於配線層36上；及複數個金屬焊墊38，其等設置於該等貫孔插塞37上。金屬焊墊38例如為包含Cu(銅)層或Al(鋁)層之金屬層。電路區域2作為控制陣列區域1之動作之控制電路(邏輯電路)發揮功能。該控制電路包含電晶體31等，且電性連接於金屬焊墊38。
陣列區域1具備設置於金屬焊墊38上之複數個金屬焊墊41、及設置於金屬焊墊41上之複數個貫孔插塞42。又，陣列區域1具備：配線層43，其設置於該等貫孔插塞42上，且包含複數條配線；及配線層44，其設置於配線層43上，且包含複數條配線。金屬焊墊41例如為包含Cu層或Al層之金屬層。上述位元線BL包含於配線層44中。又，上述控制電路經由金屬焊墊41、38等電性連接於記憶胞陣列11，經由金屬焊墊41、38等控制記憶胞陣列11之動作。
陣列區域1進而具備：複數個貫孔插塞45，其等設置於配線層44上；複數個貫孔插塞46，其等設置於該等貫孔插塞45上；及複數個金屬層47，其等設置於該等貫孔插塞46上。貫孔插塞46設置於層間絕緣膜13內，金屬層47設置於基板12內。各金屬層47設置於對應之1個貫孔插塞46上，且電性連接於該貫孔插塞46。貫孔插塞46係第1插塞之例，金屬層47係第1金屬層之例。貫孔插塞46及金屬層47之更多詳情將於下文進行敍述。
陣列區域1進而具備設置於基板12上之絕緣膜51、絕緣膜52、金屬層53、及鈍化膜54。
絕緣膜51形成於基板12上。絕緣膜51例如為氧化矽膜。絕緣膜52包含形成於基板12及絕緣膜51側面之側方部52a、及形成於絕緣膜51上表面之上方部52b。側方部52a作為基板12及絕緣膜51之側壁絕緣膜發揮功能。絕緣膜52例如為氧化矽膜。絕緣膜51及絕緣膜52與基板12同為第1層之例，進而為第2絕緣膜之例。
基板12及絕緣膜51具備到達層間絕緣膜13之開口部。絕緣膜52在該開口部內形成於基板12及絕緣膜51之側面。金屬層47配置於該開口部內。如下所述，本實施方式之金屬層47在基板12及絕緣膜51內藉由蝕刻而形成開口部時作為蝕刻終止層發揮功能。藉此，能夠抑制因用以形成開口部之蝕刻而導致貫孔插塞46被蝕刻。
金屬層53包含：上方部53a，其形成於層間絕緣膜13及金屬層47之上表面；側方部53b，其形成於絕緣膜52之側面；及上方部53c，其形成於絕緣膜52之上表面。上方部53a及側方部53b配置於上述開口部內，上方部53c配置於上述開口部外。金屬層53電性連接於各金屬層47。金屬層53例如包含Al層。金屬層53係第2金屬層之例。又，上方部53a及側方部53b係第1部分之例，金屬層53之上方部53c係第2部分之例。
鈍化膜54包含依序形成於絕緣膜52及金屬層53上之絕緣膜54a、絕緣膜54b、及絕緣膜54c。絕緣膜54a例如為氧化矽膜。絕緣膜54b例如為氮化矽膜。絕緣膜54c例如為聚醯亞胺膜。
鈍化膜54例如具有露出金屬層53之上方部53c上表面之開口部P。露出於開口部P內之上方部53c作為圖1之半導體裝置之外部連接焊墊(接合墊)發揮功能。上方部53c可經由開口部P利用接合線、焊球、金屬凸塊等連接於安裝基板及其他裝置。
圖2係表示第1實施方式之半導體裝置之構造之放大剖視圖。圖2示出上述貫孔插塞46、金屬層47、金屬層53等。
本實施方式之貫孔插塞46與金屬層47含有不同之金屬元素。各貫孔插塞46例如包含含有W(鎢)元素之單質金屬層或化合物金屬層。各金屬層47例如包含含有Al(鋁)元素、Hf(鉿)元素、或Zr(鋯)元素之單質金屬層或化合物金屬層。本實施方式中，各貫孔插塞46包含W層，各金屬層47包含Al層。貫孔插塞46內之金屬元素係第1金屬元素之例。金屬層47內之金屬元素係第2金屬元素之例。再者，當金屬層47如下所述將金屬原子注入至基板12內而形成時，各金屬層47進而包含基板12中包含之元素(例如矽元素)。
金屬層47於基板12及絕緣膜51內藉由蝕刻而形成開口部時作為蝕刻終止層發揮功能。藉此，能夠抑制因用以形成開口部之蝕刻而導致貫孔插塞46被蝕刻。本實施方式中，貫孔插塞46與金屬層47含有不同之金屬元素，因此，可使金屬層47作為用以抑制貫孔插塞46之蝕刻之蝕刻終止層發揮功能。
再者，金屬層47可藉由用以形成開口部之蝕刻或其後之蝕刻來完全地去除。於此情形時，金屬層53藉由以與各貫孔插塞46之上表面相接之方式形成而直接電性連接於各貫孔插塞46。另一方面，圖2所示之金屬層53藉由介隔金屬層47形成於各貫孔插塞46上，而經由金屬層47電性連接於各貫孔插塞46。
本實施方式之半導體裝置具備N個(N為2以上之整數)貫孔插塞46，且在該等貫孔插塞46上具備N個金屬層47。如此，本實施方式之貫孔插塞46與金屬層47一一對應。圖2示出該等貫孔插塞46與金屬層47中之2個貫孔插塞46與2個金屬層47。本實施方式之N之值例如為100～10000。本實施方式之金屬層47可以任何態樣配置，例如於XY平面內以正方格子之形式配置成二維陣列狀。本實施方式之各金屬層47之平面形狀例如為圓形。
圖3係表示第1實施方式之柱狀部CL之構造之剖視圖。
如圖3所示，記憶胞陣列11具備交替積層於層間絕緣膜13(參照圖1)上之複數條字元線WL及複數個絕緣層61。字元線WL例如為包含W(鎢)層之金屬層。絕緣層61例如為氧化矽膜。
柱狀部CL依序包含阻擋絕緣膜62、電荷儲存層63、隧道絕緣膜64、通道半導體層65、及芯絕緣膜66。電荷儲存層63例如為氮化矽膜，介隔阻擋絕緣膜62形成於字元線WL及絕緣層61之側面。電荷儲存層63亦可為多晶矽層等半導體層。通道半導體層65例如為多晶矽層，介隔隧道絕緣膜64形成於電荷儲存層63之側面。阻擋絕緣膜62、隧道絕緣膜64、及芯絕緣膜66例如為氧化矽膜或金屬絕緣膜。
圖4至圖11係表示第1實施方式之半導體裝置之製造方法之剖視圖。如下所述，本實施方式之半導體裝置係藉由將包含複數個陣列區域1之陣列晶圓W1與包含複數個電路區域2之電路晶圓W2貼合而製造。
首先，準備基板12，於基板12上形成記憶胞陣列11、及作為層間絕緣膜13之一部分之絕緣膜13a(圖4(a))。圖4(a)進而示出記憶胞陣列11中包含之字元線WL、柱狀部CL、及階梯構造部21。絕緣膜13a係第1絕緣膜之例。
接下來，於絕緣膜13a上形成硬罩層71，藉由將硬罩層71用作遮罩之RIE(Reactive Ion Etching，反應性離子蝕刻)而於絕緣膜13a內形成開口部H1、H2、H3(圖4(b))。開口部H1以到達基板12之方式形成。開口部H2以到達字元線WL之方式形成。開口部H3以到達柱狀部CL之方式形成。硬罩層71例如為碳層。硬罩層71在之後藉由灰化而去除。開口部H1係第2開口部之例。
接下來，於絕緣膜13a上形成抗蝕層72(圖5(a))。抗蝕層72以開口部H1不被抗蝕層72所覆蓋之方式形成。接下來，藉由將抗蝕層72用作遮罩之離子注入，將金屬原子注入至露出於開口部H1內之基板12內(圖5(a))。結果，在露出於開口部H1內之基板12內形成金屬層47。圖5(a)例示形成在露出於2個開口部H1內之基板12內之2個金屬層47。上述金屬原子例如為Al原子，於此情形時，金屬層47成為包含Al原子之層。金屬層47內之Al原子之面濃度例如約為1.0×1016 個/cm2 。上述金屬原子亦可為Hf原子或Zr原子。抗蝕層72在之後藉由灰化而去除。
接下來，於基板12之整個面形成金屬材料層，藉由CMP(Chemical Mechanical Polishing，化學機械研磨)將金屬材料層之表面平坦化(圖5(b))。結果，於開口部H1、H2、H3內分別由上述金屬材料層形成貫孔插塞46、接觸插塞22、貫孔插塞24。例如在各開口部H1內，於1個金屬層47上形成1個貫孔插塞46。上述金屬材料層例如為包含阻障金屬層及插塞材層之積層膜。阻障金屬層例如包含Ti(鈦)元素或Ta(鉭)元素。插塞材層例如包含W元素，此處為W層。
接下來，於基板12上，介隔絕緣膜13a等形成作為層間絕緣膜13之一部分之絕緣膜13b、字元配線層23、位元線BL、貫孔插塞45、配線層44、配線43、貫孔插塞42、金屬焊墊41等(圖6(a))。以此方式製造陣列晶圓W1。圖6(a)示出陣列晶圓W1之上表面S1。
接下來，準備基板15，於基板15上形成層間絕緣膜14、電晶體31、閘極電極32、接觸插塞33、配線層34、配線層35、配線層36、貫孔插塞37、金屬焊墊38等(圖6(b))。以此方式製造電路晶圓W2。圖6(b)示出電路晶圓W2之上表面S2。
接下來，將陣列晶圓W1與電路晶圓W2貼合(圖7)。具體而言，將基板12與基板15介隔記憶胞陣列11、層間絕緣膜13、層間絕緣膜14、電晶體31、貫孔插塞46、金屬層47等而貼合。圖7中，使陣列晶圓W1之上下方向反轉，將陣列晶圓W1與電路晶圓W2貼合。結果，基板12配置於基板15之上方。在該貼合步驟中，層間絕緣膜13與層間絕緣膜14藉由機械壓力而接著，金屬焊墊41與金屬焊墊38藉由退火而接合。
接下來，藉由背面研磨及濕式蝕刻將基板12薄化(圖8)。結果，基板12之厚度變薄。
圖9(a)至圖11(c)係表示上述基板12、貫孔插塞46、金屬層47等之放大剖視圖。
接下來，於基板12上形成絕緣膜51(圖9(a))。接下來，藉由RIE對金屬層47上方之絕緣膜51進行蝕刻(圖9(b))。結果，於絕緣膜51內形成開口部H4，於開口部H4內露出基板12。接下來，藉由RIE對露出於開口部H4內之基板12進行蝕刻(圖9(c))。結果，開口部H4亦形成於基板12內，於開口部H4內露出層間絕緣膜13及金屬層47。開口部H4係第1開口部之例。
金屬層47於進行圖9(c)之RIE時作為蝕刻終止層發揮功能。藉此，能夠抑制因該RIE而導致貫孔插塞46被蝕刻。本實施方式中，貫孔插塞46與金屬層47含有不同之金屬元素，因此可使金屬層47作為用以抑制貫孔插塞46之蝕刻之蝕刻終止層發揮功能。
圖9(c)之RIE例如使用包含F(氟)元素之蝕刻氣體進行。該蝕刻氣體之例為SF6 氣體或CF4 氣體(S表示硫，C表示碳)。該蝕刻氣體亦可包含SF6 氣體及/或CF4 氣體、及O2 氣體(O表示氧)。
包含F元素之蝕刻氣體能夠高速蝕刻基板12。於此情形時，若在貫孔插塞46上未形成金屬層47，則貫孔插塞46亦會與基板12一起被高速蝕刻。根據本實施方式，藉由在進行圖9(c)之RIE之前預先於貫孔插塞46上形成金屬層47，能夠抑制貫孔插塞46之蝕刻。
因此，較理想為，金屬層47具有對包含F元素之蝕刻氣體較高之耐受性。此種金屬層47之例為包含Al元素、Hf元素、或Zr元素之單質金屬層或化合物金屬層。藉此，既能利用包含F元素之蝕刻氣體高速蝕刻基板12，又能抑制貫孔插塞46之蝕刻。
接下來，於基板12之整個面形成絕緣膜52(圖10(a))。結果，於金屬層47、層間絕緣膜13、基板12、及絕緣膜51之表面形成絕緣膜52。
接下來，去除金屬層47及層間絕緣膜13上之絕緣膜52(圖10(b))。結果，金屬層47及層間絕緣膜13之表面於開口部H4內露出。又，絕緣膜52被加工成包含側方部52a及上方部52b之形狀。圖10(b)之步驟例如藉由如下方式進行：用抗蝕層覆蓋絕緣膜52之一部分(相當於側方部52a與上方部52b之部分)，藉由蝕刻來去除絕緣膜52之其他部分。
接下來，於基板12之整個面形成金屬層53(圖10(c))。結果，於金屬層47、層間絕緣膜13、及絕緣膜52之表面形成金屬層53。
接下來，去除絕緣膜52之上表面之金屬層53之一部分(圖11(a))。結果，金屬層53被加工成包含上方部53a、側方部53b及上方部53c之形狀。
再者，金屬層47可於進行圖10(c)之步驟之前完全去除。於此情形時，金屬層53藉由以與各貫孔插塞46之上表面相接之方式形成而直接電性連接於各貫孔插塞46。另一方面，圖11(a)所示之金屬層53藉由介隔金屬層47形成於各貫孔插塞46上，而經由金屬層47電性連接於各貫孔插塞46。
接下來，於基板12之整個面依序形成鈍化膜54之絕緣膜54a、54b、54c(圖11(b))。結果，於絕緣膜52及金屬層53之表面形成鈍化膜54。
接下來，去除上方部53c上表面之鈍化膜54之一部分(圖11(c))。結果，於鈍化膜54內形成開口部P，於開口部P內露出上方部53c之上表面。露出於開口部P內之上方部53c作為接合墊發揮功能。
其後，藉由切割將陣列晶圓W1及電路晶圓W2切斷成複數個晶片。該等晶片以各晶片包含1個陣列區域1及1個電路區域2之方式切斷。以此方式製造圖1之半導體裝置。
圖12係表示第1實施方式之半導體裝置之製造方法之另一剖視圖。
圖12係與圖9(c)對應之剖視圖，表示於基板12內形成開口部H4之步驟。本實施方式中，於貫孔插塞46上形成有金屬層47。
圖12之步驟係使用包含SF6 氣體及O2 氣體之蝕刻氣體來進行。圖12示出由SF6 氣體產生之SF5 ＋ 及F＊ 。該蝕刻氣體蝕刻基板12之速度較快。因此，本實施方式中，在基板12較厚之情形時，亦能夠在短時間內於基板12形成開口部H4。
圖12之步驟進而於貫孔插塞46上形成有金屬層47之狀態下進行。本實施方式之金屬層47包含含有Al元素、Hf元素、或Zr元素之單質金屬層或化合物金屬層，具有對包含F元素之蝕刻氣體較高之耐受性。因此，本實施方式中，於基板12較薄之情形時，亦能夠抑制貫孔插塞46之蝕刻。
如此，根據本實施方式，能夠容易地同時實現在短時間內於基板12形成開口部H4以及抑制貫孔插塞46之蝕刻。
再者，如圖12所示，本實施方式之開口部H4亦可以基板12及絕緣膜51之側面成為傾斜面之方式進行。
如上所述，本實施方式之基板12之開口部H4在預先於貫孔插塞46上設置金屬層47之狀態下形成。因此，根據本實施方式，能夠於貫孔插塞46上適宜地形成金屬層53。例如，能夠於未經用以形成開口部H4之RIE蝕刻之貫孔插塞46上，介隔金屬層47形成金屬層53。又，能夠在短時間內進行該RIE。
(第2實施方式) 圖13係表示第2實施方式之半導體裝置之構造之剖視圖。
本實施方式之半導體裝置具備與圖1所示之第1實施方式之半導體裝置相同之構成要素。但，第1實施方式之半導體裝置於複數個貫孔插塞46上具備複數個金屬層47，與此相對，本實施方式之半導體裝置於複數個貫孔插塞46上具備1個金屬層47。本實施方式之金屬層53形成於該金屬層47上。
圖14係表示第2實施方式之半導體裝置之構造之放大剖視圖。圖14示出上述貫孔插塞46、金屬層47、金屬層53等。
本實施方式之貫孔插塞46及金屬層47與第1實施方式同樣地，含有不同之金屬元素。例如，各貫孔插塞46包含W層，各金屬層47包含Al層。本實施方式中，貫孔插塞46與金屬層47含有不同之金屬元素，因此，可將金屬層47作為用以抑制貫孔插塞46之蝕刻之蝕刻終止層發揮功能。
本實施方式之半導體裝置具備N個(N為2以上之整數)貫孔插塞46，且於該等貫孔插塞46上具備1個金屬層47。本實施方式之N之值與第1實施方式同樣地，例如為100～10000。本實施方式之貫孔插塞46可以任何態樣配置，例如在XY截面內以正方格子之形式配置成二維陣列狀。本實施方式之各金屬層47之平面形狀例如為正方形或長方形等四邊形。
再者，本實施方式之半導體裝置亦可於N個貫孔插塞46上具備個數少於N個之金屬層47。例如，本實施方式之半導體裝置亦可於k×n個貫孔插塞46上具備n個金屬層47(k及n為2以上之整數)。於此情形時，較理想為將各金屬層47配置於對應之k個貫孔插塞46上。
圖15係表示第2實施方式之半導體裝置之製造方法之剖視圖。本實施方式之半導體裝置亦與第1實施方式同樣，藉由將包含複數個陣列區域1之陣列晶圓W1與包含複數個電路區域2之電路晶圓W2貼合而製造。
首先，準備基板12，於基板12內形成金屬層47(圖15(a))。該金屬層47例如藉由利用微影法及RIE於基板12內形成凹部，並將金屬層47嵌埋至該凹部內而形成於基板12內。金屬層47之形成方法例如為電漿CVD(Chemical Vapor Deposition，化學氣相沈積)或濺鍍。於此情形時，金屬層47例如藉由以下方式形成，即，利用CVD或濺鍍於基板12之凹部內部及外部形成金屬層47，並利用回蝕來去除基板12之凹部外部之金屬層47。金屬層47例如為Al層、Hf層、或Zr層。
接下來，於基板12及金屬層47上形成記憶胞陣列11、及作為層間絕緣膜13之一部分之絕緣膜13a(圖15(b))。圖15(b)進而示出記憶胞陣列11中包含之字元線WL、柱狀部CL、及階梯構造部21。
接下來，於絕緣膜13a上形成硬罩層71，藉由將硬罩層71用作遮罩之RIE於絕緣膜13a內形成開口部H1～H3(圖15(b))。開口部H1以到達金屬層47之方式形成。開口部H2以到達字元線WL之方式形成。開口部H3以到達柱狀部CL之方式形成。本實施方式中，複數個開口部H1以到達1個金屬層47之方式形成，於各開口部H1內露出金屬層47。
本實施方式中，此後省略圖5(a)之步驟，實施圖5(b)至圖11(b)之步驟。圖5(b)之步驟中，在露出於各開口部H1內之金屬層47上形成貫孔插塞46。圖9(c)之步驟中，於開口部H4內露出1個金屬層47。圖10(c)之步驟中，於該金屬層47上形成金屬層53。以此方式製造圖13之半導體裝置。
圖16係表示第2實施方式之半導體裝置之製造方法之另一剖視圖。
圖16係與圖9(c)對應之剖視圖，表示於基板12內形成開口部H4之步驟。本實施方式中，於複數個貫孔插塞46上形成有1個金屬層47。
圖16之步驟係使用包含SF6 氣體及O2 氣體之蝕刻氣體進行。因此，本實施方式中，於基板12較厚之情形時，亦能夠在短時間內於基板12形成開口部H4。
圖16之步驟進而於貫孔插塞46上形成有金屬層47之狀態下進行。因此，本實施方式中，於基板12較薄之情形時，亦能夠抑制貫孔插塞46之蝕刻。
如此，根據本實施方式，與第1實施方式同樣地，能夠容易地同時實現在短時間內於基板12形成開口部H4、及抑制貫孔插塞46之蝕刻。
如上所述，本實施方式之基板12之開口部H4在預先於複數個貫孔插塞46上形成1個金屬層47之狀態下形成。因此，根據本實施方式，與第1實施方式同樣地，能夠於貫孔插塞46上適宜地形成金屬層53。例如，能夠於未經用以形成開口部H4之RIE蝕刻之貫孔插塞46上，介隔金屬層47形成金屬層53。又，能夠於短時間內進行該RIE。
再者，本實施方式中，可在圖15(a)之步驟中，於基板12內形成複數個金屬層47，在圖15(b)之步驟中，於各金屬層47上形成對應之1個開口部H1。藉此，能夠利用電漿CVD或濺鍍而非離子注入來形成如第1實施方式之複數個金屬層47。反之，本實施方式中，於圖15(a)之步驟中，可利用離子注入而非電漿CVD或濺鍍來形成1個金屬層47。
以上，對若干實施方式進行了說明，但該等實施方式僅作為示例提出，並不意圖限定發明之範圍。本說明書中說明之新穎之裝置及方法能夠以其他各種形態實施。又，對於本說明書中說明之裝置及方法之形態，能夠在不脫離發明主旨之範圍內進行各種省略、置換、變更。隨附之申請專利範圍及其均等之範圍意圖包括如包含於發明之範圍或主旨內之形態及變化例。
相關申請案之引用 本申請案基於2020年08月31日提出申請之在先日本專利申請案第2020-146057號之優先權而主張優先權利益，藉由引用將其全部內容併入本文中。
1:陣列區域 2:電路區域 11:記憶胞陣列 12:基板 13:層間絕緣膜 13a:絕緣膜 13b:絕緣膜 14:層間絕緣膜 15:基板 21:階梯構造部 22:接觸插塞 23:字元配線層 24:貫孔插塞 31:電晶體 32:閘極電極 33:接觸插塞 34:配線層 35:配線層 36:配線層 37:貫孔插塞 38:金屬焊墊 41:金屬焊墊 42:貫孔插塞 43:配線層 44:配線層 45:貫孔插塞 46:貫孔插塞 47:金屬層 51:絕緣膜 52:絕緣膜 52a:側方部 52b:上方部 53:金屬層 53a:上方部 53b:側方部 53c:上方部 54:鈍化膜 54a:絕緣膜 54b:絕緣膜 54c:絕緣膜 61:絕緣層 62:阻擋絕緣膜 63:電荷儲存層 64:隧道絕緣膜 65:通道半導體層 66:芯絕緣膜 71:硬罩層 72:抗蝕層 BL:位元線 CL:柱狀部 H1:開口部 H2:開口部 H3:開口部 H4:開口部 P:開口部 S:陣列區域與電路區域之貼合面 S1:上表面 S2:上表面 W1:陣列晶圓 W2:電路晶圓 WL:字元線
圖1係表示第1實施方式之半導體裝置之構造之剖視圖。  圖2係表示第1實施方式之半導體裝置之構造之放大剖視圖。  圖3係表示第1實施方式之柱狀部之構造之剖視圖。  圖4(a)、(b)係表示第1實施方式之半導體裝置之製造方法之剖視圖(1/8)。  圖5(a)、(b)係表示第1實施方式之半導體裝置之製造方法之剖視圖(2/8)。  圖6(a)、(b)係表示第1實施方式之半導體裝置之製造方法之剖視圖(3/8)。  圖7係表示第1實施方式之半導體裝置之製造方法之剖視圖(4/8)。  圖8係表示第1實施方式之半導體裝置之製造方法之剖視圖(5/8)。  圖9(a)～(c)係表示第1實施方式之半導體裝置之製造方法之剖視圖(6/8)。  圖10(a)～(c)係表示第1實施方式之半導體裝置之製造方法之剖視圖(7/8)。  圖11(a)～(c)係表示第1實施方式之半導體裝置之製造方法之剖視圖(8/8)。  圖12係表示第1實施方式之半導體裝置之製造方法之另一剖視圖。  圖13係表示第2實施方式之半導體裝置之構造之剖視圖。  圖14係表示第2實施方式之半導體裝置之構造之放大剖視圖。  圖15(a)、(b)係表示第2實施方式之半導體裝置之製造方法之剖視圖。  圖16係表示第2實施方式之半導體裝置之製造方法之另一剖視圖。
1:陣列區域
2:電路區域
11:記憶胞陣列
12:基板
13:層間絕緣膜
14:層間絕緣膜
15:基板
21:階梯構造部
22:接觸插塞
23:字元配線層
24:貫孔插塞
31:電晶體
32:閘極電極
33:接觸插塞
34:配線層
35:配線層
36:配線層
37:貫孔插塞
38:金屬焊墊
41:金屬焊墊
42:貫孔插塞
43:配線層
44:配線層
45:貫孔插塞
46:貫孔插塞
47:金屬層
51:絕緣膜
52:絕緣膜
52a:側方部
52b:上方部
53:金屬層
53a:上方部
53b:側方部
53c:上方部
54:鈍化膜
54a:絕緣膜
54b:絕緣膜
54c:絕緣膜
BL:位元線
CL:柱狀部
P:開口部
S:陣列區域與電路區域之貼合面
WL:字元線

Claims (19)

  1. 一種半導體裝置，其具備：第1基板；第1絕緣膜，其設置於上述第1基板上；第1插塞，其設置於上述第1絕緣膜內；第1層，其設置於上述第1絕緣膜上；第1金屬層，其在上述第1層內設置於上述第1插塞上，且電性連接於上述第1插塞；及第2金屬層，其包含設置於上述第1層內之第1部分、及設置於上述第1層上之第2部分，且電性連接於上述第1金屬層。
  2. 如請求項1之半導體裝置，其中上述第1層包含第2基板。
  3. 如請求項2之半導體裝置，其中上述第1層進而包含設置於上述第2基板之上表面及側面之第2絕緣膜。
  4. 如請求項1至3中任一項之半導體裝置，其中上述第1插塞包含第1金屬元素，上述第1金屬層包含與上述第1金屬元素不同之第2金屬元素。
  5. 如請求項4之半導體裝置，其中上述第1金屬元素為鎢(W)元素，上述第2金屬元素為鋁(Al)元素、鉿(Hf)元素、或鋯(Zr)元素。
  6. 如請求項1至3中任一項之半導體裝置，其具備N個(N為2以上之整數)插塞作為上述第1插塞，具備設置於上述N個插塞上之N個金屬層作為上述第1金屬層。
  7. 如請求項1至3中任一項之半導體裝置，其具備N個(N為2以上之整數)插塞作為上述第1插塞，具備設置於上述N個插塞上之1個金屬層作為上述第1金屬層。
  8. 如請求項1至3中任一項之半導體裝置，其中上述第2金屬層之上述第2部分包含接合墊。
  9. 一種半導體裝置，其具備：第1絕緣膜；第1插塞，其設置於上述第1絕緣膜內；基板，其設置於上述第1絕緣膜上；第1金屬層，其在上述基板內設置於上述第1插塞上，且電性連接於上述第1插塞；及第2金屬層，其包含設置於上述基板內之第1部分、及設置於上述基板上之第2部分，且電性連接於上述第1金屬層。
  10. 如請求項9之半導體裝置，其進而具備設置於上述基板之上表面及側面之第2絕緣膜，且上述第1部分設置於上述基板及上述第2絕緣膜內，上述第2部分設置於上述基板及上述第2絕緣膜上。
  11. 一種半導體裝置之製造方法，其包括：準備第1基板及第2基板，於上述第2基板內形成第1金屬層，於上述第1金屬層上形成第1插塞，使上述第1基板與上述第2基板介隔上述第1插塞及上述第1金屬層而貼合，於上述第1基板之上方配置上述第2基板，於上述第2基板內形成第1開口部，於上述第1開口部內露出上述第1金屬層，於上述第1開口部內形成第2金屬層，使上述第2金屬層電性連接於上述第1插塞。
  12. 如請求項11之半導體裝置之製造方法，其中上述第1開口部係使用包含氟(F)元素之氣體而形成。
  13. 如請求項11或12之半導體裝置之製造方法，其中上述第1插塞包含第1金屬元素，上述第1金屬層包含與上述第1金屬元素不同之第2金屬元素。
  14. 如請求項13之半導體裝置之製造方法，其中上述第1金屬元素為鎢(W)元素，上述第2金屬元素為鋁(Al)元素、鉿(Hf)元素、或鋯(Zr)元素。
  15. 如請求項11或12之半導體裝置之製造方法，其中上述第1金屬層係藉由將金屬原子注入至上述第1基板內而形成於上述第1基板內。
  16. 如請求項11或12之半導體裝置之製造方法，其中上述第1金屬層係藉由在上述第1基板內形成凹部，並將上述第1金屬層嵌埋至上述凹部內而形成於上述第1基板內。
  17. 如請求項11或12之半導體裝置之製造方法，其中上述第1金屬層及上述第1插塞係藉由如下方式形成：於上述第2基板上形成第1絕緣膜，於上述第1絕緣膜內形成第2開口部而於上述第2開口部內露出上述第2基板，在露出於上述第2開口部內之上述第2基板內形成上述第1金屬層，於上述第2開口部內形成上述第1插塞。
  18. 如請求項11或12之半導體裝置之製造方法，其中上述第1金屬層及上述第1插塞係藉由如下方式形成：於上述第2基板內形成上述第1金屬層，於上述第2基板及上述第1金屬層上形成第1絕緣膜，於上述第1絕緣膜內形成第2開口部而於上述第2開口部內露出上述第1金屬層，在露出於上述第2開口部內之上述第1金屬層上形成上述第1插塞。
  19. 如請求項11或12之半導體裝置之製造方法，其中上述第2金屬層直接電性連接於上述第1插塞，或經由上述第1金屬層電性連接於上述第1插塞。
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