CN114078878A - 半导体器件和包括其的数据存储系统 - Google Patents

半导体器件和包括其的数据存储系统 Download PDF

Info

Publication number
CN114078878A
CN114078878A CN202110846247.5A CN202110846247A CN114078878A CN 114078878 A CN114078878 A CN 114078878A CN 202110846247 A CN202110846247 A CN 202110846247A CN 114078878 A CN114078878 A CN 114078878A
Authority
CN
China
Prior art keywords
region
substrate
semiconductor device
layer
gate electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202110846247.5A
Other languages
English (en)
Chinese (zh)
Inventor
千相勋
金智焕
姜信焕
韩智勋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of CN114078878A publication Critical patent/CN114078878A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/121—Arrangements for protection of devices protecting against mechanical damage
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/50—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/0698—Local interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/083—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts the openings being via holes penetrating underlying conductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/482—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes for individual devices provided for in groups H10D8/00 - H10D48/00, e.g. for power transistors
    • H10W20/484—Interconnections having extended contours, e.g. pads having mesh shape or interconnections comprising connected parallel stripes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices

Landscapes

  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
CN202110846247.5A 2020-08-10 2021-07-26 半导体器件和包括其的数据存储系统 Pending CN114078878A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020200100043A KR102898248B1 (ko) 2020-08-10 2020-08-10 반도체 장치 및 이를 포함하는 데이터 저장 시스템
KR10-2020-0100043 2020-08-10

Publications (1)

Publication Number Publication Date
CN114078878A true CN114078878A (zh) 2022-02-22

Family

ID=79686168

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110846247.5A Pending CN114078878A (zh) 2020-08-10 2021-07-26 半导体器件和包括其的数据存储系统

Country Status (5)

Country Link
US (1) US12302580B2 (https=)
JP (1) JP7723506B2 (https=)
KR (1) KR102898248B1 (https=)
CN (1) CN114078878A (https=)
DE (1) DE102021113524A1 (https=)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102885508B1 (ko) 2020-09-15 2025-11-13 삼성전자주식회사 반도체 장치 및 이를 포함하는 데이터 저장 시스템
KR102932178B1 (ko) * 2021-06-11 2026-03-04 삼성전자주식회사 반도체 장치 및 데이터 저장 시스템
KR20250000778A (ko) * 2023-06-27 2025-01-03 삼성전자주식회사 반도체 장치 및 이를 포함하는 전자 시스템

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160013756A (ko) 2014-07-28 2016-02-05 에스케이하이닉스 주식회사 연결구조물, 반도체 장치 및 그 제조 방법
KR102282138B1 (ko) * 2014-12-09 2021-07-27 삼성전자주식회사 반도체 소자
US20170104000A1 (en) 2015-10-13 2017-04-13 Joo-Hee PARK Vertical memory devices
US9818759B2 (en) * 2015-12-22 2017-11-14 Sandisk Technologies Llc Through-memory-level via structures for a three-dimensional memory device
US9985040B2 (en) 2016-01-14 2018-05-29 Micron Technology, Inc. Integrated circuitry and 3D memory
US9917093B2 (en) 2016-06-28 2018-03-13 Sandisk Technologies Llc Inter-plane offset in backside contact via structures for a three-dimensional memory device
US9905307B1 (en) * 2016-08-24 2018-02-27 Sandisk Technologies Llc Leakage current detection in 3D memory
CN106910746B (zh) 2017-03-08 2018-06-19 长江存储科技有限责任公司 一种3d nand存储器件及其制造方法、封装方法
US10685914B2 (en) 2017-08-31 2020-06-16 SK Hynix Inc. Semiconductor device and manufacturing method thereof
KR102587973B1 (ko) 2017-11-07 2023-10-12 삼성전자주식회사 3차원 반도체 메모리 장치
JP2019160922A (ja) 2018-03-09 2019-09-19 東芝メモリ株式会社 半導体装置
KR102614849B1 (ko) 2018-05-21 2023-12-18 삼성전자주식회사 지지대를 갖는 3d 반도체 소자 및 그 형성 방법
JP2019220534A (ja) 2018-06-18 2019-12-26 キオクシア株式会社 半導体記憶装置およびその製造方法
US10971432B2 (en) 2018-08-06 2021-04-06 Samsung Electronics Co., Ltd. Semiconductor device including a through wiring area
JP2020035921A (ja) 2018-08-30 2020-03-05 キオクシア株式会社 半導体記憶装置
JP2020047810A (ja) 2018-09-20 2020-03-26 キオクシア株式会社 半導体記憶装置及びその製造方法
US11282783B2 (en) * 2020-01-07 2022-03-22 Sandisk Technologies Llc Three-dimensional memory device with via structures surrounded by perforated dielectric moat structure and methods of making the same

Also Published As

Publication number Publication date
KR20220019522A (ko) 2022-02-17
US12302580B2 (en) 2025-05-13
KR102898248B1 (ko) 2025-12-10
JP7723506B2 (ja) 2025-08-14
US20220045084A1 (en) 2022-02-10
JP2022032028A (ja) 2022-02-24
DE102021113524A1 (de) 2022-02-10

Similar Documents

Publication Publication Date Title
CN114582883A (zh) 半导体器件以及包括该半导体器件的数据存储系统
CN114078878A (zh) 半导体器件和包括其的数据存储系统
JP7723505B2 (ja) 半導体装置及びこれを含むデータ格納システム
US12268006B2 (en) Semiconductor device and data storage system including the same
CN116234318A (zh) 用于制造半导体器件的方法
CN114388522A (zh) 半导体芯片和包括半导体芯片的半导体装置
EP4387409A1 (en) Semiconductor device and data storage systems including a semiconductor device
US11800712B2 (en) Semiconductor device and electronic system including the same
US11985820B2 (en) Semiconductor devices and data storage systems including the same
CN117156851A (zh) 半导体器件以及包括该半导体器件的电子系统
CN117116904A (zh) 半导体器件及包括其的数据存储系统
CN116896887A (zh) 半导体器件及包括该半导体器件的数据存储系统
CN114188350A (zh) 半导体器件和包括半导体器件的电子系统
EP4626165A1 (en) Semiconductor devices and data storage systems including the same
US20250107086A1 (en) Semiconductor devices and data storage systems including the same
EP4426082A1 (en) Semiconductor devices and data storage systems including the same
KR20250060654A (ko) 반도체 장치 및 이를 포함하는 데이터 저장 시스템
CN115206914A (zh) 半导体器件和包括半导体器件的数据存储系统
CN118870816A (zh) 半导体装置和包括半导体装置的数据存储系统
CN117082872A (zh) 半导体器件和包括其的数据存储系统
CN119677108A (zh) 半导体器件以及包括其的数据存储系统
KR20220159313A (ko) 반도체 장치 및 이를 포함하는 데이터 저장 시스템
CN117500275A (zh) 半导体器件以及包括该半导体器件的电子系统
CN118159032A (zh) 半导体器件和包括该半导体器件的数据存储系统
CN119451122A (zh) 半导体器件和包括该半导体器件的数据存储系统

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination