CN114072901A - 晶片载置台及其制法 - Google Patents

晶片载置台及其制法 Download PDF

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CN114072901A
CN114072901A CN202080047761.6A CN202080047761A CN114072901A CN 114072901 A CN114072901 A CN 114072901A CN 202080047761 A CN202080047761 A CN 202080047761A CN 114072901 A CN114072901 A CN 114072901A
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ceramic sintered
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竹林央史
相川贤一郎
久野达也
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Abstract

一种晶片载置台，其在陶瓷烧结体的表面具备支撑晶片的多个凸部。陶瓷烧结体的表面中没有凸部的部分是表面粗糙度Ra为0.1μm以下的镜面。凸部是与陶瓷烧结体相同材质的气溶胶沉积膜或喷镀膜。

Description

晶片载置台及其制法
技术领域
本发明涉及晶片载置台及其制法。
背景技术
以往，在半导体晶片的传送、曝光、CVD等成膜工艺、清洗、蚀刻、切割等微细加工中，使用载置晶片的晶片载置台。在专利文献1中，作为这样晶片载置台，公开了如下的载置台，其具备通过腐蚀加工(喷砂加工)在上表面部形成了凹凸的陶瓷烧结体、埋设于该陶瓷烧结体的静电电极、以及将该静电电极与外部电源连接的端子。
现有技术文献
专利文献
专利文献1：日本特开2006-147724号公报
发明内容
发明所要解决的课题
在对陶瓷烧结体的上表面部实施腐蚀加工的情况下，一般对陶瓷烧结体的上表面部进行镜面精加工，用掩模覆盖想要形成凸部的部位，利用腐蚀加工对未被掩模覆盖的部位进行粉碎(参照图2)。
但是，若微观地观察陶瓷烧结体的上表面部中的腐蚀加工面，则有时会看到快要脱落微粒的部位、腐蚀加工的介质的残渣等残留的部位。如果存在这样的部位，则有可能成为在半导体工艺中不理想的微粒产生的原因。为了改善这一点，例如可考虑使用柔软的材料对腐蚀加工面进行表面处理(例如研磨)等，但由于磨后的面与镜面相比较粗，因此依然有可能成为微粒产生的原因。
本发明是为了解决这样的课题而完成的，其主要目的在于防止在半导体工艺中产生微粒。
用于解决课题的方案
本发明的晶片载置台是在陶瓷烧结体的表面具备支撑晶片的多个凸部的晶片载置台，
所述陶瓷烧结体的所述表面中没有所述凸部的部分是表面粗糙度Ra为0.1μm以下的镜面，
所述凸部是与所述陶瓷烧结体相同材质的气溶胶沉积(AD)膜或喷镀膜。
该晶片载置台例如可通过在对陶瓷烧结体的表面进行镜面精加工后，在想要形成凸部的部位形成AD膜或喷镀膜而得到。由于该晶片载置台的陶瓷烧结体的表面中没有凸部的部分是镜面，因此不会成为微粒产生的原因。因此，根据该晶片载置台，能够防止在半导体工艺中产生微粒。
在本发明的晶片载置台中，所述凸部的角(顶面与侧面的边界)可以带有圆度。这样一来，凸部的角不易成为对于机械性外力的应力集中部位。
在本发明的晶片载置台中，所述凸部可以与所述陶瓷烧结体相比致密性低。陶瓷烧结体通过采用热压烧成等而能够制成致密的烧结体。另一方面，由于凸部是AD膜或喷镀膜，因此与陶瓷烧结体相比致密性低。
本发明的晶片载置台的制法包括：
(a)对陶瓷烧结体的表面进行镜面精加工的工序；以及
(b)通过AD法或喷镀法在所述表面中想要形成凸部的部分形成凸部的工序。
根据该晶片载置台的制法，能够比较容易地制作上述的本发明的晶片载置台。
附图说明
图1是本实施方式的晶片载置台的制造工序图。
图2是以往的晶片载置台的制造工序图。
具体实施方式
以下，参照附图说明本发明的优选的实施方式。图1是本实施方式的晶片载置台的制造工序图(纵剖视图)。
晶片载置台在圆板状的陶瓷烧结体的表面具备支撑晶片的多个凸部。陶瓷烧结体的表面中没有凸部的部分是表面粗糙度Ra为0.1μm以下的镜面。凸部是与陶瓷烧结体相同材质的AD膜或喷镀膜。在剖面观察时，凸部的角(顶面与侧面的边界)带有圆度。在观察晶片载置台的截面时，凸部与陶瓷烧结体相比致密性降低。陶瓷烧结体通过采用热压烧成而成为致密质。另一方面，由于凸部是AD膜或喷镀膜，因此与陶瓷烧结体相比致密性降低(例如气孔率变高)。陶瓷烧结体也可以内置静电电极、RF电极以及加热器电极(电阻发热体)中的至少一者。凸部的顶面也可以经过研磨。
晶片载置台的制法包括：(a)对陶瓷烧结体的表面进行镜面精加工的工序；以及(b)通过AD法(包括等离子体AD法)或喷镀法在陶瓷烧结体表面中的想要形成凸部的部分形成凸部的工序。在工序(b)中，也可以以仅使表面中的想要形成凸部的部分露出的方式用掩模覆盖表面，通过AD法或喷镀法在露出的部位形成凸部。AD法由于能够通过冲击固化现象使陶瓷粒子成膜，因此不需要在高温下对陶瓷粒子进行烧结。若考虑到在将晶片载置于多个凸部的顶面时凸部与晶片摩擦、或在进行半导体工艺时由于暴露于等离子体而有可能从凸部脱落微粒，则与由喷镀膜形成凸部的情况相比，更优选利用AD膜来形成凸部。这是因为，AD膜相对致密且与表面的密合性高。在利用喷镀法形成凸部的情况下，为了提高密合性，优选预先使想要形成凸部的部分粗糙。
根据以上说明的本实施方式的晶片载置台，由于陶瓷烧结体的表面中没有凸部的部分是镜面，因此不会成为微粒产生的原因。因此，根据该晶片载置台，能够防止在半导体工艺中产生微粒。
另外，由于凸部的角带有圆度，因此难以成为对于机械性外力的应力集中部位。
本申请将2019年6月28日申请的日本专利申请第2019-121487号作为优先权主张的基础，通过引用将其全部内容包含在本说明书中。
产业上的利用可能性
本发明能够用于例如半导体晶片的传送、曝光、CVD等成膜工艺、清洗、蚀刻、切割等微细加工。

Claims (4)

1.一种晶片载置台，其在陶瓷烧结体的表面具备支撑晶片的多个凸部，
所述陶瓷烧结体的所述表面中没有所述凸部的部分是表面粗糙度Ra为0.1μm以下的镜面，
所述凸部是与所述陶瓷烧结体相同材质的气溶胶沉积膜或喷镀膜。
2.根据权利要求1所述的晶片载置台，其中，所述凸部的角带有圆度。
3.根据权利要求1或2所述晶片载置台，其中，所述凸部与所述陶瓷烧结体相比致密性低。
4.一种晶片载置台的制法，包括：
(a)对陶瓷烧结体的表面进行镜面精加工的工序；以及
(b)通过气溶胶沉积法或喷镀法在所述表面中想要形成凸部的部分形成凸部的工序。
CN202080047761.6A 2019-06-28 2020-06-10 晶片载置台及其制法 Pending CN114072901A (zh)

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