CN113948482A - 其中嵌入有电子组件的基板 - Google Patents

其中嵌入有电子组件的基板 Download PDF

Info

Publication number
CN113948482A
CN113948482A CN202110609136.2A CN202110609136A CN113948482A CN 113948482 A CN113948482 A CN 113948482A CN 202110609136 A CN202110609136 A CN 202110609136A CN 113948482 A CN113948482 A CN 113948482A
Authority
CN
China
Prior art keywords
layer
disposed
core
substrate
electronic component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202110609136.2A
Other languages
English (en)
Inventor
朴昌华
金致成
李恩惠
宋尧汉
邢建辉
李栽欣
姜德万
朴眞吾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electro Mechanics Co Ltd
Original Assignee
Samsung Electro Mechanics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electro Mechanics Co Ltd filed Critical Samsung Electro Mechanics Co Ltd
Publication of CN113948482A publication Critical patent/CN113948482A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/182Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H05K1/188Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or attaching to a structure having a conductive layer, e.g. a metal foil, such that the terminals of the component are connected to or adjacent to the conductive layer before embedding, and by using the conductive layer, which is patterned after embedding, at least partially for connecting the component
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/182Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0201Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H05K1/0203Cooling of mounted components
    • H05K1/0204Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate
    • H05K1/0206Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate by printed thermal vias
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19Manufacturing methods of high density interconnect preforms
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20Structure, shape, material or disposition of high density interconnect preforms
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/25Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92Specific sequence of method steps
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • H05K1/111Pads for surface mounting, e.g. lay-out
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • H05K1/115Via connections; Lands around holes or via connections
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/182Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H05K1/186Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4602Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4697Manufacturing multilayer circuits having cavities, e.g. for mounting components
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568Temporary substrate used as encapsulation process aid
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0233Structure of the redistribution layers
    • H01L2224/02331Multilayer structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0233Structure of the redistribution layers
    • H01L2224/02333Structure of the redistribution layers being a bump
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0237Disposition of the redistribution layers
    • H01L2224/02373Layout of the redistribution layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0237Disposition of the redistribution layers
    • H01L2224/02381Side view
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061Disposition
    • H01L2224/0618Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181On opposite sides of the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13005Structure
    • H01L2224/13008Bump connector integrally formed with a redistribution layer on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111Tin [Sn] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/25Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H01L2224/251Disposition
    • H01L2224/2518Disposition being disposed on at least two different sides of the body, e.g. dual array
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29111Tin [Sn] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29116Lead [Pb] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/29124Aluminium [Al] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29139Silver [Ag] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29144Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29155Nickel [Ni] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/29166Titanium [Ti] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/2919Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73267Layer and HDI connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8038Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/80399Material
    • H01L2224/804Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/80401Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/80411Tin [Sn] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8038Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/80399Material
    • H01L2224/804Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/80401Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/80416Lead [Pb] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8038Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/80399Material
    • H01L2224/804Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/80417Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/80424Aluminium [Al] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8038Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/80399Material
    • H01L2224/804Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/80438Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/80439Silver [Ag] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8038Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/80399Material
    • H01L2224/804Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/80438Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/80444Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8038Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/80399Material
    • H01L2224/804Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/80438Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/80447Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8038Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/80399Material
    • H01L2224/804Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/80438Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/80455Nickel [Ni] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8038Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/80399Material
    • H01L2224/804Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/80463Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/80466Titanium [Ti] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399Material
    • H01L2224/814Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81401Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/81411Tin [Sn] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399Material
    • H01L2224/814Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81401Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/81416Lead [Pb] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399Material
    • H01L2224/814Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81417Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/81424Aluminium [Al] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399Material
    • H01L2224/814Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81439Silver [Ag] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399Material
    • H01L2224/814Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81444Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399Material
    • H01L2224/814Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81447Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399Material
    • H01L2224/814Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81455Nickel [Ni] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399Material
    • H01L2224/814Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81463Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/81466Titanium [Ti] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399Material
    • H01L2224/834Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83401Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/83411Tin [Sn] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399Material
    • H01L2224/834Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83401Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/83416Lead [Pb] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399Material
    • H01L2224/834Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83417Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/83424Aluminium [Al] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399Material
    • H01L2224/834Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83438Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/83439Silver [Ag] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399Material
    • H01L2224/834Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83438Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/83444Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399Material
    • H01L2224/834Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83438Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/83447Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399Material
    • H01L2224/834Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83438Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/83455Nickel [Ni] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399Material
    • H01L2224/834Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83463Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/83466Titanium [Ti] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92242Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838Geometry or layout
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device
    • H01L2924/15155Shape the die mounting substrate comprising a recess for hosting the device the shape of the recess being other than a cuboid
    • H01L2924/15156Side view
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/02Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
    • H05K2203/025Abrading, e.g. grinding or sand blasting
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14Related to the order of processing steps
    • H05K2203/1461Applying or finishing the circuit pattern after another process, e.g. after filling of vias with conductive paste, after making printed resistors
    • H05K2203/1469Circuit made after mounting or encapsulation of the components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0011Working of insulating substrates or insulating layers
    • H05K3/0044Mechanical working of the substrate, e.g. drilling or punching
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/007Manufacture or processing of a substrate for a printed circuit board supported by a temporary or sacrificial carrier
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0097Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • H05K3/305Affixing by adhesive

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

本公开提供一种其中嵌入有电子组件的基板,所述其中嵌入有电子组件的基板包括:芯结构,具有腔;金属层,设置在所述芯结构的所述腔的底表面上;以及电子组件,设置在所述芯结构的所述腔中的所述金属层上。所述其中嵌入有电子组件的基板具有优异的散热效果。

Description

其中嵌入有电子组件的基板
本申请要求于2020年7月17日在韩国知识产权局提交的第10-2020-0088970号韩国专利申请的优先权的权益,该韩国专利申请的公开内容通过引用被全部包括于此。
技术领域
本公开涉及一种其中嵌入有电子组件的基板。
背景技术
随着在信息技术(IT)领域中的电子装置(包括移动电话)已经变轻薄,响应于对此的技术需求,需要将诸如集成电路(IC)的电子组件插入印刷电路板中的技术,并且近年来已经使用各种方法开发了将电子组件嵌入印刷电路板中的技术。
此外,随着电子组件的性能的提高以及组件之间的信号传输量的增加,电子组件中的发热量增加。因此,已经对其中嵌入有这种电子组件的印刷电路板的散热设计进行了许多研究和开发。
发明内容
本公开的一方面在于提供一种具有优异的散热效果的其中嵌入有电子组件的基板。
本公开的另一方面在于提供一种具有优异的布线设计效率的其中嵌入有电子组件的基板。
根据本公开所提出的各种方案中的一种方案,第一金属层设置在其中设置有电子组件的腔的底表面上,并且第二金属层设置在所述电子组件的侧表面上,以使散热路径多样化,同时增加散热面积。
根据本公开的一方面,一种其中嵌入有电子组件的基板可包括:芯结构,包括第一绝缘主体、多个第一布线层以及一个或更多个第一过孔层,所述多个第一布线层设置在所述第一绝缘主体上和/或所述第一绝缘主体中,所述一个或更多个第一过孔层设置在所述第一绝缘主体中,所述芯结构具有穿透所述第一绝缘主体的至少一部分的腔;第一金属层,设置在所述腔的底表面上;电子组件,设置在所述腔中的所述第一金属层上;以及第二金属层,设置在所述电子组件的侧表面上。
根据本公开所提出的各种方案中的另一种方案,金属层设置在其中设置有电子组件的腔的底表面上,并且图案孔形成在所述金属层中,以使用所述金属层的一部分作为用于形成所述腔的阻挡金属,并且可作为散热路径,而所述金属层的剩余部分用作信号路径。
根据本公开的一方面,一种其中嵌入有电子组件的基板可包括:芯结构,包括绝缘主体、多个布线层以及一个或更多个过孔层,所述多个布线层设置在所述绝缘主体上和/或所述绝缘主体中,所述一个或更多个过孔层设置在所述绝缘主体中,所述芯结构具有穿透所述绝缘主体的至少一部分的腔;金属层,设置在所述腔的底表面上,并且具有图案孔;以及电子组件,设置在所述腔中的所述金属层上。
根据本公开的一方面,一种基板可包括:芯结构,具有腔,并且包括绝缘主体、一个或更多个第一布线层以及一个或更多个过孔层,所述一个或更多个第一布线层设置在所述绝缘主体上和/或所述绝缘主体中,所述一个或更多个过孔层设置在所述绝缘主体中并且连接到所述一个或更多个第一布线层;第一金属层,设置在所述绝缘主体上或所述绝缘主体中;电子组件,设置在所述腔中的所述第一金属层上;以及第二金属层,从所述第一金属层延伸以与所述电子组件的侧表面接触。
附图说明
通过结合附图以及以下具体实施方式,本公开的以上和其他方面、特征及优点将被更清楚地理解,在附图中:
图1是示出电子装置系统的示例的框图;
图2是示出电子装置的示例的立体图;
图3是示出其中嵌入有电子组件的基板的示例的截面图;
图4是示出沿图3中的线I-I'截取的图3中所示的其中嵌入有电子组件的基板的示意性截面图;
图5是示出沿图3中的线II-II'截取的图3中所示的其中嵌入有电子组件的基板的示意性截面图;
图6至图17是示意性示出制造图3的其中嵌入有电子组件的基板的示例的截面图;
图18是示意性示出其中嵌入有电子组件的基板的另一示例的截面图;
图19是示意性示出其中嵌入有电子组件的基板的另一示例的截面图;以及
图20是示意性示出其中嵌入有电子组件的基板的另一示例的截面图。
具体实施方式
在下文中,将参照附图描述本公开的示例性实施例。在附图中,为了描述的清楚性,可夸大或简要示出元件的形状、尺寸等。
图1是示出电子装置系统的示例的框图。
参照图1,电子装置1000可将主板1010容纳在其中。芯片相关组件1020、网络相关组件1030、其他组件1040等可与主板1010物理连接和/或电连接。这些组件可通过各种信号线1090连接到其他组件(下面将描述)。
芯片相关组件1020可包括:存储器芯片,诸如易失性存储器(例如,动态随机存取存储器(DRAM))、非易失性存储器(例如,只读存储器(ROM))、闪存等;应用处理器芯片,诸如中央处理器(例如,中央处理单元(CPU))、图形处理器(例如,图形处理单元(GPU))、数字信号处理器、密码处理器、微处理器、微控制器等;以及逻辑芯片,诸如模数转换器(ADC)、专用集成电路(ASIC)等。然而,芯片相关组件1020不限于此,并且还可包括其他类型的芯片相关组件。另外,芯片相关组件1020可彼此组合。
网络相关组件1030可包括与诸如以下协议兼容或者使用诸如以下协议进行操作的组件:无线保真(Wi-Fi)(电气和电子工程师协会(IEEE)802.11族等)、全球微波接入互操作性(WiMAX)(IEEE 802.16族等)、IEEE 802.20、长期演进(LTE)、演进仅数据(Ev-DO)、高速分组接入+(HSPA+)、高速下行链路分组接入+(HSDPA+)、高速上行链路分组接入+(HSUPA+)、增强数据GSM环境(EDGE)、全球移动通信系统(GSM)、全球定位系统(GPS)、通用分组无线业务(GPRS)、码分多址(CDMA)、时分多址(TDMA)、数字增强型无绳电信(DECT)、蓝牙、3G协议、4G协议和5G协议以及在上述协议之后指定的任何其他无线协议和有线协议。然而,网络相关组件1030不限于此,并且还可包括与各种其他无线标准或协议或者有线标准或协议兼容或者使用各种其他无线标准或协议或者有线标准或协议进行操作的组件。另外,网络相关组件1030可与上述芯片相关组件1020彼此组合。
其他组件1040可包括高频率电感器、铁氧体电感器、功率电感器、铁氧体磁珠、低温共烧陶瓷(LTCC)组件、电磁干扰(EMI)滤波器、多层陶瓷电容器(MLCC)等。然而,其他组件1040不限于此,并且还可包括用于各种其他目的的无源组件等。另外,其他组件1040可与上述芯片相关组件1020和/或上述网络相关组件1030彼此组合。
根据电子装置1000的类型,电子装置1000可包括可物理连接和/或电连接到主板1010或者可不物理连接和/或不电连接到主板1010的其他组件。这些其他组件可包括例如相机1050、天线1060、显示器1070、电池1080、音频编解码器(未示出)、视频编解码器(未示出)、功率放大器(未示出)、指南针(未示出)、加速度计(未示出)、陀螺仪(未示出)、扬声器(未示出)、大容量存储装置(例如,硬盘驱动器)(未示出)、光盘(CD)驱动器(未示出)、数字通用盘(DVD)驱动器(未示出)等。然而,这些其他组件不限于此,并且根据电子装置1000的类型等,还可包括用于各种目的的其他组件。
电子装置1000可以是智能电话、个人数字助理(PDA)、数字摄像机、数码相机、网络系统、计算机、监视器、平板PC、膝上型PC、上网本PC、电视、视频游戏机、智能手表、汽车组件等。然而,电子装置1000不限于此,并且可以是能够处理数据的任何其他电子装置。
图2是示出电子装置的示例的立体图。
参照图2,在如上所述的各种电子装置1000中,半导体封装件可用于各种目的。例如,主板1110可容纳在智能电话1100的主体中,并且各种电子组件1120可物理连接和/或电连接到主板1110。另外,可物理连接和/或电连接到主板1110或者可不物理和/或不电连接到主板1110的其他组件(诸如相机模块1130)可容纳在主体中。电子组件1120中的一些可以是芯片相关组件(例如,半导体封装件1121),但不限于此。电子装置不必限于智能电话1100,而可以是如上所述的其他电子装置。
图3是示出其中嵌入有电子组件的基板的截面图。
图4是示出沿图3中的线I-I'截取的图3中所示的其中嵌入有电子组件的基板的截面图。
图5是示出沿图3中的线II-II'截取的图3中所示的其中嵌入有电子组件的基板的截面图。
参照附图,其中嵌入有电子组件的基板100A可包括芯结构110,芯结构110包括第一绝缘层111、多个第一布线层112a和112b以及一个或更多个第一过孔层113,芯结构110具有穿透第一绝缘层111的腔110H、设置在腔110H的底表面上的第一金属层M、设置在腔110H中的第一金属层M上的电子组件120以及设置在电子组件120的侧表面上的第二金属层N。
如上所述,在根据示例的其中嵌入有电子组件的基板100A中,第一金属层M设置在其中设置有电子组件120的腔110H的底表面上,并且第二金属层N设置在电子组件120的侧表面上。因此,可多方面地提供用于将从电子组件120产生的热消散的散热路径,并且可增加散热面积。因此,其中嵌入有电子组件的基板100A可具有优异的散热效果。
此外,第二金属层N可物理接触电子组件120的侧表面。在这种情况下,可更有效地释放从电子组件120产生的热。第二金属层N可围绕电子组件120的侧表面。例如,在电子组件120大致呈长方体的情况下,第二金属层N可围绕电子组件120的四个侧表面。例如,第二金属层N可连续地围绕电子组件120的四个侧表面,但是本公开不限于此,并且在特定区域中可存在局部不连续点h3。
此外,第二金属层N可与第一金属层M物理接触。在这种情况下,可将热有效地传递到第一金属层M,结果,可将从电子组件120产生的热有效地释放。第一金属层M可具有槽部h1,并且第二金属层N可填充槽部h1。例如,第二金属层N的一部分可设置在槽部h1中。在这种情况下,例如,在如图4或5所示的平面上,槽部h1可沿着电子组件120的四个侧表面形成。例如,槽部h1可沿着电子组件120的四个侧表面连续地形成,但不限于此,并且在特定区域中可存在局部不连续点h3。
另外,在根据示例的其中嵌入有电子组件的基板100A中,第一金属层M具有图案孔h2。结果,第一金属层M可包括第一金属图案M1和多个第二金属图案M2,第一金属图案M1具有槽部h1,多个第二金属图案M2彼此间隔开并且被第一金属图案M1围绕。多个第二金属图案M2中的一部分第二金属图案M2可用作直接散热路径,并且多个第二金属图案M2中的剩余的第二金属图案M2可用作信号路径。因此,从电子组件120的底表面产生的热可经由最短路径通过第一金属层M有效地释放到外部,同时,第一金属层M的一部分可用作信号路径,以提高布线设计的效率。图案孔h2可以是一个图案孔h2,或者可以是彼此区分开的多个图案孔h2,并且多个第二金属图案M2的数量和形状可根据图案孔h2的形成以各种方式变化。
此外,多个第二金属图案M2中的至少一部分的第二金属图案M2可电连接到多个第一布线层112a和112b中的至少一个接地图案,并且多个第二金属图案M2中的剩余的第二金属图案M2中的至少一者可连接(例如,电连接)到多个第一布线层112a和112b中的至少一个信号图案。第一金属图案M1还可电连接到多个第一布线层112a和112b中的至少一个接地图案,因此,多个第二金属图案M2的至少一部分可连接到第一金属图案M1,并且由此可电连接到多个第一布线层112a和112b中的至少一个接地图案。
可选地,可仅设置第二金属层N而不在第一金属层M中形成图案孔h2,或者相反,可仅在第一金属层M中形成图案孔h2而不设置第二金属层N,但是满足这两种情况(即,同时形成图案孔h2和第二金属层N)对于优异的散热效果和优异的布线设计是更优选的。
参照附图,根据示例的其中嵌入有电子组件的基板100A还可包括:包封剂130,设置在芯结构110上以填充腔110H的至少一部分并且使电子组件120的至少一部分嵌入包封剂130中;第二布线层132,设置在包封剂130上;第二过孔层133,穿透包封剂130;第一钝化层150,设置在芯结构110下方;和/或第二钝化层160,设置在包封剂130上。在这种情况下,第一钝化层150可具有多个第一开口151,多个第一开口151使设置在最下侧的第一布线层112a的至少一部分和第一金属层M的至少一部分暴露。在这种情况下,由于第一金属层M可用作直接散热路径,因此可通过使散热路径的长度最小化来增强散热效果。
参照附图,根据示例的其中嵌入有电子组件的基板100A还可包括:多个第一电连接金属155,分别设置在第一钝化层150的多个第一开口151中;多个第二电连接金属165,分别设置在第二钝化层160的多个第二开口161中;以及多个表面安装组件170,通过多个第二电连接金属165表面安装在第二钝化层160上。如上所述,根据示例的其中嵌入有电子组件的基板100A可用作封装基板,并且可通过设置表面安装组件170而具有封装模块形式。
在下文中,将参照附图更详细地描述根据示例的其中嵌入有电子组件的基板100A的组件。
芯结构110包括:绝缘主体,包括第一绝缘层(或称为第一芯绝缘层)111;多个第一布线层112a和112b,分别设置在绝缘主体上或绝缘主体中;以及一个或更多个第一过孔层(或称为第一芯过孔层)113,设置在绝缘主体中。另外,芯结构110可具有穿透第一绝缘层111的腔110H。例如,芯结构110可包括:第一绝缘层111;1-1布线层(或称为第一芯布线层)112a,嵌入第一绝缘层111的下部中;1-2布线层(或称为第二芯布线层)112b,设置在第一绝缘层111的上表面上;以及第一过孔层113,穿透第一绝缘层111并且电连接1-1布线层112a与1-2布线层112b,并且芯结构110可具有穿透第一绝缘层111的腔110H。
可使用绝缘材料作为第一绝缘层111的材料。可使用热固性树脂(诸如环氧树脂)或热塑性树脂(诸如聚酰亚胺树脂)作为绝缘材料。另外,可使用在这些树脂中包含增强材料(诸如无机填料(诸如二氧化硅)和/或芯材料(诸如玻璃纤维))的绝缘材料。例如,半固化片可用作第一绝缘层111的材料,但不限于此。
第一布线层112a和112b可包括金属材料。可使用铜(Cu)、铝(Al)、银(Ag)、锡(Sn)、金(Au)、镍(Ni)、铅(Pb)、钛(Ti)或它们的合金作为金属材料。第一布线层112a和112b可根据相应层的设计执行各种功能。例如,第一布线层112a和112b可包括接地图案、电力图案、信号图案等。图案中的每者可具有线形状、面形状和/或垫形状。第一布线层112a和112b可利用加成工艺(AP)、半AP(SAP)、改进的SAP(MSAP)、封孔(TT)等形成,结果,第一布线层112a和112b可包括种子层(无电镀层)和基于该种子层形成的电解镀层。
1-1布线层112a的下表面与第一绝缘层111的下表面之间可具有第一台阶d1。例如,可通过嵌入式迹线基板(ETS)方法形成1-1布线层112a,如稍后所描述的,可去除用作种子层的金属箔来形成第一台阶d1。1-1布线层112a可不具有种子层(单独的无电镀层),并且可仅包括单个电解镀层。
另一方面,1-2布线层112b可包括种子层(无电镀层)和基于该种子层形成的电解镀层。当涂树脂铜箔(RCC)用作第一绝缘层111时,在最下侧上还可包括金属箔(诸如铜箔)。如果需要,则还可进一步包括形成在铜箔的表面上的底漆树脂(primer resin)。
第一过孔层113可包括金属材料。可使用铜(Cu)、铝(Al)、银(Ag)、锡(Sn)、金(Au)、镍(Ni)、铅(Pb)、钛(Ti)或它们的合金作为金属材料。根据设计,第一过孔层113可包括用于信号连接的连接过孔、用于接地连接的连接过孔和用于电力连接的连接过孔等。第一过孔层113的连接过孔中的每个连接过孔可以是其中通路孔被金属材料填满的过孔,或者是其中金属材料沿着通路孔的壁表面形成的过孔。例如,参照图3所示的截面图,每个布线过孔(或称为连接过孔)可具有其中上表面的宽度大于下表面的宽度的锥形形状。第一过孔层113可通过镀覆工艺(诸如AP、SAP、MSAP、TT等)形成,结果,与1-2布线层112b类似,第一过孔层113可包括种子层(无电镀层)和基于该种子层形成的电解镀层。
第一金属层M可包括金属材料。可使用铜(Cu)、铝(Al)、银(Ag)、锡(Sn)、金(Au)、镍(Ni)、铅(Pb)、钛(Ti)或它们的合金作为金属材料。第一金属层M的中心区域可通过腔110H暴露,并且第一金属层M的边缘区域可嵌入第一绝缘层111中。在这种情况下,第一金属层M的在中心区域中的上表面和第一金属层M的在边缘区域中的上表面之间可具有第二台阶d2。例如,在使用喷砂工艺形成腔110H的工艺中,可通过精细颗粒的侵蚀去除用作阻挡件的第一金属层M的中心区域的一部分,以形成第二台阶d2。
第一金属层M的下表面与第一绝缘层111的下表面之间可具有第一台阶d1。例如,当形成1-1布线层112a时,也可通过ETS方法形成第一金属层M,从而可去除用作种子层的金属箔,以形成第一台阶d1。第一金属层M可不具有种子层(单独的无电镀层),并且可仅包括单个电解镀层。根据本发明的示例性实施例,第一金属层M可设置绝缘主体中,也可设置在绝缘主体上。
第一金属层M可具有槽部h1,并且槽部h1可填充有第二金属层N。例如,在如图4或5所示的平面上,槽部h1可沿着电子组件120的四个侧表面形成。例如,槽部h1可沿着电子组件120的四个侧表面连续地形成,但不限于此,并且在特定区域中可存在局部不连续点h3。另外,第一金属层M可具有图案孔h2,并且第一金属层M可包括第一金属图案M1和多个第二金属图案M2,第一金属图案M1通过图案孔h2沿着腔110H的边缘设置并且具有槽部h1,多个第二金属图案M2彼此间隔开并且被第一金属图案M1围绕。多个第二金属图案M2中的每者的形状没有特别限制,并且可具有线形状、面形状和/或垫形状。图案孔h2可填充有第一钝化层150。
第二金属层N可包括金属材料,并且可使用铜(Cu)、铝(Al)、银(Ag)、锡(Sn)、金(Au)、镍(Ni)、铅(Pb)、钛(Ti)或它们的合金作为金属材料。第二金属层N可与电子组件120的侧表面物理接触。例如,在如图4或5所示的平面上,第二金属层N可围绕电子组件120的四个侧表面。
例如,第二金属层N可连续地围绕电子组件120的四个侧表面,但是本公开不限于此,并且在特定区域中可存在局部不连续点h3。第二金属层N可物理接触第一金属层M。例如,第二金属层N可填充第一金属层M的槽部h1。第二金属层N可通过例如镀覆工艺形成,诸如AP、SAP、MSAP或TT的工艺。因此,第二金属层N可包括种子层(形成在稍后将描述的深过孔的底表面和壁表面上的无电镀层)以及基于该种子层形成为填充深过孔的电解镀层。
电子组件120可以是集成电路(IC),在集成电路(IC)中,数百到数百万个元件被集成在单个芯片中。例如,电子组件120可以是处理器芯片(诸如中央处理器(例如,CPU)、图形处理器(例如,GPU)、现场可编程门阵列(FPGA)、数字信号处理器、加密处理器、微处理器、微控制器等),具体地,电子组件120可以是应用处理器(AP),但不限于此,并且电子组件120可以是存储器(诸如易失性存储器(例如,DRAM)、非易失性存储器(例如,ROM)、闪存等)、模数转换器或逻辑芯片(诸如专用IC(ASIC)等)。
电子组件120可以以面朝上的形式设置,使得其上设置有连接垫120P的表面面向上部,并且该表面的相对表面通过粘合膜125(诸如裸片附着膜(DAF)等)附接到第一金属层M。可使用具有优异的散热特性的粘合剂(例如具有优异的散热特性的DAF)作为粘合膜125。电子组件120可以是片式无源组件,例如,片式电感器或片式电容器。电子组件120可以是IC和片形式的无源组件的组合,在这种情况下,可形成多个腔110H。
包封剂130可设置在芯结构110上,并且可填充腔110H的至少一部分,并且可使电子组件120的至少一部分嵌入包封剂130中。可使用绝缘材料作为包封剂130的材料。也可使用热固性树脂(诸如环氧树脂)或热塑性树脂(诸如聚酰亚胺树脂)作为绝缘材料。此外,也可使用其中无机填料(诸如二氧化硅)包含在这些树脂中的绝缘材料。例如,可使用味之素堆积膜(ABF)作为包封剂130的材料,但不限于此,并且也可使用感光包封剂(PIE)作为包封剂130的材料。可选地,也可使用半固化片作为包封剂130的材料。
第二布线层132可设置在包封剂130的上表面上。第二布线层132可包括金属材料,诸如铜(Cu)、铝(Al)、银(Ag)、锡(Sn)、金(Au)、镍(Ni)、铅(Pb)、钛(Ti)或它们的合金。第二布线层132可根据设计执行各种功能。例如,第二布线层132可包括接地(GND)图案、电力(PWR)图案、信号(S)图案等。图案中的每者可具有线形状、面形状或垫形状。
第二布线层132可通过诸如AP、SAP、MSAP、TT等的工艺形成,因此,第二布线层132可包括种子层(无电镀层)和基于该种子层形成的电解镀层。当使用RCC作为包封剂130时,在最下侧还可包括金属箔(诸如铜箔),并且还可包括形成在铜箔的表面上的底漆树脂。
第二过孔层133可穿透包封剂130,并且可将第二布线层132电连接到1-2布线层112b和连接垫120P中的每者。第二过孔层133可包括金属材料,诸如铜(Cu)、铝(Al)、银(Ag)、锡(Sn)、金(Au)、镍(Ni)、铅(Pb)、钛(Ti)或它们的合金。根据设计,第二过孔层133可包括用于信号连接的连接过孔、用于接地连接的连接过孔、用于电力连接的连接过孔等。第二过孔层133的布线过孔可以是其中通路孔被金属材料填满的过孔,或者可以是其中金属材料沿着通路孔的壁表面形成的过孔。例如,参照图3所示的截面图,每个布线过孔可具有其中上表面的宽度大于下表面的宽度的锥形形状。第二过孔层133也可通过镀覆工艺(诸如AP、SAP、MSAP、TT等)形成,因此,与第二布线层132类似,第二过孔层133可包括种子层(无电镀层)和基于该种子层形成的电解镀层。
第一钝化层150和第二钝化层160可保护内部构造免受外部的物理损坏和化学损坏等。第一钝化层150可具有多个第一开口151,第二钝化层160可具有多个第二开口161。多个第一开口151可使1-1布线层112a和第一金属层M中的每者的至少一部分暴露。多个第二开口161可使第二布线层132的至少一部分暴露。第一钝化层150和第二钝化层160的材料可包括绝缘材料。在这种情况下,可使用热固性树脂(诸如环氧树脂)、热塑性树脂(诸如聚酰亚胺树脂)、其中热固性树脂和/或热塑性树脂与无机填料混合的材料作为绝缘材料,例如,可使用ABF,但不限于此。
第一电连接金属155设置在第一钝化层150的多个第一开口151上,第二电连接金属165设置在第二钝化层160的多个第二开口161上。第一电连接金属155连接到1-1布线层112a的通过第一开口151暴露的部分和第一金属层M的通过第一开口151暴露的部分。第二电连接金属165连接到第二布线层132的通过第二开口161暴露的部分。第一电连接金属155可将其中嵌入有电子组件的基板100A物理连接和/或电连接到外部实体。例如,其中嵌入有电子组件的基板100A可通过第一电连接金属155安装在电子装置的主板、球栅阵列(BGA)基板等上。第二电连接金属165可将其中嵌入有电子组件的基板100A物理连接和/或电连接到表面安装组件170。第一电连接金属155和第二电连接金属165可利用锡(Sn)或包含锡(Sn)的合金(例如焊料)形成,但这仅仅是示例,并且材料不受此特别限制。第一电连接金属155和第二电连接金属165可分别被构造为焊盘、焊球、引脚等。
表面安装组件170中的每者可以是有源组件和/或无源组件。有源组件的示例可包括上述用于电子组件120的IC。无源组件的示例可包括片式电容器(诸如多层陶瓷电容器(MLCC))和片式电感器(诸如功率电感器(PI))。如果需要,则覆盖表面安装组件170的模塑材料还可设置在第二钝化层160上,并且模塑材料可以是已知的环氧树脂模塑料(EMC),但不限于此。当进一步设置表面安装组件170时,其中嵌入有电子组件的基板100A可用作封装模块,例如,系统级封装(SiP)。
图6至图17是示出用于制造图3所示的其中嵌入有电子组件的基板的工艺的示例的示图。
参照图6,制备载体210。金属箔(诸如铜箔)m1可设置在载体210的两个表面(例如上表面和下表面)上。
参照图7,将金属箔m1用作基础种子层,通过ETS镀覆工艺在载体210上形成1-1布线层112a和第一金属层M。
参照图8,使用RCC材料形成第一绝缘层111,其中金属箔(诸如铜箔)m2设置在半固化片的上表面上。此后,通过激光加工等在第一绝缘层111中形成通路孔113h。
参照图9,通过镀覆工艺形成1-2布线层112b和第一过孔层113。由此,形成芯结构110。此后,将图案化的干膜220堆叠在芯结构110上,用于在后续工艺中形成腔110H。
参照图10,通过喷砂等形成腔110H。在该工艺中,第一金属层M可用作阻挡件,并且可从第一金属层M的通过腔110H暴露的区域去除第一金属层M的一部分。
参照图11,去除干膜220,并且使用粘合膜125将电子组件120以面朝上(即,设置有连接垫120P的表面面向上部)的形式附接到腔110H中的第一金属层M。
参照图12,通过ABF层压在芯结构110上来形成包封剂130,并且通过激光加工等形成通路孔133h。
参照图13,通过镀覆工艺形成第二布线层132和第二过孔层133。通过一系列工艺在载体210的两侧上制造出层压件。
参照图14,将层压件与载体210分离。
参照图15,将干膜230和240分别附接到分离的层压件的两侧,并且通过激光加工等形成穿透第一金属层M和包封剂130的深过孔V,并且形成穿透第一金属层M的图案孔h2。深过孔V的穿透第一金属层M的区域成为上述槽部h1。
参照图16,通过利用镀覆工艺填充深过孔V来形成第二金属层N。此外,去除干膜230和240。
参照图17,通过ABF层压等形成第一钝化层150和第二钝化层160,并且通过激光加工等形成多个第一开口151和多个第二开口161。此后,根据需要,形成第一电连接金属155和第二电连接金属165。
可通过一系列工艺制造根据上述示例的具有嵌入其中的电子组件的基板100A,并且省略其中嵌入有电子组件的基板100A的其他重复内容的描述。
图18是示出其中嵌入有电子组件的基板的另一示例的示意性截面图。
参照附图,与在根据上述示例的其中嵌入有电子组件的基板100A中形成的芯结构110相比,在根据另一示例的其中嵌入有电子组件的基板100B中,芯结构110形成为更多层。例如,芯结构110可包括:1-1绝缘层111a;1-1布线层112a,嵌入1-1绝缘层111a的下部中;1-2布线层112b,设置在1-1绝缘层111a的上表面上;1-1过孔层113a,穿透1-1绝缘层111a并将1-1布线层112a与1-2布线层112b电连接;1-2绝缘层(或称为第二芯绝缘层)111b,设置在1-1绝缘层111a的上表面上并覆盖1-2布线层112b;1-3布线层(或称为第三芯布线层)112c,设置在1-2绝缘层111b的上表面上;以及1-2过孔层(或称为第二芯过孔层)113b,穿透1-2绝缘层111b并将1-2布线层112b和1-3布线层112c电连接。并且,腔110H可穿透1-1绝缘层111a和1-2绝缘层111b。
因此,芯结构110的层数不受特别限制,并且可根据设计形成为更多层。如果需要,则芯结构110可形成为比附图中所示的层更多的层。将省略对根据另一示例的其中嵌入有电子组件的基板100B的其他重复内容的描述。
图19是示出其中嵌入有电子组件的基板的另一示例的示意性截面图。
参照附图,与根据上述示例的其中嵌入有电子组件的基板100A相比,在根据另一示例的其中嵌入有电子组件的基板100C中,在包封剂130上进一步设置堆积结构140。堆积结构140包括:第二绝缘主体,包括第二绝缘层141;一个或更多个第三布线层142,设置在第二绝缘主体上或第二绝缘主体中;以及一个或更多个第三过孔层143,设置在第二绝缘主体中。第二钝化层160可设置在堆积结构140上。第二钝化层160可具有使第三布线层142的至少一部分暴露的多个第二开口161。
可使用绝缘材料作为第二绝缘层141的材料。可使用热固性树脂(诸如环氧树脂)或热塑性树脂(诸如聚酰亚胺树脂)作为绝缘材料。另外,可使用在这些树脂中包含增强材料(诸如无机填料(诸如二氧化硅)和/或芯材料(诸如玻璃纤维))的绝缘材料。例如,半固化片可用作第二绝缘层141的材料,但不限于此,并且可使用不包含增强材料(诸如玻璃纤维)的材料,例如ABF等。可选地,可使用感光绝缘材料(诸如感光电介质(PID))。
第三布线层142可设置在第二绝缘层141的上表面上。第三布线层142可包括金属材料,诸如铜(Cu)、铝(Al)、银(Ag)、锡(Sn)、金(Au)、镍(Ni)、铅(Pb)、钛(Ti)或它们的合金。在示例性实施例中,第三布线层142可执行各种功能。例如,第三布线层142可包括接地(GND)图案、电力(PWR)图案、信号(S)图案等。每个图案可具有线形状、面形状或垫形状。第三布线层142可通过诸如加成工艺(AP)、半AP(SAP)、改进的SAP(MSAP)、封孔(TT)等工艺形成,因此,第三布线层142可包括种子层(无电镀层)和基于该种子层形成的电解镀层。当RCC用作第二绝缘层141的材料时,在最下侧还可包括金属箔(诸如铜箔),并且还可包括形成在铜箔的表面上的底漆树脂。
第三过孔层143可穿透第二绝缘层141,并且可将第三布线层142电连接到第二布线层132。第三过孔层143可包括金属材料,诸如铜(Cu)、铝(Al)、银(Ag)、锡(Sn)、金(Au)、镍(Ni)、铅(Pb)、钛(Ti)或它们的合金。根据设计,第三过孔层143可包括用于信号连接的连接过孔、用于接地连接的连接过孔、用于电力连接的连接过孔等。第三过孔层143的每个布线过孔可以是其中通路孔被金属材料填满的过孔,或者是其中金属材料沿着通路孔的壁表面形成的过孔。例如,参照图19所示的截面图,每个布线过孔可具有其中上表面的宽度大于下表面的宽度的锥形形状。第三过孔层143也可通过镀覆工艺(诸如AP、SAP、MSAP、TT等)形成,因此,第三过孔层143可包括种子层(无电镀层)和基于该种子层形成的电解镀层。
因此,堆积结构140可进一步设置在包封剂130上,并且堆积结构140的层数不受特别限制,且可根据设计形成为更多个层。如果需要,则堆积结构140可形成为比图中所示的层的更多的层。将省略对根据另一示例的其中嵌入有电子组件的基板100C的其他重复内容的描述。
图20是示出其中嵌入有电子组件的基板的另一示例的示意性截面图。
参照附图,与根据上述示例的其中嵌入有电子组件的基板100A相比,在根据另一示例的其中嵌入有电子组件的基板100D中,芯结构110形成为更多层。例如,芯结构110可包括:1-1绝缘层111a;1-1布线层112a,嵌入1-1绝缘层111a的下部中;1-2布线层112b,设置在1-1绝缘层111a的上表面上;1-1过孔层113a,穿透1-1绝缘层111a并且将1-1布线层112a与1-2布线层112b电连接;1-2绝缘层111b,设置在1-1绝缘层111a的上表面上并且覆盖1-2布线层112b;1-3布线层112c,设置在1-2绝缘层111b的上表面上;以及1-2过孔层113b,穿透1-2绝缘层111b并且将1-2布线层112b和1-3布线层112c电连接。并且,腔110H可穿透1-1绝缘层111a和1-2绝缘层111b。
另外,与根据上述示例的其中嵌入有电子组件的基板100A相比,在根据另一示例的其中嵌入有电子组件的基板100D中,在包封剂130上进一步设置堆积结构140。堆积结构140包括:第二绝缘主体,包括第二绝缘层141;一个或更多个第三布线层142,设置在第二绝缘主体上或第二绝缘主体中;以及一个或更多个第三过孔层143,设置在第二绝缘主体中。第二钝化层160可设置在堆积结构140上。第二钝化层160可具有使第三布线层142的至少一部分暴露的多个第二开口161。
如上所述,作为本公开的各种效果之一,可提供一种具有优异的散热效果的电子组件嵌入式基板(即,其中嵌入有电子组件的基板)。
作为本公开的各种效果中的另一效果,可提供一种具有优异的布线设计效率的其中嵌入有电子组件的基板。
在示例性实施例中,为了便于描述,术语“侧区域”、“侧表面”等可用于指示沿左/右方向形成的表面,术语“下侧”、“下部”、“下表面”等可用于指示相对于附图中的截面朝下的方向,并且术语“上侧”、“上部”、“上表面”等可用于指示与上述方向相反的方向(即,相对于附图中的截面朝上的方向)。元件设置在侧区域、上侧、上部区域或下部区域上的概念可包括其中元件在各个方向上与被构造为基准的元件直接接触的构造以及其中元件不与基准元件直接接触的构造。为了便于描述,这些术语可如上定义,并且示例性实施例的范围不受上述术语特别限制。
在示例性实施例中,术语“连接”不仅可指“直接连接”,而且还包括通过粘合层等方式的“间接连接”。此外,术语“电连接”可包括其中元件“被物理连接”的情况和其中元件“未被物理连接”的情况两者。此外,术语“第一”、“第二”等可用于将一个元件与另一元件区分开,并且不限制与元件相关的顺序和/或重要性等。在一些情况下,在不脱离示例性实施例的范围的情况下,第一元件可被称为第二元件,类似地,第二元件可被称为第一元件。
在示例性实施例中,术语“示例性实施例”可以不指示同一个示例性实施例,而是可被提供以描述和强调每个示例性实施例的不同的独特特征。可实施上面提出的示例性实施例,而不排除与其他示例性实施例的特征组合的可能性。例如,除非另有说明,否则即使在一个示例性实施例中描述的特征未在另一示例性实施例中描述,该描述也可被理解为与另一示例性实施例相关。
在示例性实施例中使用的术语仅仅用于描述示例性实施例,并不意在限制本公开。除非另有说明,否则单数术语也包括复数形式。
虽然上面已经示出和描述了示例性实施例,但是对于本领域技术人员将显而易见的是,在不脱离本发明的由所附权利要求限定的范围的情况下,可做出修改和变型。

Claims (21)

1.一种其中嵌入有电子组件的基板,包括:
芯结构,包括第一绝缘主体、多个第一布线层以及一个或更多个第一过孔层,所述多个第一布线层设置在所述第一绝缘主体上和/或所述第一绝缘主体中,所述一个或更多个第一过孔层设置在所述第一绝缘主体中,所述芯结构具有穿透所述第一绝缘主体的至少一部分的腔;
第一金属层,设置在所述腔的底表面上;
电子组件,设置在所述腔中的所述第一金属层上;以及
第二金属层,设置在所述电子组件的侧表面上。
2.根据权利要求1所述的其中嵌入有电子组件的基板,其中,所述第二金属层与所述电子组件的所述侧表面物理接触。
3.根据权利要求2所述的其中嵌入有电子组件的基板,其中,所述第二金属层围绕所述电子组件的侧表面。
4.根据权利要求1-3中任一项所述的其中嵌入有电子组件的基板,其中,所述第二金属层与所述第一金属层物理接触。
5.根据权利要求4所述的其中嵌入有电子组件的基板,其中,所述第一金属层具有槽部,并且
所述第二金属层的一部分设置在所述槽部中。
6.根据权利要求5所述的其中嵌入有电子组件的基板,其中,所述槽部沿着所述电子组件的侧表面延伸。
7.根据权利要求1-3中任一项所述的其中嵌入有电子组件的基板,所述基板还包括设置在所述芯结构下方的第一钝化层,所述第一钝化层具有多个第一开口,所述多个第一开口使所述多个第一布线层中的设置在最下侧的第一布线层的至少一部分和所述第一金属层的至少一部分暴露。
8.根据权利要求1-3中任一项所述的其中嵌入有电子组件的基板,所述基板还包括:
包封剂,设置在所述芯结构上,设置在所述腔的至少一部分中,并且使所述电子组件的至少一部分嵌入所述包封剂中;
第二布线层,设置在所述包封剂上;以及
第二过孔层,穿透所述包封剂,并且将所述第二布线层连接到所述多个第一布线层和所述电子组件中的每者。
9.根据权利要求8所述的其中嵌入有电子组件的基板,所述基板还包括第二钝化层,所述第二钝化层设置在所述包封剂上并且具有使所述第二布线层的至少一部分暴露的多个第二开口。
10.根据权利要求8所述的其中嵌入有电子组件的基板,所述基板还包括:
堆积结构,包括第二绝缘主体、一个或更多个第三布线层以及一个或更多个第三过孔层,所述第二绝缘主体设置在所述包封剂上,所述一个或更多个第三布线层设置在所述第二绝缘主体上或所述第二绝缘主体中,所述一个或更多个第三过孔层设置在所述第二绝缘主体中;以及
第二钝化层,设置在所述堆积结构上,并且具有多个第二开口,所述多个第二开口使所述一个或更多个第三布线层中的设置在最上侧的第三布线层的至少一部分暴露。
11.根据权利要求1-3中任一项所述的其中嵌入有电子组件的基板,其中,所述电子组件具有第一表面和第二表面,在所述第一表面上设置有连接垫,所述第二表面与所述第一表面相对,并且所述第二表面通过粘合膜附接到所述第一金属层。
12.根据权利要求1-3中任一项所述的其中嵌入有电子组件的基板,其中,所述第一绝缘主体包括第一芯绝缘层,所述多个第一布线层包括第一芯布线层和第二芯布线层,所述第一过孔层包括第一芯过孔层,所述第一芯布线层嵌入所述第一芯绝缘层的下部中,所述第二芯布线层设置在所述第一芯绝缘层的上表面上,所述第一芯过孔层穿透所述第一芯绝缘层并且连接所述第一芯布线层和所述第二芯布线层,
所述腔穿透所述第一芯绝缘层,
所述第一金属层位于与所述第一芯布线层的高度相同的高度处,并且
所述第一金属层的至少一部分嵌入所述第一芯绝缘层中。
13.根据权利要求12所述的其中嵌入有电子组件的基板,其中,所述第一绝缘主体还包括第二芯绝缘层,所述多个第一布线层还包括第三芯布线层,所述第一过孔层还包括第二芯过孔层,所述第二芯绝缘层设置在所述第一芯绝缘层的上表面上以覆盖所述第二芯布线层,所述第三芯布线层设置在所述第二芯绝缘层的上表面上,所述第二芯过孔层穿透所述第二芯绝缘层并且连接所述第二芯布线层和所述第三芯布线层,
所述腔还穿透所述第二芯绝缘层。
14.根据权利要求12所述的其中嵌入有电子组件的基板,其中,所述第一芯绝缘层的下表面和所述第一芯布线层的下表面之间具有第一台阶,并且
所述第一金属层的在通过所述腔暴露的区域中的上表面和所述第一金属层的在嵌入所述第一芯绝缘层中的区域中的上表面之间具有第二台阶。
15.一种其中嵌入有电子组件的基板,包括:
芯结构,包括绝缘主体、多个布线层以及一个或更多个过孔层,所述多个布线层设置在所述绝缘主体上和/或所述绝缘主体中,所述一个或更多个过孔层设置在所述绝缘主体中,所述芯结构具有穿透所述绝缘主体的至少一部分的腔;
金属层,设置在所述腔的底表面上,并且具有图案孔;以及
电子组件,设置在所述腔中的所述金属层上。
16.根据权利要求15所述的其中嵌入有电子组件的基板,其中,所述金属层包括通过所述图案孔彼此间隔开的多个金属图案,
所述多个金属图案中的至少一部分金属图案连接到所述多个布线层中的至少一个接地图案,并且
所述多个金属图案中的剩余的金属图案中的至少一者连接到所述多个布线层中的至少一个信号图案。
17.一种基板,包括:
芯结构,具有腔,并且包括绝缘主体、一个或更多个第一布线层以及一个或更多个过孔层,所述一个或更多个第一布线层设置在所述绝缘主体上和/或所述绝缘主体中,所述一个或更多个过孔层设置在所述绝缘主体中并且连接到所述一个或更多个第一布线层;
第一金属层,设置在所述绝缘主体上或所述绝缘主体中;
电子组件,设置在所述腔中的所述第一金属层上;以及
第二金属层,从所述第一金属层延伸以与所述电子组件的侧表面接触。
18.根据权利要求17所述的基板,其中,所述第二金属层覆盖所述电子组件的侧表面。
19.根据权利要求17所述的基板,所述基板还包括包含绝缘材料的包封剂,所述包封剂设置在所述芯结构上,并且具有设置在所述腔中的部分以使所述电子组件的至少一部分嵌入所述包封剂中,
其中,所述包封剂的设置在所述腔中的所述部分设置在所述第二金属层和所述芯结构之间。
20.根据权利要求17-19中任一项所述的基板,其中,所述第一金属层包括彼此间隔开的多个金属图案。
21.根据权利要求17或18所述的基板,其中,所述电子组件具有其上设置有连接垫的第一表面和与所述第一表面相对的第二表面,
所述第二表面面向所述第一金属层,并且
所述基板还包括:
包封剂,设置在所述芯结构上;
第二布线层,设置在所述包封剂上;以及
第二过孔层,设置在所述包封剂中,并且将所述第二布线层连接到所述一个或更多个第一布线层中的至少一者和/或所述连接垫。
CN202110609136.2A 2020-07-17 2021-06-01 其中嵌入有电子组件的基板 Pending CN113948482A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020200088970A KR20220010280A (ko) 2020-07-17 2020-07-17 전자부품 내장기판
KR10-2020-0088970 2020-07-17

Publications (1)

Publication Number Publication Date
CN113948482A true CN113948482A (zh) 2022-01-18

Family

ID=79293118

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110609136.2A Pending CN113948482A (zh) 2020-07-17 2021-06-01 其中嵌入有电子组件的基板

Country Status (3)

Country Link
US (1) US11490503B2 (zh)
KR (1) KR20220010280A (zh)
CN (1) CN113948482A (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20220130916A (ko) * 2021-03-19 2022-09-27 삼성전기주식회사 전자부품 내장기판
CN116209134A (zh) * 2021-11-30 2023-06-02 鹏鼎控股(深圳)股份有限公司 电路板总成及其制造方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101049390B1 (ko) * 2005-12-16 2011-07-14 이비덴 가부시키가이샤 다층 프린트 배선판 및 그 제조 방법
KR20110139462A (ko) * 2010-06-23 2011-12-29 삼성전기주식회사 절연수지 조성물 및 이를 이용하여 제조된 인쇄회로기판
KR101775150B1 (ko) * 2010-07-30 2017-09-05 삼성전자주식회사 다층 라미네이트 패키지 및 그 제조방법
JP2013211480A (ja) 2012-03-30 2013-10-10 Fujikura Ltd 部品内蔵基板
KR101420526B1 (ko) * 2012-11-29 2014-07-17 삼성전기주식회사 전자부품 내장기판 및 그 제조방법
KR101497230B1 (ko) * 2013-08-20 2015-02-27 삼성전기주식회사 전자부품 내장기판 및 전자부품 내장기판 제조방법
KR102016487B1 (ko) * 2014-10-28 2019-09-02 삼성전기주식회사 인쇄회로기판 및 그 제조방법

Also Published As

Publication number Publication date
US11490503B2 (en) 2022-11-01
KR20220010280A (ko) 2022-01-25
US20220022310A1 (en) 2022-01-20

Similar Documents

Publication Publication Date Title
TW201724414A (zh) 扇出型半導體封裝及其製造方法
TWI636546B (zh) 電子元件封裝
CN111725148B (zh) 半导体封装件
CN111146188A (zh) 半导体封装件
CN113948482A (zh) 其中嵌入有电子组件的基板
CN112447655A (zh) 封装件基板
US11658124B2 (en) Connection structure embedded substrate
US20220053631A1 (en) Component package and printed circuit board for the same
CN113905516A (zh) 电子组件嵌入式基板
US20230245989A1 (en) Printed circuit board and electronic component package including the same
CN112951792A (zh) 电子组件嵌入式基板
US11587878B2 (en) Substrate having electronic component embedded therein
US10932368B1 (en) Substrate-embedded electronic component
CN114245561A (zh) 印刷电路板和基板
CN113013109A (zh) 嵌有电子组件的基板
CN112996224A (zh) 嵌有电子组件的基板
CN112992844A (zh) 电子组件嵌入式基板
US11910527B2 (en) Substrate with electronic component embedded therein
US11948849B2 (en) Package-embedded board
US11075156B2 (en) Substrate having electronic component embedded therein
US20240040698A1 (en) Printed circuit board
CN114269060A (zh) 电子组件嵌入式基板
CN114340138A (zh) 印刷电路板和包括该印刷电路板的电子组件封装件
CN116437565A (zh) 印刷电路板和电子组件封装件
CN114615800A (zh) 印刷电路板

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination