CN113939898A - 用于切割半导体晶片的方法和由该方法制成的半导体器件 - Google Patents

用于切割半导体晶片的方法和由该方法制成的半导体器件 Download PDF

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Publication number
CN113939898A
CN113939898A CN202080043132.6A CN202080043132A CN113939898A CN 113939898 A CN113939898 A CN 113939898A CN 202080043132 A CN202080043132 A CN 202080043132A CN 113939898 A CN113939898 A CN 113939898A
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CN
China
Prior art keywords
region
semiconductor wafer
laser beam
die
semiconductor
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Pending
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CN202080043132.6A
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English (en)
Chinese (zh)
Inventor
凯文·施奈德
亚历山大·康波斯
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Wofu Semiconductor Co ltd
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Wofu Semiconductor Co ltd
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Application filed by Wofu Semiconductor Co ltd filed Critical Wofu Semiconductor Co ltd
Publication of CN113939898A publication Critical patent/CN113939898A/zh
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66431—Unipolar field-effect transistors with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0095—Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Dicing (AREA)
  • Laser Beam Processing (AREA)
CN202080043132.6A 2019-06-13 2020-06-12 用于切割半导体晶片的方法和由该方法制成的半导体器件 Pending CN113939898A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US16/440,063 US11289378B2 (en) 2019-06-13 2019-06-13 Methods for dicing semiconductor wafers and semiconductor devices made by the methods
US16/440,063 2019-06-13
PCT/US2020/037440 WO2020252265A1 (en) 2019-06-13 2020-06-12 Methods for dicing semiconductor wafers and semiconductor devices made by the methods

Publications (1)

Publication Number Publication Date
CN113939898A true CN113939898A (zh) 2022-01-14

Family

ID=73744750

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202080043132.6A Pending CN113939898A (zh) 2019-06-13 2020-06-12 用于切割半导体晶片的方法和由该方法制成的半导体器件

Country Status (6)

Country Link
US (2) US11289378B2 (de)
EP (1) EP3963623A4 (de)
JP (1) JP7465288B2 (de)
KR (1) KR20220031016A (de)
CN (1) CN113939898A (de)
WO (1) WO2020252265A1 (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20210202318A1 (en) * 2019-12-27 2021-07-01 Micron Technology, Inc. Methods of forming semiconductor dies with perimeter profiles for stacked die packages

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* Cited by examiner, † Cited by third party
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JP2003151924A (ja) 2001-08-28 2003-05-23 Tokyo Seimitsu Co Ltd ダイシング方法およびダイシング装置
SG139508A1 (en) 2001-09-10 2008-02-29 Micron Technology Inc Wafer dicing device and method
JP2003332270A (ja) * 2002-05-15 2003-11-21 Renesas Technology Corp 半導体装置およびその製造方法
US6945844B2 (en) 2002-07-26 2005-09-20 Cree, Inc. Methods for dynamically controlling a semiconductor dicing saw
JP2005064231A (ja) * 2003-08-12 2005-03-10 Disco Abrasive Syst Ltd 板状物の分割方法
JP2005064230A (ja) * 2003-08-12 2005-03-10 Disco Abrasive Syst Ltd 板状物の分割方法
US7005317B2 (en) * 2003-10-27 2006-02-28 Intel Corporation Controlled fracture substrate singulation
US7008861B2 (en) 2003-12-11 2006-03-07 Cree, Inc. Semiconductor substrate assemblies and methods for preparing and dicing the same
US7550367B2 (en) * 2004-08-17 2009-06-23 Denso Corporation Method for separating semiconductor substrate
JP2006073690A (ja) 2004-09-01 2006-03-16 Disco Abrasive Syst Ltd ウエーハの分割方法
US9034731B2 (en) * 2005-02-03 2015-05-19 Stats Chippac Ltd. Integrated, integrated circuit singulation system
JP2006253402A (ja) * 2005-03-10 2006-09-21 Nec Electronics Corp 半導体装置の製造方法
JP4809632B2 (ja) * 2005-06-01 2011-11-09 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP4942313B2 (ja) * 2005-07-07 2012-05-30 株式会社ディスコ ウエーハのレーザー加工方法
US7176053B1 (en) 2005-08-16 2007-02-13 Organicid, Inc. Laser ablation method for fabricating high performance organic devices
KR20080046658A (ko) 2005-09-16 2008-05-27 크리 인코포레이티드 실리콘 카바이드 전력 소자들을 그 상에 가지는 반도체웨이퍼들의 가공방법들
JP2007134454A (ja) * 2005-11-09 2007-05-31 Toshiba Corp 半導体装置の製造方法
WO2007055010A1 (ja) * 2005-11-10 2007-05-18 Renesas Technology Corp. 半導体装置の製造方法および半導体装置
JP2008053500A (ja) * 2006-08-25 2008-03-06 Disco Abrasive Syst Ltd ウエーハの分割方法
US8629532B2 (en) * 2007-05-08 2014-01-14 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor wafer with assisting dicing structure and dicing method thereof
JP4645863B2 (ja) 2008-09-09 2011-03-09 カシオ計算機株式会社 半導体装置の製造方法
US8211781B2 (en) * 2008-11-10 2012-07-03 Stanley Electric Co., Ltd. Semiconductor manufacturing method
JP5487749B2 (ja) 2009-06-17 2014-05-07 富士通株式会社 半導体装置及びその製造方法
JP5758116B2 (ja) * 2010-12-16 2015-08-05 株式会社ディスコ 分割方法
US8809120B2 (en) * 2011-02-17 2014-08-19 Infineon Technologies Ag Method of dicing a wafer
EP2762286B1 (de) 2013-01-31 2015-07-01 ams AG Zerteilungsverfahren
DE102015100783A1 (de) * 2015-01-20 2016-07-21 Infineon Technologies Ag Verfahren zum Zertrennen eines Wafers und Halbleiterchip
JP2016134523A (ja) 2015-01-20 2016-07-25 株式会社東芝 半導体装置及びその製造方法
JP6532273B2 (ja) 2015-04-21 2019-06-19 株式会社ディスコ ウェーハの加工方法
JP6478801B2 (ja) * 2015-05-19 2019-03-06 株式会社ディスコ ウエーハの加工方法
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JP2018156973A (ja) 2017-03-15 2018-10-04 株式会社ディスコ ウェーハの加工方法
JP6890885B2 (ja) * 2017-04-04 2021-06-18 株式会社ディスコ 加工方法
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JP6836491B2 (ja) 2017-11-07 2021-03-03 株式会社荏原製作所 デバイスが形成された基板を個々のチップに分割するための方法および装置

Also Published As

Publication number Publication date
KR20220031016A (ko) 2022-03-11
JP2022536751A (ja) 2022-08-18
EP3963623A1 (de) 2022-03-09
JP7465288B2 (ja) 2024-04-10
WO2020252265A1 (en) 2020-12-17
US20220216108A1 (en) 2022-07-07
US20200395246A1 (en) 2020-12-17
EP3963623A4 (de) 2023-06-07
US11289378B2 (en) 2022-03-29

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