CN113498544B - 碳化硅半导体装置及其制造方法 - Google Patents
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- H—ELECTRICITY
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/66—Vertical DMOS [VDMOS] FETs
- H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
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- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/66—Vertical DMOS [VDMOS] FETs
- H10D30/664—Inverted VDMOS transistors, i.e. source-down VDMOS transistors
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- H10D12/01—Manufacture or treatment
- H10D12/031—Manufacture or treatment of IGBTs
- H10D12/032—Manufacture or treatment of IGBTs of vertical IGBTs
- H10D12/038—Manufacture or treatment of IGBTs of vertical IGBTs having a recessed gate, e.g. trench-gate IGBTs
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- H10D12/441—Vertical IGBTs
- H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
- H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
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- H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
- H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
- H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
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- H10D62/054—Forming charge compensation regions, e.g. superjunctions by high energy implantations in bulk semiconductor bodies, e.g. forming pillars
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- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
- H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]
- H10D62/109—Reduced surface field [RESURF] PN junction structures
- H10D62/111—Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures
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- H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
- H10D62/149—Source or drain regions of field-effect devices
- H10D62/151—Source or drain regions of field-effect devices of IGFETs
- H10D62/152—Source regions of DMOS transistors
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- H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
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- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
- H10D64/512—Disposition of the gate electrodes, e.g. buried gates
- H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates
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- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/34—Deposited materials, e.g. layers
- H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
- H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
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- H10P14/34—Deposited materials, e.g. layers
- H10P14/3438—Doping during depositing
- H10P14/3441—Conductivity type
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- H10P30/21—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically active species
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- H10P30/218—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the implantation in a compound semiconductor of both electrically active and inactive species in the same semiconductor region to be doped n-type or p-type
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- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/01—Manufacture or treatment
- H10D62/051—Forming charge compensation regions, e.g. superjunctions
- H10D62/052—Forming charge compensation regions, e.g. superjunctions by forming stacked epitaxial layers
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- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
- H10D62/149—Source or drain regions of field-effect devices
- H10D62/151—Source or drain regions of field-effect devices of IGFETs
- H10D62/156—Drain regions of DMOS transistors
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Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311330705.5A CN117276345A (zh) | 2019-02-27 | 2020-02-13 | 碳化硅半导体装置的制造方法 |
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2019-034380 | 2019-02-27 | ||
| JP2019034380 | 2019-02-27 | ||
| JP2020008376A JP7140148B2 (ja) | 2019-02-27 | 2020-01-22 | 炭化珪素半導体装置およびその製造方法 |
| JP2020-008376 | 2020-01-22 | ||
| PCT/JP2020/005592 WO2020175157A1 (ja) | 2019-02-27 | 2020-02-13 | 炭化珪素半導体装置およびその製造方法 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202311330705.5A Division CN117276345A (zh) | 2019-02-27 | 2020-02-13 | 碳化硅半导体装置的制造方法 |
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| Publication Number | Publication Date |
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| CN113498544A CN113498544A (zh) | 2021-10-12 |
| CN113498544B true CN113498544B (zh) | 2023-10-27 |
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| CN202080016354.9A Active CN113498544B (zh) | 2019-02-27 | 2020-02-13 | 碳化硅半导体装置及其制造方法 |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US12057498B2 (https=) |
| JP (1) | JP7140148B2 (https=) |
| CN (1) | CN113498544B (https=) |
Families Citing this family (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE112020007709T5 (de) | 2020-10-22 | 2023-08-03 | Mitsubishi Electric Corporation | Halbleitervorrichtung |
| JP7563750B2 (ja) * | 2021-03-12 | 2024-10-08 | 富士電機株式会社 | 炭化珪素半導体装置の製造方法 |
| JP7613670B2 (ja) | 2021-03-19 | 2025-01-15 | 富士電機株式会社 | 炭化珪素半導体装置および炭化珪素半導体装置の製造方法 |
| JP7543960B2 (ja) * | 2021-03-25 | 2024-09-03 | 株式会社デンソー | 半導体装置とその製造方法 |
| JP7582061B2 (ja) * | 2021-05-14 | 2024-11-13 | 株式会社デンソー | 半導体装置 |
| JP7676979B2 (ja) * | 2021-06-16 | 2025-05-15 | 株式会社デンソー | 炭化珪素半導体装置 |
| JP7187620B1 (ja) * | 2021-07-13 | 2022-12-12 | 昭和電工株式会社 | SiCエピタキシャルウェハ及びSiCエピタキシャルウェハの製造方法 |
| WO2023042359A1 (ja) * | 2021-09-17 | 2023-03-23 | ヌヴォトンテクノロジージャパン株式会社 | 半導体装置 |
| CN113990923B (zh) * | 2021-10-20 | 2023-04-04 | 电子科技大学 | 一种集成沟道二极管的碳化硅双槽mosfet |
| EP4333078A4 (en) | 2021-12-17 | 2024-10-23 | Fuji Electric Co., Ltd. | Semiconductor device |
| KR102593101B1 (ko) * | 2022-03-11 | 2023-10-24 | 화인칩스 주식회사 | 파워 모스펫 |
| JP7694816B2 (ja) * | 2022-04-14 | 2025-06-18 | 株式会社デンソー | 半導体装置とその製造方法 |
| JP7757235B2 (ja) * | 2022-05-13 | 2025-10-21 | 株式会社デンソー | 半導体装置とその製造方法 |
| CN114678277B (zh) * | 2022-05-27 | 2022-08-16 | 深圳平创半导体有限公司 | 中心注入p+屏蔽区的分裂栅平面mosfet及其制造方法 |
| CN115458584B (zh) * | 2022-09-15 | 2025-01-28 | 深圳市森国科科技股份有限公司 | SiC MOSFET器件结构 |
| JP7841410B2 (ja) * | 2022-11-18 | 2026-04-07 | 株式会社デンソー | 炭化珪素半導体装置 |
| JP7798759B2 (ja) * | 2022-12-14 | 2026-01-14 | 株式会社デンソー | 半導体装置の製造方法 |
| CN116314338B (zh) * | 2023-05-18 | 2023-08-01 | 深圳平创半导体有限公司 | 一种半导体结构及其制备方法 |
| DE102023205312A1 (de) | 2023-06-07 | 2024-12-12 | Robert Bosch Gesellschaft mit beschränkter Haftung | Halbleiterbauelement mit reduzierter spreizung des flächenspezifischen durchgangswiderstands und mit verbesserter kurzschlussfähigkeit |
| CN118888592A (zh) * | 2024-07-18 | 2024-11-01 | 长飞先进半导体(武汉)有限公司 | 功率器件及制备方法、功率模块、功率转换电路和车辆 |
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| JP2009194065A (ja) * | 2008-02-13 | 2009-08-27 | Denso Corp | 炭化珪素半導体装置およびその製造方法 |
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- 2020-01-22 JP JP2020008376A patent/JP7140148B2/ja active Active
- 2020-02-13 CN CN202080016354.9A patent/CN113498544B/zh active Active
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- 2021-08-24 US US17/410,044 patent/US12057498B2/en active Active
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| JP2009194065A (ja) * | 2008-02-13 | 2009-08-27 | Denso Corp | 炭化珪素半導体装置およびその製造方法 |
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| US20210384343A1 (en) | 2021-12-09 |
| CN113498544A (zh) | 2021-10-12 |
| US12057498B2 (en) | 2024-08-06 |
| JP7140148B2 (ja) | 2022-09-21 |
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