CN113498544B - 碳化硅半导体装置及其制造方法 - Google Patents

碳化硅半导体装置及其制造方法 Download PDF

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CN113498544B
CN113498544B CN202080016354.9A CN202080016354A CN113498544B CN 113498544 B CN113498544 B CN 113498544B CN 202080016354 A CN202080016354 A CN 202080016354A CN 113498544 B CN113498544 B CN 113498544B
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CN113498544A (zh
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竹内有一
铃木克己
山下侑佑
加藤武宽
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Denso Corp
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Denso Corp
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/64Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66Vertical DMOS [VDMOS] FETs
    • H10D30/668Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • HELECTRICITY
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    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/64Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66Vertical DMOS [VDMOS] FETs
    • H10D30/664Inverted VDMOS transistors, i.e. source-down VDMOS transistors
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    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01Manufacture or treatment
    • H10D12/031Manufacture or treatment of IGBTs
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    • H10D12/00Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01Manufacture or treatment
    • H10D12/031Manufacture or treatment of IGBTs
    • H10D12/032Manufacture or treatment of IGBTs of vertical IGBTs
    • H10D12/038Manufacture or treatment of IGBTs of vertical IGBTs having a recessed gate, e.g. trench-gate IGBTs
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    • H10D12/00Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411Insulated-gate bipolar transistors [IGBT]
    • H10D12/441Vertical IGBTs
    • H10D12/461Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
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    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0297Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
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    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
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    • H10D62/054Forming charge compensation regions, e.g. superjunctions by high energy implantations in bulk semiconductor bodies, e.g. forming pillars
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    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/109Reduced surface field [RESURF] PN junction structures
    • H10D62/111Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures
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    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
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    • H10D62/13Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149Source or drain regions of field-effect devices
    • H10D62/151Source or drain regions of field-effect devices of IGFETs 
    • H10D62/152Source regions of DMOS transistors
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    • H10D62/17Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
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    • H10D62/80Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
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    • H10D64/27Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311Gate electrodes for field-effect devices
    • H10D64/411Gate electrodes for field-effect devices for FETs
    • H10D64/511Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512Disposition of the gate electrodes, e.g. buried gates
    • H10D64/513Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates
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    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34Deposited materials, e.g. layers
    • H10P14/3402Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
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    • H10P14/3438Doping during depositing
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    • H10P30/204Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
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    • H10P30/218Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the implantation in a compound semiconductor of both electrically active and inactive species in the same semiconductor region to be doped n-type or p-type
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    • H10D62/13Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149Source or drain regions of field-effect devices
    • H10D62/151Source or drain regions of field-effect devices of IGFETs 
    • H10D62/156Drain regions of DMOS transistors
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JP2019-034380 2019-02-27
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JP2020008376A JP7140148B2 (ja) 2019-02-27 2020-01-22 炭化珪素半導体装置およびその製造方法
JP2020-008376 2020-01-22
PCT/JP2020/005592 WO2020175157A1 (ja) 2019-02-27 2020-02-13 炭化珪素半導体装置およびその製造方法

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JP7676979B2 (ja) * 2021-06-16 2025-05-15 株式会社デンソー 炭化珪素半導体装置
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CN113990923B (zh) * 2021-10-20 2023-04-04 电子科技大学 一种集成沟道二极管的碳化硅双槽mosfet
EP4333078A4 (en) 2021-12-17 2024-10-23 Fuji Electric Co., Ltd. Semiconductor device
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JP7694816B2 (ja) * 2022-04-14 2025-06-18 株式会社デンソー 半導体装置とその製造方法
JP7757235B2 (ja) * 2022-05-13 2025-10-21 株式会社デンソー 半導体装置とその製造方法
CN114678277B (zh) * 2022-05-27 2022-08-16 深圳平创半导体有限公司 中心注入p+屏蔽区的分裂栅平面mosfet及其制造方法
CN115458584B (zh) * 2022-09-15 2025-01-28 深圳市森国科科技股份有限公司 SiC MOSFET器件结构
JP7841410B2 (ja) * 2022-11-18 2026-04-07 株式会社デンソー 炭化珪素半導体装置
JP7798759B2 (ja) * 2022-12-14 2026-01-14 株式会社デンソー 半導体装置の製造方法
CN116314338B (zh) * 2023-05-18 2023-08-01 深圳平创半导体有限公司 一种半导体结构及其制备方法
DE102023205312A1 (de) 2023-06-07 2024-12-12 Robert Bosch Gesellschaft mit beschränkter Haftung Halbleiterbauelement mit reduzierter spreizung des flächenspezifischen durchgangswiderstands und mit verbesserter kurzschlussfähigkeit
CN118888592A (zh) * 2024-07-18 2024-11-01 长飞先进半导体(武汉)有限公司 功率器件及制备方法、功率模块、功率转换电路和车辆

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US20210384343A1 (en) 2021-12-09
CN113498544A (zh) 2021-10-12
US12057498B2 (en) 2024-08-06
JP7140148B2 (ja) 2022-09-21

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