CN113394183A - 层叠型半导体装置以及该层叠型半导体装置的制造方法 - Google Patents

层叠型半导体装置以及该层叠型半导体装置的制造方法 Download PDF

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CN113394183A
CN113394183A CN202010893405.8A CN202010893405A CN113394183A CN 113394183 A CN113394183 A CN 113394183A CN 202010893405 A CN202010893405 A CN 202010893405A CN 113394183 A CN113394183 A CN 113394183A
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electrode
substrate
buffer
insulating structure
semiconductor device
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李南宰
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SK Hynix Inc
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SK Hynix Inc
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Abstract

提供了一种层叠型半导体装置以及该层叠型半导体装置的制造方法。该层叠型半导体装置包括：多个半导体芯片，其层叠以彼此交叠；多个贯通电极，其分别穿透半导体芯片，多个贯通电极彼此结合；以及多个空隙，其分别掩埋在贯通电极中。

Description

层叠型半导体装置以及该层叠型半导体装置的制造方法
技术领域
本公开总体上涉及层叠型半导体装置以及该层叠型半导体装置的制造方法，更具体地，涉及一种包括贯通电极的层叠型半导体装置以及该层叠型半导体装置的制造方法。
背景技术
在层叠型半导体装置中，半导体芯片彼此交叠，以使得半导体装置的集成度可改进。彼此交叠的半导体芯片可通过贯通电极彼此电连接。贯通电极可减小彼此交叠的半导体芯片之间的互连结构的长度，因此可提供具有改进的数据传输速度的半导体装置。
发明内容
根据本公开的一方面，可提供一种层叠型半导体装置，该层叠型半导体装置包括：多个半导体芯片，其层叠以彼此交叠；多个贯通电极，其分别穿透半导体芯片，其中，多个贯通电极彼此结合；以及多个空隙，其分别掩埋在贯通电极中。
根据本公开的另一方面，可提供一种制造层叠型半导体装置的方法，该方法包括以下步骤：形成由掩埋有第一空隙的第一贯通电极穿透的第一半导体芯片；形成由掩埋有第二空隙的第二贯通电极穿透的第二半导体芯片；使第一半导体芯片在第二半导体芯片上对齐；以及将第一贯通电极结合到第二贯通电极。
附图说明
在附图中，为了例示清晰，尺寸可能被夸大。将理解，当元件被称为在两个元件“之间”时，其可以是这两个元件之间的仅有元件，或者也可存在一个或更多个中间元件。相似的标号始终表示相似的元件。
图1是示意性地示出根据本公开的实施方式的层叠型半导体装置的截面图。
图2是示出图1所示的区域A的放大截面图。
图3是示出根据本公开的实施方式的存储器系统的框图。
图4是示出根据本公开的实施方式的层叠型存储器装置的截面图。
图5是示出根据本公开的实施方式的存储器系统的示图。
图6是示出根据本公开的实施方式的存储器系统的框图。
图7是示出根据本公开的实施方式的计算系统的框图。
图8是示出根据本公开的实施方式的CMOS图像传感器的示图。
图9A、图9B、图9C、图9D、图9E、图9F、图9G、图9H、图9I、图9J、图10A和图10B是示出根据本公开的实施方式的层叠型半导体装置的制造方法的截面图。
具体实施方式
为了描述根据本公开的概念的实施方式，本文所公开的具体结构或功能描述仅是例示性的。根据本公开的概念的实施方式可按照各种形式实现，不应被解释为限于本文中所阐述的实施方式。
以下，使用术语“第一”和“第二”来将一个组件与另一组件相区分。例如，在不脱离根据本公开的概念的范围的情况下，第一组件可被称为第二组件，类似地，第二组件可被称为第一组件。
实施方式提供一种能够改进结合结构的稳定性的层叠型半导体装置以及该层叠型半导体装置的制造方法。
图1是示意性地示出根据本公开的实施方式的层叠型半导体装置10的截面图。图1是沿着设置有层叠型半导体装置10的贯通电极TE1至TEn的通孔区域(through viaregion)截取的截面图。
参照图1，层叠型半导体装置10可包括多个半导体芯片C1至Cn(n是2或更大的自然数)。半导体芯片C1至Cn可层叠以彼此交叠。半导体芯片C1至Cn可被贯通电极TE1至TEn穿透。
穿透半导体芯片C1至Cn中的每一个的贯通电极的数量和布置方式可各种各样。分别穿透不同的半导体芯片C1至Cn的贯通电极TE1至TEn可排成一条线。诸如凸块的结合介质可设置在贯通电极之间以实现贯通电极之间的电连接。在本公开的实施方式中，排成一条线的贯通电极TE1至TEn可彼此直接结合而没有诸如凸块的任何介质，以彼此电连接。彼此连接的贯通电极TE1至TEn可用作数据传输路径。
半导体芯片C1至Cn可以是相同类型的芯片或不同类型的芯片。在实施方式中，半导体芯片C1至Cn中的每一个可以是存储器芯片。在另一实施方式中，半导体芯片C1至Cn中的至少一个可对应于逻辑芯片，其它可对应于存储器芯片。在另一实施方式中，半导体芯片C1至Cn中的至少一个可对应于逻辑芯片，其它可对应于像素芯片。
贯通电极TE1至TEn中的每一个可包括缓冲部BP以及从缓冲部BP延伸的垂直部VP。上贯通电极的垂直部VP和下贯通电极的缓冲部彼此结合，以使得贯通电极TE1至TEn彼此电连接。
以下，半导体芯片C1至Cn当中的设置在相对上部的半导体芯片(例如，C2)被指定为第一半导体芯片，半导体芯片C1至Cn当中的设置在相对下部的半导体芯片(例如，C3)被指定为第二半导体芯片。另外，贯通电极TE1至TEn当中的设置在相对上部的贯通电极(例如，TE2)由第一贯通电极表示，贯通电极TE1至TEn当中的设置在相对下部的贯通电极(例如，TE3)由第二贯通电极表示。
图2是示出图1所示的区域A的放大截面图。参照图1描述的贯通电极TE1至TEn的缓冲部BP可包括第一贯通电极TE2的第一缓冲部BPa和第二贯通电极TE3的第二缓冲部BPb，参照图1描述的贯通电极TE1至TEn的垂直部VP可包括第一贯通电极TE2的第一垂直部VPa和第二贯通电极TE3的第二垂直部VPb。
参照图2，第一半导体芯片C2和第二半导体芯片C3中的每一个可包括基板110a或110b、第一绝缘结构120a或120b、导电焊盘130a或130b以及第二绝缘结构140a或140b。
第一半导体芯片C2和第二半导体芯片C3的基板110a和110b中的每一个可具有第一表面SU1a或SU1b以及与第一表面SU1a或SU1b相对的第二表面SU2a或SU2b。第一半导体芯片C2和第二半导体芯片C3的第一绝缘结构120a和120b可分别形成在基板110a和110b的第一表面SU1a和SU1b上。第一半导体芯片C2的导电焊盘130a可面向基板110a的第一表面SU1a并且第一绝缘结构120a插置在它们之间，并且第二半导体芯片C3的导电焊盘130b可面向基板110b的第一表面SU1b并且第一绝缘结构120b插置在它们之间。第一半导体芯片C2和第二半导体芯片C3的第二绝缘结构140a和140b可形成为分别覆盖第一绝缘结构120a的设置有导电焊盘130a的表面以及第一绝缘结构120b的设置有导电焊盘130b的表面。
第二半导体芯片C3的基板110b可结合到第一半导体芯片C2的第二绝缘结构140a。第一贯通电极TE2和第二贯通电极TE3中的每一个可填充与之对应的缓冲孔和通路孔(viahole)。换言之，第一贯通电极TE2可填充第一缓冲孔BHa和第一通路孔VHa，第二贯通电极TE3可填充第二缓冲孔BHb和第二通路孔VHb。
第一缓冲孔BHa可从第一表面SU1a朝着第二表面SU2a延伸以穿透第一半导体芯片C2的基板110a。第一通路孔VHa可从第一缓冲孔BHa延伸，并且可穿透第一半导体芯片C2的第一绝缘结构120a、导电焊盘130a和第二绝缘结构140a。第一贯通电极TE2的第一缓冲部BPa可设置在第一缓冲孔BHa中。第一贯通电极TE2的第一垂直部VPa可从第一缓冲部BPa延伸并填充第一通路孔VHa。
第二缓冲孔BHb可从第一表面SU1b朝着第二表面SU2b延伸以穿透第二半导体芯片C3的基板110b。第二通路孔VHb可从第二缓冲孔BHb延伸，并且可穿透第二半导体芯片C3的第一绝缘结构120b、导电焊盘130b和第二绝缘结构140b。第二贯通电极TE3的第二缓冲部BPb可设置在第二缓冲孔BHb中。第二贯通电极TE3的第二垂直部VPb可从第二缓冲部BPb延伸并填充第二通路孔VHb。
第一半导体芯片C2和第二半导体芯片C3的基板110a和110b可通过侧壁绝缘图案151a和151b与第一贯通电极TE2和第二贯通电极TE3绝缘。侧壁绝缘图案151a可在缓冲部BPa和基板110a之间以及垂直部VPa和第一绝缘结构120a之间延伸。侧壁绝缘图案151b可在缓冲部BPb和基板110b之间以及垂直部VPb和第一绝缘结构120b之间延伸。第一贯通电极TE2的第一垂直部VPa和第二贯通电极TE3的第二垂直部VPb可分别与导电焊盘130a和130b接触。在实施方式中，第一贯通电极TE2的第一垂直部VPa可比侧壁绝缘图案151a突出更远以与导电焊盘130a和第二绝缘结构140a接触，第二贯通电极TE3的第一垂直部VPb可比侧壁绝缘图案151b突出更远以与导电焊盘130b和第二绝缘结构140b接触。
空隙可分别掩埋在第一贯通电极TE2和第二贯通电极TE3中。空隙可包括气隙。空隙可包括掩埋在第一贯通电极TE2中的第一空隙159a和掩埋在第二贯通电极TE3中的第二空隙159b。第一垂直部VPa可设置在第一空隙159a和第二空隙159b之间。
第一空隙159a可设置在第一缓冲孔BHa中，并由第一贯通电极TE2的第一缓冲部BPa围绕。即，第一空隙159a可由第一缓冲部BPa密封在第一缓冲孔BHa中。
第二空隙159b可设置在第二缓冲孔BHb中，并由第二贯通电极TE3的第二缓冲部BPb围绕。即，第二空隙159b可由第二缓冲部BPb密封在第二缓冲孔BHb中。
第一缓冲孔BHa和第二缓冲孔BHb中的每一个可具有比第一通路孔VHa和第二通路孔VHb中的每一个的宽度更宽的宽度。因此，图1所示的缓冲部BP的宽度WB可被限定为大于垂直部VP的宽度WA。此外，第一空隙159a和第二空隙159b可形成在第一缓冲孔BHa和第二缓冲孔BHb中。在实施方式中，第一缓冲孔BHa和第二缓冲孔BHb中的每一个可具有在第一贯通电极TE2和第二贯通电极TE3层叠的层叠方向上延伸的弯曲侧壁，并且第一通路孔VHa和第二通路孔VHb中的每一个可具有在层叠方向上延伸的平坦侧壁。
第二缓冲部BPb可包括通过在第二缓冲部BPb和第一垂直部VPa之间的结合中产生的压力而向第二气隙159b的内部凹陷的凹陷部RP。
基板110a和110b中的每一个可以是由硅、锗、砷化镓等制成的半导体基板。
第一绝缘结构120a和120b中的每一个可延伸以覆盖形成在主区域(图中未示出)中的集成电路，并且包括多层绝缘层。
导电焊盘130a和130b中的每一个可连接到设置在与之对应的半导体芯片的主区域中的集成电路。导电焊盘130a和130b可由各种导电材料形成。在实施方式中，导电焊盘130a和130b可包括铝。
第二绝缘结构140a和140b可包括各种绝缘材料。在实施方式中，第二绝缘结构140a和140b可包括氧化硅层。
第一贯通电极TE2和第二贯通电极TE3中的每一个可包括屏障层153a或153b和金属层155a或155b。屏障层153a和153b中的每一个可形成为由钛、氮化钛、钽、氮化钽、钨、氮化钨、镍、氮化镍等制成的单层，或者形成为包括钛和氮化钛的双层。金属层155a和155b中的每一个可包括可通过低温等离子体退火结合的各种金属。在实施方式中，金属层155a和155b中的每一个可包括可在300℃或更低的温度下结合的金属。在实施方式中，金属层155a和155b中的每一个可包括铜。
第一贯通电极TE2和第二贯通电极TE3的金属层155a和155b可彼此结合。金属层155a和155b可分别围绕空隙159a和159b。换言之，第一空隙150a可被掩埋在金属层155a中，第二空隙159b可被掩埋在金属层155b中。
屏障层153a和153b可分别形成在金属层155a和155b的侧壁上。即，屏障层153a和153b可分别设置在金属层155a和侧壁绝缘图案151a之间以及金属层155b和侧壁绝缘图案151b之间。屏障层153a可在金属层155a和导电焊盘130a之间以及金属层155a和第二绝缘结构140a之间延伸。屏障层153b可在金属层155b和导电焊盘130b之间以及金属层155b和第二绝缘结构140b之间延伸。
根据本公开的上述实施方式，各个贯通电极可包括与导电焊盘接触的接触表面、与基板的第二表面相邻的第一结合表面以及与第二绝缘结构的表面相邻的第二结合表面。例如，第一贯通电极TE2可包括与导电焊盘130a接触的接触表面CS、与基板110a的第二表面SU2a相邻的第一结合表面BS1以及与第二绝缘结构140a的表面相邻的第二结合表面BS2。第二结合表面BS2可被设置为接触表面CS。第二绝缘结构140a的表面可与相邻的基板110b的第二表面SU2b接触。
图3是示出根据本公开的实施方式的存储器系统300的框图。
参照图3，存储器系统300可被应用于诸如计算机、数字相机或智能电话的电子装置，以处理数据。
存储器系统300可包括存储控制器310和层叠型存储器装置320。
根据来自主机HOST的访问请求，存储控制器310可向层叠型存储器装置320发送数据或向层叠型存储器装置320提供控制信号。存储控制器310可检测从层叠型存储器装置320读取的数据的错误，并纠正所检测到的错误。
层叠型存储器装置320可包括彼此层叠的两个或更多个存储器芯片330_1至330_n。存储器芯片330_1至330_n中的每一个可包括易失性存储器装置或非易失性存储器装置。例如，存储器芯片330_1至330_n中的每一个可包括动态随机存取存储器(DRAM)、只读存储器(ROM)、掩模ROM(MROM)、可编程ROM(PROM)、可擦除可编程ROM(EPROM)、电可擦除可编程ROM(EEPROM)、NAND闪存、NOR闪存、相变随机存取存储器(PRAM)、磁性RAM(MRAM)、电阻RAM(RRAM)、铁电RAM(FRAM)等。
存储器芯片330_1至330_n可通过参照图1和图2描述的贯通电极彼此结合。
图4是示出根据本公开的实施方式的层叠型存储器装置400的截面图。
层叠型存储器装置400可包括存储器单元阵列区域AR1、外围电路区域AR2和通孔区域AR3。存储器单元阵列区域AR1和外围电路区域AR2可被包括在层叠型存储器装置400的主区域中。通孔区域AR3可以是提供数据传输路径的区域并且其中设置有彼此结合的贯通电极457a和457b。
层叠型存储器装置400可包括彼此交叠的第一存储器芯片MCa和第二存储器芯片MCb。第一存储器芯片MCa和第二存储器芯片MCb中的每一个可包括半导体基板410a或410b、形成在半导体基板410a或410b的表面上的第一绝缘结构420a或420b以及形成在第一绝缘结构420a或420b的表面上的第二绝缘结构440a或440b。
用于阱结构和沟道的各种杂质可被掺杂在半导体基板410a和410b中。隔离层411a和411b可被掩埋在半导体基板410a和410b中。
存储器单元和连接到存储器单元的线可被掩埋在存储器单元阵列区域AR1中的第一绝缘结构420a和420b中的每一个中。尽管图4中举例说明了存储器单元包括DRAM单元结构的情况，但本公开不限于此。导电焊盘431a和431b可被分别掩埋在存储器单元阵列区域AR1中的第二绝缘结构440a和440b中。形成在存储器单元阵列区域AR1中的导电焊盘431a和431b可经由掩埋在第一绝缘结构420a和420b中的线连接到存储器单元。
用于控制存储器单元的操作的外围电路和连接到外围电路的线可被掩埋在外围电路区域AR2中的第一绝缘结构420a和420b中的每一个中。根据从外部(例如，存储控制器)输入的控制信号，外围电路可向存储器单元输入数据或从存储器单元读取数据。导电焊盘433a和433b可分别被掩埋在外围电路区域AR2中的第二绝缘结构440a和440b中。形成在外围电路区域AR2中的导电焊盘433a和433b中的每一个可经由掩埋在与之对应的第一绝缘结构420a或420b中的线连接到与之对应的外围电路。
上述第一绝缘结构420a和420b以及第二绝缘结构440a和440b可延伸到通孔区域AR3。用作层叠型存储器装置400与层叠型存储器装置400的外部(例如，存储控制器)交换数据或信号的路径的贯通电极457a和457b可形成在通孔区域AR3中。贯通电极457a和457b可分别通过侧壁绝缘图案451a和451b与基板410a和410b绝缘，并且分别电连接到设置在外围电路区域AR2中的导电焊盘430a和430b。
贯通电极457a和457b可按与参照图2描述的第一贯通电极TE2和第二贯通电极TE3中的每一个相同的结构形成。
图5是示出根据本公开的实施方式的存储器系统500的示图。
参照图5，存储器系统500可包括安装在中介层(interposer)510上的高带宽存储器装置(HBM)520和处理器530。
HBM 520可通过中介层510连接到处理器530。HBM 520可包括设置在中介层510上的接口芯片521以及层叠在接口芯片521上的存储器芯片523。存储器芯片523和接口芯片521可通过如参照图1描述的贯通电极的结合结构彼此电连接。穿透存储器芯片523和接口芯片521的各个贯通电极可包括如参照图2描述的空隙。
接口芯片521可提供用于处理器530和存储器芯片523之间的通信的接口。
处理器530可包括用于控制各个HBM 520的存储控制器。例如，处理器530可包括内置有存储器控制的图形处理单元(GPU)或中央处理单元(CPU)。
图6是示出根据本公开的实施方式的存储器系统600的框图。
参照图6，存储器系统600可包括存储控制器610和层叠型存储器装置620。
存储控制器610可控制层叠型存储器装置620，并且包括静态随机存取存储器(SRAM)611、中央处理单元(CPU)612、主机接口613、纠错块614和存储器接口615。SRAM 611可用作CPU 612的工作存储器。CPU 612可执行用于存储控制器610的数据交换的总体控制操作。主机接口613设置有连接到存储器系统600的主机Host的数据交换协议。纠错块614检测包括在从层叠型存储器装置620读取的数据中的错误，并纠正所检测到的错误。存储器接口615执行与层叠型存储器装置620的接口。存储控制器610还可包括存储用于与主机Host接口的代码数据等的只读存储器(ROM)。
层叠型存储器装置620可包括多个存储器封装621_1至621_m。存储器封装621_1至621_m中的每一个可按多个存储器芯片623层叠的结构形成。存储器芯片623可通过如参照图1描述的贯通电极的结合结构彼此电连接。穿透存储器芯片623的各个贯通电极可包括如参照图2描述的空隙。
可向存储控制器610和层叠型存储器装置620提供多个通道CH1至CHm。与通道CH1至CHm中的每一个对应的存储器封装可电连接到通道。通道CH1至CHm中的每一个可通过穿透存储器芯片623的贯通电极电连接到与之对应的存储器封装。
上述存储器系统600可以是层叠型存储器装置620和存储控制器610彼此联接的存储卡或固态驱动器(SSD)。例如，当存储器系统600是SSD时，存储控制器610可通过诸如通用串行总线(USB)协议、多媒体卡(MMC)协议、外围组件互连(PCI)协议、高速PCI(PCI-E)协议、高级技术附件(ATA)协议、串行ATA(SATA)协议、并行ATA(PATA)协议、小型计算机小型接口(SCSI)协议、增强小型磁盘接口(ESDI)协议和集成驱动电子设备(IDE)协议的各种接口协议之一来与外部(例如，主机)通信。
图7是示出根据本公开的实施方式的计算系统的框图。
参照图7，计算系统700可包括电连接到系统总线760的CPU 720、随机存取存储器(RAM)730、用户接口740、调制解调器750和存储器系统710。当计算系统700是移动装置时，还可包括用于向计算系统700供应操作电压的电池，并且还可包括应用芯片组、图像处理器、移动DRAM等。
存储器系统710可包括存储控制器711和存储器装置712。存储器装置712可与参照图6描述的层叠型存储器装置620相同地配置。存储控制器711可与参照图6描述的存储控制器610相同地配置。
图8是示出根据本公开的实施方式的CMOS图像传感器(CIS)800的示图。
参照图8，CIS 800可包括逻辑芯片810和层叠在逻辑芯片810上的像素芯片820。
逻辑芯片810可包括用于处理来自像素芯片820的像素信号的逻辑电路。逻辑电路可包括行驱动器、相关双采样器(CDS)、模数转换器(ADC)、定时控制器等。
像素芯片820可包括像素阵列。像素阵列可通过转换入射光来生成电像素信号。像素阵列可包括以矩阵形式布置的多个单位像素。像素阵列可由从逻辑芯片810提供的驱动信号驱动。
逻辑芯片810和像素芯片820可通过彼此结合的贯通电极而被穿透，并且通过贯通电极彼此电连接。穿透逻辑芯片810和像素芯片820的贯通电极可与参照图2描述的第一贯通电极TE2和第二贯通电极TE3相同地配置。
图9A、图9B、图9C、图9D、图9E、图9F、图9G、图9H、图9I、图9J、图10A和图10B是示出根据本公开的实施方式的层叠型半导体装置的制造方法的截面图。图9A、图9B、图9C、图9D、图9E、图9F、图9G、图9H、图9I、图9J、图10A和图10B是沿着层叠型半导体装置的通孔区域截取的截面图。
图9A至图9J是示出半导体芯片的制造方法的实施方式的截面图。
参照图9A，可在具有第一表面910S1和与第一表面910S1相对的第二表面910S2的初步基板910A的第一表面910S1上形成第一绝缘结构920。尽管图中未示出，用于半导体芯片的存储器单元阵列、像素阵列、外围电路和逻辑电路中的至少一个的元件和线可形成在初步基板910A的主区域(未示出)中。
初步基板910A可以是由硅、锗、砷化镓等制成的半导体基板。用于阱结构、沟道区域等的各种杂质可被掺杂在初步基板910A中。
第一绝缘结构920可延伸以覆盖初步基板910A的主区域(未示出)。第一绝缘结构920可包括层叠在初步基板910A上的两个或更多个绝缘层。
随后，可在第一绝缘结构920上形成导电焊盘930。随后，可在第一绝缘结构920上形成第二绝缘结构940。第二绝缘结构940可形成为覆盖导电焊盘930。
随后，可在第二绝缘结构940上形成掩模图案941。掩模图案941可使用光刻工艺来构图以具有与导电焊盘930交叠的开口。
可通过使用上述掩模图案941作为蚀刻屏障通过蚀刻工艺依次蚀刻第二绝缘结构940、导电焊盘930和第一绝缘结构920来形成通路孔943。可形成通路孔943以暴露初步基板910A。通路孔943可形成至通路孔943不穿透初步基板910A的深度。在实施方式中，通路孔943可形成至与包括第二绝缘结构940、导电焊盘930和第一绝缘结构920的层叠结构的厚度对应的深度。通路孔943的宽度可形成为比导电焊盘930的宽度窄。
参照图9B，在形成通路孔943之后，可去除图9A所示的掩模图案941。随后，可在通路孔943的侧壁上形成保护层945。保护层945可由相对于初步基板910A具有蚀刻选择性的材料形成。在实施方式中，保护层945可包括氧化物。保护层945可被蚀刻，使得初步基板910A可通过通路孔943的底表面暴露。
参照图9C，可通过经由通路孔943蚀刻初步基板910A来形成缓冲孔947。在初步基板910A被蚀刻的同时，第一绝缘结构920、导电焊盘930和第二绝缘结构940可由图9B所示的保护层945保护。在形成缓冲孔947之后可去除保护层945。
用于形成缓冲孔947的蚀刻工艺可通过各向同性蚀刻工艺来执行。因此，在初步基板910A和第一绝缘结构920层叠的方向上，缓冲孔947的侧壁可具有大于通路孔943的侧壁的曲率。在实施方式中，缓冲孔947可形成为圆形形状或椭圆形形状。
缓冲孔947可从通路孔943延伸到初步基板910A的内部。缓冲孔947的底表面可与初步基板910A的第二表面910S2间隔开。换言之，缓冲孔947可形成至缓冲孔947不完全穿透初步基板910A的深度。
参照图9D，可在缓冲孔947和通路孔943中的每一个的表面上形成绝缘层951L。绝缘层951L可延伸到限定通路孔943的侧壁、导电焊盘930的侧壁和第二绝缘结构940的侧壁的第一绝缘结构920的侧壁上，并且延伸到第二绝缘结构940的顶表面上。绝缘层951L可包括氧化物层。
参照图9E，可在绝缘层951L上形成牺牲材料952。可使用旋涂工艺形成牺牲材料952以填充图9D所示的缓冲孔947和通路孔943。随后，可通过去除牺牲材料952的一部分来使图9D所示的通路孔943的上端敞开。以下，通路孔943的当牺牲材料952的一部分被去除时敞开的上端被定义为开口OP。
用于形成开口OP的牺牲材料952的蚀刻工艺可包括诸如回蚀工艺的蚀刻工艺。牺牲材料952可由相对于第二绝缘结构940和导电焊盘930具有蚀刻选择性的材料形成。在实施方式中，牺牲材料952可包括碳、光致抗蚀剂或有机化合物。
开口OP可延伸至设置导电焊盘930的侧壁的水平。在实施方式中，限定开口OP的底表面的牺牲材料952的顶表面可对应于设置绝缘结构920的顶表面的水平。
参照图9F，通过蚀刻图9E所示的绝缘层951L的暴露部分来形成侧壁绝缘层951。侧壁绝缘层951可保持在侧壁绝缘层951从缓冲孔947的表面延伸到第一绝缘结构920的侧壁上的状态。
参照图9G，可通过选择性地去除图9F所示的牺牲材料952来暴露侧壁绝缘层951。随后，可在侧壁绝缘层951上依次形成屏障层953L和金属层955L。
屏障层953L可从侧壁绝缘层951延伸到导电焊盘930的侧壁上。屏障层953L可连接到侧壁绝缘层951上暴露的导电焊盘930。屏障层953L可形成为包括钛、氮化钛、钽、氮化钽、氮化钨、镍、硼化镍等的单层，或者形成为包括钛和氮化钛的双层。
可通过诸如电镀的沉积工艺形成金属层955L。在实施方式中，金属层955L可包括铜。金属层955L可形成在屏障层953L上以填充缓冲孔947和通路孔943。气隙959可掩埋在形成到比通路孔943的深度更深的深度的缓冲孔947中。当缓冲孔947的宽度形成为比通路孔943的宽度宽时，可在缓冲孔947中容易地掩埋空隙959。金属层955L可完全填充通路孔943，使得空隙959可被密封在缓冲孔947中。
参照图9H，可通过平坦化工艺去除图9G所示的金属层955L和屏障层953L中的每一个的一部分，使得第二绝缘结构940的顶表面暴露。
参照图9I，可从图9H所示的初步基板910A的第二表面910S2去除初步基板910A的一部分，使得侧壁绝缘层951的端部暴露。因此，初步基板910A的厚度可减小。以下，具有减小的厚度的初步基板被定义为结合基板910B。侧壁绝缘层951的端部可在该端部比结合基板910B突出更远的状态下暴露。
参照图9J，可去除图9I所示的侧壁绝缘层951的暴露部分。因此，可形成用作目标的侧壁绝缘图案951P。
随后，可通过去除屏障层的一部分以使得金属层955暴露来形成屏障图案953P。屏障图案953P和金属层955可构成贯通电极957。金属层955的暴露部分可构成比结合基板910B突出更远的突出部PP。
通过参照图9A至图9J描述的工艺形成的贯通电极957可包括填充结合基板910B中的缓冲孔947的缓冲部P1以及从缓冲部P1延伸的垂直部P2。垂直部P2可形成在侧壁绝缘图案951P上以填充穿透第一绝缘结构920、导电图案930和第二绝缘结构940的通路孔943并与导电焊盘930接触。
图10A和图10B是示出将第一半导体芯片970和第二半导体芯片980结合的工艺的截面图。第一半导体芯片970和第二半导体芯片980之间的结合工艺可通过晶圆之间的结合工艺来执行，通过管芯之间的结合工艺来执行，或者通过晶圆与管芯之间的结合工艺来执行。
参照图10A，可分别由通过参照图9A至图9J描述的工艺制造的第一贯通电极957a和第二贯通电极957b穿透第一半导体芯片970和第二半导体芯片989。第一空隙959a可掩埋在第一贯通电极957a中，第二空隙959b可掩埋在第二贯通电极957b中。
根据参照图9A至图9J描述的工艺，第一贯通电极957a可包括第一缓冲部P1a以及从第一缓冲部P1a延伸的第一垂直部P2a。第一缓冲部P1a可设置在穿透第一半导体芯片970的第一结合基板910Ba的第一缓冲孔947a中，并且围绕第一空隙959a。第一垂直部P2a可延伸以穿透第一半导体芯片970的第一绝缘结构920a、第一导电焊盘930a和第二绝缘结构940a。第一缓冲部P1a的面向第一结合基板910Ba的侧壁和第一垂直部P2a的面向第一绝缘结构920a的侧壁可由第一侧壁绝缘图案951Pa围绕。第一垂直部P2a可比第一侧壁绝缘图案951Pa突出更远，并且与第一半导体芯片970的第一导电焊盘930a接触。
根据参照图9A至图9J描述的工艺，第二贯通电极957b可包括第二缓冲部P1b以及从第二缓冲部P1b延伸的第二垂直部P2b。第二缓冲部P1b可设置在穿透第二半导体芯片980的第二结合基板910Bb的第二缓冲孔947b中，并且围绕第二气隙959b。第二垂直部P2b可延伸以穿透第二半导体芯片980的第一绝缘结构920b、第二导电焊盘930b和第二绝缘结构940b。第二缓冲部P1b的面向第二结合基板910Bb的侧壁和第二垂直部P2b的面向第一绝缘结构920b的侧壁可由第二侧壁绝缘图案951Pb围绕。第二垂直部P2b可比第二侧壁绝缘图案951Pb突出更远，并且与第二半导体芯片980的第二导电焊盘930b接触。
第一缓冲部P1a可比第一结合基板910Ba突出更远，并且第二缓冲部P1b可比第二结合基板910Bb突出更远。
第一半导体芯片970可在第二半导体芯片980上对齐，使得第一垂直部P2a和第二缓冲部P1b面向彼此。
参照图10B，第一半导体芯片970的第一贯通电极957a可结合到第二半导体芯片980的第二贯通电极957b。第一贯通电极957a和第二贯通电极957b可通过将第一垂直部P2a结合到第二缓冲部P1b来彼此结合。
结合工艺可包括等离子体退火工艺。可在300℃或更低的低温下执行等离子体退火工艺。在等离子体退火工艺期间，第一贯通电极957a和第二贯通电极957b可通过第一贯通电极957a和第二贯通电极957b的金属层之间的相干性来彼此结合。
第一贯通电极957a和第二贯通电极957b中的每一个的金属层可能由于在上述结合工艺期间产生的热而热膨胀，并且在第一贯通电极957a和第二贯通电极957b之间可能出现排斥力。通过第一贯通电极957a与第二贯通电极957b之间产生的排斥力以及第一贯通电极957a和第二贯通电极957b的金属层之间的相干性，第二贯通电极957b的突出部可向图10A所示的第二空隙959b的内部凹陷。因此，图10A所示的第二空隙959b的形状可能在如图10B所示的结合工艺中变形，并且作为具有比第一空隙959a大的曲率偏差的凹陷空隙959b’保留。在实施方式中，凹陷空隙959b’可具有凹部和凸部。
如上所述，根据本公开的实施方式，在结合工艺期间在结合界面处的金属层之间产生的排斥力可被空隙的缓冲作用抵消。因此，半导体芯片之间的结合结构的稳定性可改进。
尽管上面举例说明了第一半导体芯片970和第二半导体芯片980彼此结合的结构，但是本公开中彼此结合的半导体芯片的数量不限于此。
根据本公开，在结合工艺期间由于贯通电极的热膨胀而引起的贯通电极之间的排斥力可通过形成在贯通电极中的空隙来抵消。因此，结合结构的稳定性可改进。
相关申请的交叉引用
本申请要求2020年3月12日提交于韩国知识产权局的韩国专利申请号10-2020-0030963的优先权，其完整公开通过引用并入本文。

Claims (22)

1.一种层叠型半导体装置，该层叠型半导体装置包括：
多个半导体芯片，多个所述半导体芯片层叠以彼此交叠；
多个贯通电极，多个所述贯通电极分别穿透所述半导体芯片，其中，多个所述贯通电极彼此结合；以及
多个空隙，多个所述空隙分别掩埋在所述贯通电极中。
2.根据权利要求1所述的层叠型半导体装置，其中，各个所述半导体芯片包括：
基板，该基板具有第一表面以及与所述第一表面相对的第二表面；
第一绝缘结构，该第一绝缘结构在所述基板的所述第一表面上；
导电焊盘，该导电焊盘面向所述基板的所述第一表面，并且所述第一绝缘结构插置在所述导电焊盘与所述基板的所述第一表面之间；以及
第二绝缘结构，该第二绝缘结构覆盖所述第一绝缘结构的设置有所述导电焊盘的表面。
3.根据权利要求2所述的层叠型半导体装置，其中，各个所述贯通电极包括：
接触表面，该接触表面与所述导电焊盘接触；
第一结合表面，该第一结合表面与所述基板的所述第二表面相邻；以及
第二结合表面，该第二结合表面与所述第二绝缘结构的表面相邻。
4.根据权利要求2所述的层叠型半导体装置，其中，各个所述贯通电极包括：
缓冲部，该缓冲部设置在缓冲孔中，该缓冲孔从所述基板的所述第一表面朝着所述第二表面延伸以穿透所述基板；以及
垂直部，该垂直部填充通路孔，该通路孔从所述缓冲孔延伸以穿透所述第一绝缘结构、所述导电焊盘和所述第二绝缘结构。
5.根据权利要求4所述的层叠型半导体装置，该层叠型半导体装置还包括在所述第一绝缘结构和所述垂直部之间以及在所述缓冲部和所述基板之间延伸的侧壁绝缘图案，
其中，所述垂直部比所述侧壁绝缘图案突出更远以与所述导电焊盘和所述第二绝缘结构接触。
6.根据权利要求4所述的层叠型半导体装置，其中，各个所述空隙被掩埋在所述缓冲孔中，并且由所述缓冲部围绕。
7.根据权利要求4所述的层叠型半导体装置，其中，所述贯通电极通过上贯通电极的所述垂直部和下贯通电极的所述缓冲部彼此结合的结构来彼此电连接。
8.根据权利要求4所述的层叠型半导体装置，其中，所述缓冲孔具有在多个所述贯通电极层叠的层叠方向上延伸的弯曲侧壁，并且
其中，所述通路孔具有在所述层叠方向上延伸的平坦侧壁。
9.根据权利要求4所述的层叠型半导体装置，其中，所述缓冲孔具有比所述通路孔的宽度更宽的宽度。
10.根据权利要求1所述的层叠型半导体装置，其中，所述贯通电极包括：
多个金属层，多个所述金属层分别围绕所述空隙，其中，多个所述金属层彼此结合；以及
多个屏障层，多个所述屏障层分别形成在所述金属层的侧壁上。
11.根据权利要求1所述的层叠型半导体装置，其中，多个所述空隙中的至少一个变形。
12.根据权利要求1所述的层叠型半导体装置，其中，多个所述空隙中的至少一个是凹陷空隙。
13.一种制造层叠型半导体装置的方法，该方法包括以下步骤：
形成由掩埋有第一空隙的第一贯通电极穿透的第一半导体芯片；
形成由掩埋有第二空隙的第二贯通电极穿透的第二半导体芯片；
使所述第一半导体芯片在所述第二半导体芯片上对齐；以及
将所述第一贯通电极结合到所述第二贯通电极。
14.根据权利要求13所述的方法，其中，所述第一贯通电极与所述第二贯通电极的结合包括等离子体退火工艺。
15.根据权利要求13所述的方法，其中，在所述第一贯通电极被结合到所述第二贯通电极时，所述第二空隙的形状变形。
16.根据权利要求13所述的方法，其中，形成所述第一半导体芯片的步骤和形成所述第二半导体芯片的步骤中的每一个包括以下步骤：
在具有第一表面以及与所述第一表面相对的第二表面的基板的所述第一表面上形成第一绝缘结构；
在所述第一绝缘结构上形成导电焊盘；
在所述第一绝缘结构上形成第二绝缘结构以覆盖所述导电焊盘；
形成穿透所述第二绝缘结构、所述导电焊盘和所述第一绝缘结构的通路孔以暴露所述基板；
形成从所述通路孔延伸到所述基板的内部的缓冲孔；
从所述缓冲孔的表面向所述第一绝缘结构的侧壁上形成侧壁绝缘层；
在所述侧壁绝缘层上形成连接到所述导电焊盘的屏障层；
在所述屏障层上形成金属层以填充所述缓冲孔和所述通路孔；
将所述屏障层和所述金属层平坦化以暴露所述第二绝缘结构；
从所述基板的所述第二表面去除所述基板的一部分以减小所述基板的厚度并暴露所述侧壁绝缘层的端部；以及
去除所述侧壁绝缘层的所述端部和所述屏障层的一部分以暴露所述金属层。
17.根据权利要求16所述的方法，其中，所述金属层具有比具有减小的厚度的所述基板突出更远的突出部。
18.根据权利要求16所述的方法，其中，所述第一空隙和所述第二空隙中的每一个被掩埋在所述缓冲孔中。
19.根据权利要求16所述的方法，其中，所述第一贯通电极和所述第二贯通电极中的每一个包括缓冲部和垂直部，所述缓冲部填充所述缓冲孔，所述垂直部填充所述通路孔并且与所述导电焊盘接触，
其中，所述第一贯通电极与所述第二贯通电极的结合是通过将所述第一贯通电极的所述垂直部结合到所述第二贯通电极的所述缓冲部来执行的。
20.根据权利要求13所述的方法，其中，所述第一贯通电极包括第一缓冲部和第一垂直部，所述第一缓冲部穿透所述第一半导体芯片的第一基板并且围绕所述第一空隙，所述第一垂直部从所述第一缓冲部延伸并且连接到所述第一半导体芯片的第一导电焊盘，
其中，所述第二贯通电极包括第二缓冲部和第二垂直部，所述第二缓冲部穿透所述第二半导体芯片的第二基板并且围绕所述第二空隙，所述第二垂直部从所述第二缓冲部延伸并且连接到所述第二半导体芯片的第二导电焊盘。
21.根据权利要求20所述的方法，其中，所述第一缓冲部形成为比所述第一基板突出更远，并且
所述第二缓冲部形成为比所述第二基板突出更远。
22.根据权利要求21所述的方法，其中，在所述第一贯通电极被结合到所述第二贯通电极时，所述第二缓冲部的突出部朝着所述第二空隙的内部凹陷。
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KR20210147363A (ko) * 2020-05-28 2021-12-07 에스케이하이닉스 주식회사 반도체 장치 및 그 제조방법
KR102599631B1 (ko) 2020-06-08 2023-11-06 삼성전자주식회사 반도체 칩, 반도체 장치, 및 이를 포함하는 반도체 패키지
JP2023554312A (ja) 2021-08-31 2023-12-27 エルジー エナジー ソリューション リミテッド 電極走行ローラー及びこれを含むノッチング装置

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3879816B2 (ja) * 2000-06-02 2007-02-14 セイコーエプソン株式会社 半導体装置及びその製造方法、積層型半導体装置、回路基板並びに電子機器
KR100881199B1 (ko) * 2007-07-02 2009-02-05 삼성전자주식회사 관통전극을 구비하는 반도체 장치 및 이를 제조하는 방법
KR101052870B1 (ko) * 2008-04-21 2011-07-29 주식회사 하이닉스반도체 관통 전극, 이를 갖는 회로 기판, 이를 갖는 반도체 패키지및 반도체 패키지를 갖는 적층 반도체 패키지
JP5212118B2 (ja) * 2009-01-05 2013-06-19 日立金属株式会社 半導体装置およびその製造方法
US20110058348A1 (en) * 2009-09-10 2011-03-10 Ibiden Co., Ltd. Semiconductor device
US8709948B2 (en) * 2010-03-12 2014-04-29 Novellus Systems, Inc. Tungsten barrier and seed for copper filled TSV
KR20120012602A (ko) * 2010-08-02 2012-02-10 삼성전자주식회사 반도체 장치, 그 제조 방법 및 반도체 패키지의 제조 방법
KR101801137B1 (ko) * 2011-02-21 2017-11-24 삼성전자주식회사 반도체 장치 및 그 제조 방법
JP2012231096A (ja) * 2011-04-27 2012-11-22 Elpida Memory Inc 半導体装置及びその製造方法
KR20120133057A (ko) * 2011-05-30 2012-12-10 삼성전자주식회사 반도체 패키지 및 그 제조방법
US20130313687A1 (en) * 2012-01-13 2013-11-28 Zycube Co., Ltd. Through via/the buried via elrctrolde material and the said via structure and the said via manufacturing method
US8703508B2 (en) * 2012-08-14 2014-04-22 Powertech Technology Inc. Method for wafer-level testing diced multi-chip stacked packages
US9281242B2 (en) * 2012-10-25 2016-03-08 Nanya Technology Corp. Through silicon via stacked structure and a method of manufacturing the same
US20140175614A1 (en) * 2012-12-20 2014-06-26 Industrial Technology Research Institute Wafer stacking structure and method of manufacturing the same
US9443796B2 (en) 2013-03-15 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. Air trench in packages incorporating hybrid bonding
KR101936405B1 (ko) * 2013-06-11 2019-04-03 에스케이하이닉스 주식회사 적층 반도체 패키지 및 이의 제조방법
JP6073757B2 (ja) * 2013-08-07 2017-02-01 ルネサスエレクトロニクス株式会社 半導体装置
EP2908337A1 (en) * 2014-02-12 2015-08-19 ams AG Semiconductor device with a thermally stable bump contact on a TSV and method of producing such a semiconductor device
JP6113679B2 (ja) * 2014-03-14 2017-04-12 株式会社東芝 半導体装置
JP6509635B2 (ja) * 2015-05-29 2019-05-08 東芝メモリ株式会社 半導体装置、及び、半導体装置の製造方法
JP6489965B2 (ja) * 2015-07-14 2019-03-27 新光電気工業株式会社 電子部品装置及びその製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115966512A (zh) * 2022-12-14 2023-04-14 湖北江城芯片中试服务有限公司 半导体结构及其制作方法以及封装系统

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