CN113314523A - 半导体器件和制造半导体器件的方法 - Google Patents

半导体器件和制造半导体器件的方法 Download PDF

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CN113314523A
CN113314523A CN202011412478.7A CN202011412478A CN113314523A CN 113314523 A CN113314523 A CN 113314523A CN 202011412478 A CN202011412478 A CN 202011412478A CN 113314523 A CN113314523 A CN 113314523A
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CN113314523B (zh
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朱龙琨
黄懋霖
徐崇威
余佳霓
江国诚
王志豪
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本申请的实施例提供了具有第一全环栅(GAA)晶体管、第二GAA晶体管和第三GAA晶体管的半导体。第一(GAA)晶体管包括多个第一沟道构件、位于多个第一沟道构件上方的栅极介电层、位于栅极介电层上方的第一功函数层以及位于第一功函数层上方的胶层。第二GAA晶体管包括多个第二沟道构件、位于多个第二沟道构件上方的界面层、位于界面层上方的栅极介电层、位于栅极介电层上方并与栅极介电层接触的第二功函数层、位于第二功函数层上方并与第二功函数层接触的第一功函数层以及位于第一功函数层上方的胶层。第三GAA晶体管包括多个第三沟道构件、位于多个第三沟道构件上方的栅极介电层以及位于栅极介电层上方的胶层。根据本申请的其他实施例，还提供了制造半导体器件的方法。

Description

半导体器件和制造半导体器件的方法
技术领域
本申请的实施例涉及半导体器件和制造半导体器件的方法。
背景技术
半导体集成电路(IC)工业经历了快速增长。IC材料和设计的技术进步产生了多代IC，其中，每一代都具有比先前一代更小且更复杂的电路。在IC发展过程中，功能密度(即每芯片面积上互连器件的数量)通常增大了而几何尺寸(即，使用制造工艺可以做出的最小的元件(或线))减小了。这种规模缩小工艺通常通过增加产量效率和降低相关成本来提供很多益处。这种按比例缩小工艺也增大了加工和制造IC的复杂度。
例如，随着集成电路(IC)技术朝着更小的技术节点发展，已经引入了多栅极器件，以通过增加栅极-沟道耦合、减小截止状态电流和减小短沟道效应(SCE)来改善栅极控制。多栅极器件通常是指具有栅极结构或其一部分设置在沟道区域的多于一侧上方的器件。鳍式场效应晶体管(FinFET)和全环栅(GAA)晶体管(两者也称为非平面晶体管)是多栅极器件的示例，这些器件已成为高性能和低泄漏应用的流行和有希望的候选者。FinFET的升高的沟道在多于一侧上被栅极围绕(例如，栅极围绕从衬底延伸的半导体材料“鳍”的顶部和侧壁)。与平面晶体管相比，这种配置提供了对沟道的更好控制，并大大降低了SCE(特别是通过减少亚阈值泄漏(即，处于“截止”状态的FinFET的源极和漏极之间的耦合))。GAA晶体管的栅极结构可以部分或全部围绕沟道区域延伸，以提供对两侧或更多侧沟道区域的访问。GAA晶体管的沟道区域可以由纳米线、纳米片、其他纳米结构和/或其他合适的结构形成。在一些实施方案中，这种沟道区域包括竖直堆叠的多个纳米线(其水平延伸，从而提供水平取向的沟道)。这种GAA晶体管可以被称为竖直堆叠的水平GAA(VGAA)晶体管。
当期望具有不同阈值电压的GAA晶体管时，一个或多个层可以毯式沉积在所有沟道区域上方，并且从一部分沟道区中选择性地去除。有时，去除沉积在沟道区域中的纳米结构之间的材料可能具有挑战性。不清除或不完全清除这种材料可能会导致器件故障或性能下降。因此，尽管现有的GAA晶体管和其形成工艺通常足以满足其预期目的，但是它们没有在每个方面都完全令人满意。
发明内容
根据本申请的一个实施例，提供了一种半导体器件，包括：第一全环栅(GAA)晶体管，包括：多个第一沟道构件，位于多个第一沟道构件上方的界面层，位于界面层上方的栅极介电层，位于栅极介电层上方并与栅极介电层接触的第一功函数层，和位于第一功函数层上方的胶层；第二GAA晶体管，包括：多个第二沟道构件，位于多个第二沟道构件上方的界面层，位于界面层上方的栅极介电层，位于栅极介电层上方并与栅极介电层接触的第二功函数层，位于第二功函数层上方并与第二功函数层接触的第一功函数层，和位于第一功函数层上方的胶层；以及第三GAA晶体管，包括：多个第三沟道构件，位于多个第三沟道构件上方的界面层，位于界面层上方的栅极介电层，和位于栅极介电层上方的胶层。
根据本申请的另一个实施例，提供了一种制造半导体器件的方法，包括：提供工件，工件包括衬底、位于衬底的第一区域中的第一竖直堆叠沟道构件、位于衬底的第二区域中的第二竖直堆叠沟道构件和位于衬底的第三区域中的第三竖直堆叠沟道构件；在第一竖直堆叠沟道构件、第二竖直堆叠沟道构件和第三竖直堆叠沟道构件上方沉积栅极介电层；在栅极介电层上方沉积牺牲层；蚀刻牺牲层使得牺牲层的一部分保持设置在第一竖直堆叠沟道构件、第二竖直堆叠沟道构件和第三竖直堆叠沟道构件中的相邻沟道构件之间；选择性地去除第二区域中的所有牺牲层；在第一竖直堆叠沟道构件、第二竖直堆叠沟道构件和第三竖直堆叠沟道构件上方沉积第一功函数层；选择性地去除第一区域中的第一功函数层和牺牲层；在第一竖直堆叠沟道构件、第二竖直堆叠沟道构件和第三竖直堆叠沟道构件上方沉积第二功函数层，第二功函数层不同于第一功函数层；以及在第二功函数层上方沉积钝化层。
根据本申请的又一个实施例，提供了一种制造半导体器件的方法，包括：提供工件，工件包括衬底、位于衬底的第一区域中的第一竖直堆叠沟道构件、位于衬底的第二区域中的第二竖直堆叠沟道构件和位于衬底的第三区域中的第三竖直堆叠沟道构件；在第一竖直堆叠沟道构件、第二竖直堆叠沟道构件和第三竖直堆叠沟道构件上方沉积栅极介电层；在栅极介电层上方沉积牺牲层；部分地和选择性地蚀刻牺牲层使得牺牲层的一部分设置在第一竖直堆叠沟道构件、第二竖直堆叠沟道构件和第三竖直堆叠沟道构件中的相邻沟道构件之间；选择性地去除第二区域中的所有牺牲层；在第一竖直堆叠沟道构件、第二竖直堆叠沟道构件和第三竖直堆叠沟道构件上方沉积第一功函数层；选择性地去除第一区域中的第一功函数层和牺牲层；在第一竖直堆叠沟道构件、第二竖直堆叠沟道构件和第三竖直堆叠沟道构件上方沉积第二功函数层，第二功函数层不同于第一功函数层；在第二功函数层上方沉积钝化层；选择性地去除第三区域中的钝化层、第一功函数层、第二功函数层和牺牲层；选择性地去除第三区域中的钝化层、第一功函数层、第二功函数层和牺牲层；在第一竖直堆叠沟道构件、第二竖直堆叠沟道构件和第三竖直堆叠沟道构件上方沉积胶层；以及在胶层上方沉积金属填充层，其中，第一功函数层不同于第二功函数层，其中，第一功函数层的组成与胶层的组成基本相同。
本申请的实施例提供了阈值电压不同的晶体管。
附图说明
当结合附图进行阅读时，根据下面详细的描述可以最佳地理解本发明的各个方面。应该强调，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。还应强调的是，所附附图仅示出了本发明的典型实施例，因此不应视为对本发明范围的限制，因为本发明可以同样很好地应用于其他实施例。
图1是示出根据本公开的实施例的形成半导体器件的方法的流程图。
图2A是根据本公开的各个方面的工件的第一区域的示意性立体图。
图2B是根据本公开的各个方面的工件的第二区域的示意性立体图。
图2C是根据本公开的各个方面的工件的第三区域的示意性立体图。
图3-图23示出根据图1中的方法在制造的各个阶段中的工件的第一区域、第二区域和第三区域的局部截面图。
具体实施方式
以下公开内容提供了许多不同的实施例或实例，以用于实现所提供主题的不同特征。在下面描述元件和布置的特定实例以简化本发明。当然这些仅是实例并不旨在限定。例如，在以下描述中，在第二部件上方或上形成第一部件可以包括第一部件和第二部件直接接触的实施例，也可以包括形成在第一部件和第二部件之间的附加部件使得第一部件和第二部件不直接接触的实施例。而且，本发明在各个实例中可以重复参考数字和/或字母。这种重复仅是为了简明和清楚，其自身并不表示所论述的各个实施例和/或配置之间的关系。
此外，为了便于描述，本文中可以使用诸如“在…下方”、“在…下面”、“下部”、“在…上面”、“上部”等的空间关系术语，以描述如图中所示的一个元件或部件与另一元件或部件的关系。空间关系术语旨在包括除了在图中所描述的方向之外的使用或操作中的器件的不同方向。装置可以以其他方式定位(旋转90度或在其他方位)，并且在本文中使用的空间关系描述符可以同样地作相应地解释。
更进一步，当用“约”、“近似”等描述数值或数值的范围时，该词语旨在涵盖在包括所描述的数值的合理范围内的数值，诸如本领域技术人员所理解的所描述的数值的+/-10％或其他值。例如，词语“约5nm”涵盖从4.5nm至5.5nm的尺寸范围。
本公开涉及GAA晶体管，更具体地，涉及半导体器件中具有不同阈值电压的GAA晶体管。根据本公开的实施例的半导体器件包括位于第一区域中的第一类型GAA晶体管、位于第二区域中的第二类型GAA晶体管和位于第三区域中的第三类型GAA晶体管。第一类型GAA晶体管包括第一竖直堆叠的沟道构件，第二类型GAA晶体管包括第二竖直堆叠的沟道构件，并且第三类型GAA晶体管包括第三竖直堆叠的沟道构件。第一类型GAA晶体管包括位于第一竖直堆叠的沟道构件上方的界面层、位于界面层上方的栅极介电层、位于栅极介电层上方的n型功函数层、位于n型功函数层上方的钝化层、位于钝化层上方的胶层以及位于胶层上方的金属填充层。第二类型GAA晶体管包括位于第二竖直堆叠的沟道构件上方的界面层、位于界面层上方的栅极介电层、位于栅极介电层上方的p型功函数层、位于p型功函数层上方的n型功函数层、位于n型功函数层上方的钝化层、位于钝化层上方的胶层以及位于胶层上方的金属填充层。第三类型GAA晶体管包括位于第三竖直堆叠的沟道构件上方的界面层、位于界面层上方的栅极介电层、位于栅极介电层上方的胶层以及位于胶层上方的金属填充层。根据本公开的实施例，用于形成半导体器件的工艺包括在沟道构件之间形成牺牲层，以防止难以去除的功函数层沉积在沟道构件之间。通过在沟道构件之间设置很少或没有难以去除的功函数层，可以容易地去除沟道构件之间的材料，随后可以在沟道构件周围沉积沉积层。
图1示出根据本公开的各个方面的用于制造半导体器件的方法100的流程图。下面将结合图2A、图2B、图2C和图3-图23来描述图1，这些是在将半导体器件制造在工件上之前根据图1中的方法100的各个制造阶段的工件的局部截面图。贯穿本公开，为了便于参考，可以互换地指代工件和半导体器件，因为在其制造工艺结束时工件将成为半导体器件并且可以共用相同的附图标记。对于方法100的额外的实施例，可以在方法100之前、期间和之后提供额外的步骤，并且可以移动、替换或消除所描述的步骤中的一些。可以在图2A、图2B、图2C和图3-图23所示的半导体器件中添加附加部件，并且以下描述的一些部件可以在半导体器件的其他实施例中被替换、修改或消除。
现在参考图1、图2A、图2B和图2C，方法100包括框102，其中，在工件200的衬底202上的第一区域1000、第二区域2000和第三区域3000上方形成多个交替的半导体层204。图2A示出工件200的第一区域1000，图2B示出工件200的第二区域2000，图2C示出工件200的第三区域3000。在一些实施例中，衬底202包括硅。替代地或附加地，衬底202包括：另一元素半导体，诸如锗；化合物半导体，诸如碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟；合金半导体，诸如硅锗(SiGe)、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP；或它们的组合。在一些实施方式中，衬底202包括一种或多种III-V族材料、一种或多种II-IV族材料或其组合。在一些实施方式中，衬底202是绝缘体上半导体衬底，诸如绝缘体上硅(SOI)衬底、绝缘体上硅锗(SGOI)衬底或绝缘体上锗(GOI)衬底。可以通过注氧隔离(SIMOX)、晶圆接合和/或其他适当方法制造绝缘体上半导体衬底。衬底202可以包括根据半导体器件200的设计要求配置的各种掺杂区域。P型掺杂区域可以包括p型掺杂剂，诸如硼、铟、其他p型掺杂剂或其组合。N型掺杂区域可以包括n型掺杂剂，诸如磷、砷、其他n型掺杂剂或其组合。在一些实施方式中，衬底202包括由p型掺杂剂和n型掺杂剂的组合形成的掺杂区域。各种掺杂区域可以直接形成在衬底202上和/或中，例如，提供p阱结构、n阱结构、双阱结构、凸起结构或其组合。可以执行离子注入工艺、扩散工艺和/或其他合适的掺杂工艺以形成各种掺杂区域。在一些实施例中，在n型阱上方形成p型GAA器件，并且在p型阱上方形成n型GAA器件。
第一区域1000、第二区域2000和第三区域3000是用于具有不同阈值电压的晶体管的器件区域。在一些实施例中，第一区域1000可以是具有第一阈值电压的n型器件区域，第三区域3000可以是具有第三阈值电压的p型器件区域，第二区域2000可以是具有介于第一阈值电压和第三阈值电压之间的第二阈值电压的中级器件区域。第一阈值电压、第二阈值电压和第三阈值电压彼此不同。举例来说，第一阈值电压可以在约4.3eV和约4.5eV之间，第二阈值电压可以在约4.5eV和约4.7eV之间，并且第三阈值电压可以在约4.7eV和约4.9eV之间。取决于设计参数，第二区域2000中的中级器件可以用作n型器件或p型器件以减少泄漏电流。
在图2A、图2B和图2C所示的实施例中，多个交替的半导体层204包括被多个第二半导体层206交错的多个第一半导体层208。即，两个相邻的第一半导体层208中间夹着一个第二半导体层206。多个第一半导体层208由第一半导体材料形成，并且多个第二半导体层206由与第一半导体材料不同的第二半导体材料形成。在一些实施例中，第一半导体材料是硅(Si)或基本上由硅构成，并且第二半导体材料是硅锗(SiGe)或基本上由硅锗构成。在一些其他实施例中，第一半导体材料是硅或基本上由硅构成，并且第二半导体材料是锗(Ge)或基本上锗构成。在一些替代实施例中，第一半导体材料包括具有第一锗含量的硅锗(SiGe)，并且第二半导体材料包括具有比第一锗含量高的第二锗含量的硅锗(SiGe)。可以通过交替地沉积或外延生长多个第一半导体层208和多个第二半导体层206来形成多个交替的半导体层204。在一些实施方式中，在将多个交替的半导体层204图案化为鳍结构(鳍形有源区域)之后，可以选择性地去除沟道区域中的多个第二半导体层206的一部分，以释放由多个第一半导体层208形成的沟道构件。就这方面而言，第二半导体层206用作牺牲半导体层，并且可以这样命名。
仍参考图1、图2A、图2B和图2C，方法100包括框104，其中，在第一区域1000中形成第一鳍结构210A，在第二区域2000中形成第二鳍结构210B，在第三区域3000中形成第三鳍结构210C。如图2A所示，可以对多个交替的半导体层204进行图案化以在第一区域1000中形成第一鳍结构210A。如图2B所示，可以对多个交替的半导体层204进行图案化以在第二区域2000中形成第二鳍结构210B。如图2C所示，可以对多个交替的半导体层204进行图案化以在第三区域3000中形成第三鳍结构210C。在框104处，第一鳍结构210A、第二鳍结构210B和第三鳍结构210C可以通过使用诸如光刻和蚀刻工艺的适当工艺来图案化。在一些实施例中，使用干蚀刻或等离子蚀刻工艺从多个交替的半导体层204蚀刻鳍结构。在一些其他实施例中，可以通过双图案光刻(DPL)工艺、四图案光刻(QPL)工艺或多图案光刻(MPL)工艺来形成鳍结构。通常，DPL、QPL和MPL工艺将光刻和自对准工艺结合，从而允许创建图案，例如其间距小于使用单个直接光刻工艺所能获得的间距。在一些实施方式中，介电隔离部件212形成在第一鳍结构210A、第二鳍结构210B和第三鳍结构210C之间。介电隔离部件212也可以称为浅沟槽隔离(STI)部件212。
仍参考图1、图2A、图2B和图2C，方法100包括框106，其中，在第一鳍结构210A的第一沟道区域1100、第二鳍结构210B的第二沟道区域2100以及第三鳍结构210C的第三沟道区域3100上方形成伪栅极结构214。如图2A、图2B和图2C所示，伪栅极结构214可以包括伪栅极介电层216、伪栅电极218、栅极顶部硬掩模220和栅极间隔件221。在一些实施例中，伪栅电极218可以由多晶硅形成，并且伪栅极介电层216可以由氧化硅或氮氧化硅形成。栅极顶部硬掩模220可以由氧化硅或氮化硅形成。在一些实施方式中，栅极顶部硬掩模220可以包括多层。例如，栅顶部硬掩模220可以包括与伪栅电极218相邻的氧化硅层和位于氧化硅层上方的氮化硅层。栅极间隔件221沿伪栅电极218的侧壁延伸并限定第一沟道区域1100和第二沟道区域2100。在一些实施例中，栅极间隔件221可以由氧化硅、氮氧化硅、氮化硅、碳氮氧化硅、介电常数低于二氧化硅的介电常数(即，约3.9)的低k介电材料或其组合形成。
为了描述和说明的清楚起见，图3-图23中的每一个都包括沿图2A所示的截面I-I'的第一鳍结构210A的局部截面图、沿图2B所示的截面II-II'的第二鳍结构210B的局部截面图以及沿图2C所示的截面III-III'的第三鳍结构210C的局部截面图。如图2A所示，截面I-I'沿伪栅极结构214延伸并穿过第一沟道区域1100。如图2B所示，截面II-II'沿伪栅极结构214延伸并穿过第二沟道区域2100。如图2C所示，截面III-III'沿伪栅极结构214延伸并穿过第三沟道区域3100。
参考图1和图3-图5，方法100包括框108，其中，释放第一沟道区域1100中的第一沟道构件2081，释放第二沟道区域2100中的第二沟道构件2082，以及释放第三沟道区域3100中的第三沟道构件2083。在一些实施例中，在框106处形成伪栅极结构214之后，伪栅极结构214用作蚀刻掩模以开槽第一鳍结构210A、第二鳍结构210B和第三鳍结构210C，以形成源极/漏极沟槽来暴露第一沟道区域1100、第二沟道区域2100和第三沟道区域3100中的多个第一半导体层208和多个第二半导体层206的侧壁。在一些实施例中，可以选择性地且部分地蚀刻第一沟道区域1100、第二沟道区域2100和第三沟道区域3100中的多个第二半导体层206，以在多个第一半导体层208中的两个之间形成内部间隔件凹槽。然后，在内部间隔件凹槽内形成内部间隔件部件。然后，可以在源极/漏极沟槽中形成外延源极/漏极部件。在形成外延源极/漏极部件之后，可以在工件200上方沉积层间介电(ILD)层。可以执行诸如化学机械抛光(CMP)工艺的平坦化工艺以平坦化工件200，直到暴露伪栅电极218。然后可以使用适当的干蚀刻或湿蚀刻工艺来选择性地去除暴露的伪栅电极218。图3示出在去除伪栅电极218之后的第一沟道区域1100、第二沟道区域2100和第三沟道区域3100中的多个交替的半导体层204。在一些实施例中，可以使用与用于去除伪栅电极218的蚀刻工艺不同的适当蚀刻工艺来去除伪栅极介电层216。图4示出在去除伪栅极介电层216之后的第一沟道区域1100、第二沟道区域2100和第三沟道区域3100中的多个交替的半导体层204。在去除伪栅极介电层216之后，可以选择性地去除多个第二半导体层206。在一些实施方式中，多个第二半导体层206由硅锗形成，并且选择性去除工艺包括使用诸如臭氧的适当氧化剂来氧化多个第二半导体层206。之后，可以选择性地去除被氧化的第二半导体层206。此时，如图5所示，第一沟道构件2081形成在第一区域1000中，第二沟道构件2082形成在第二区域2000中，并且第三沟道构件2083形成在第三区域3000中。
参考图1和图6，方法100包括框110，其中，在第一区域1000中的第一沟道构件2081、第二区域2000中的第二沟道构件2082和第三区域3000中的第三沟道构件2083上方形成界面层222。在一些实施例中，界面层222可以包括氧化硅或氮氧化硅或其他合适的材料。在一些实施例中，可以使用合适的方法来沉积界面层222，诸如原子层沉积(ALD)、化学气相沉积(CVD)、臭氧氧化、热氧化或其他合适的方法。界面层222起到控制和减少栅极泄漏电流并改善栅极介电层228(如图7所示)与沟道构件(包括第一沟道构件2081、第二沟道构件2082和第三沟道构件2083)之间的界面粘附的作用。
参考图1和图7，方法100包括框112，其中，在第一区域1000、第二区域2000和第三区域3000中的界面层222上方沉积栅极介电层228。在一些实施例中，栅极介电层228是高k介电层，因为其介电常数大于二氧化硅的介电常数
Figure BDA0002814580210000101
。在一些实施方式中，栅极介电层228可以包括掺杂或未掺杂的氧化铪(HfO2)、掺杂或未掺杂的氧化锆(ZrO2)、掺杂或未掺杂的氧化钛(TiO2)或掺杂或未掺杂的氧化铝(Al2O3)。例如，栅极介电层228可以包括氧化硅铪(HfSiO)、氮氧化硅铪(HfSiON)或氧化铝铪(HfAlO)、氧化钽铪(HfTaO)、氧化锆铪(HfZrO)、氧化硅锆(ZrSiO2)、氧化钛铪(HfTiO)或其组合。在框112处的操作结束时，第一沟道构件2081、第二沟道构件2082和第三沟道构件2083中的每一个都被界面层222和栅极介电层228围绕。
参考图1和图8，方法100包括框114，其中，在栅极介电层228上方沉积牺牲层230。根据本公开，牺牲层230由可以选择性地去除而基本上不损坏栅极介电层的材料形成。在一些实施例中，牺牲层230由介电材料(诸如氧化硅、氮化硅、氧化铝、氧化钛、氧化锆)、半导体材料(诸如硅或锗或SiGe)、低密度金属氮化物(诸如氮化钛)或其他合适的材料形成。在一些示例中，牺牲层230可以由氧化硅或氮化硅形成。可以使用原子层沉积(ALD)或其他合适的方法来沉积牺牲层230。
参考图1和图9，方法100包括框116，其中，去除牺牲层230的一部分。在一些实施例中，在框116处，当蚀刻牺牲层230时，第一沟道构件2081、第二沟道构件2082和第三沟道构件2083中的每一个都用作蚀刻掩模或蚀刻屏蔽件。框116处的牺牲层230的去除包括基于形成牺牲层230的材料选择的干蚀刻工艺或湿蚀刻。在图9所示的一些实施方式中，在框116处的操作结束之后，保留牺牲层230的设置在相邻沟道构件之间的部分。牺牲层230的该剩余部分可以被称为剩余牺牲层230'。换句话说，框116处的操作可以去除第一沟道构件2081、第二沟道构件2082和第三沟道构件2083的最顶面和侧面上方的牺牲层230，以暴露沉积在其上方的栅极介电层228。这里，最顶面是指第一沟道构件2081、第二沟道构件2082和第三沟道构件2083中的最顶部沟道构件的顶面。如图9所示，剩余牺牲层230'竖直设置在相邻的第一沟道构件2081、第二沟道构件2082和第三沟道构件2083之间。
参考图1、图10、图11和图12，方法100包括框118，其中，选择性地去除第二区域2000中的剩余牺牲层230'。在图10所示的一些实施例中，可以形成图案化的硬掩模232，使得第一区域1000和第三区域3000被图案化的硬掩模232覆盖并且暴露第二区域2000。在示例性工艺中，首先在工件200上方毯式沉积硬掩模层，在沉积的硬掩模层上方沉积底部抗反射涂层(BARC)，然后在BARC层上方沉积光刻胶层。将光刻胶层预烘烤、通过暴露于穿过掩模或从掩模反射的图案化辐射进行图案化、后烘烤以及在使用显影剂的显影工艺中显影以形成图案化的光刻胶层。图案化的光刻胶层用作蚀刻掩模以图案化BARC层。然后，将图案化的BARC层用作蚀刻掩模以图案化硬掩模层，从而形成图案化的硬掩模232。在一些情况下，硬掩模层可以是单层或多层。现在参考图11，从暴露的第二区域2000去除剩余牺牲层230'，同时第一区域1000和第三区域3000保持被图案化的硬掩模232掩蔽。现在参考图12。使用适当的蚀刻工艺去除图案化的硬掩模232。
参考图1和图13，方法100包括框120，其中，第一功函数层234沉积在第一沟道构件2081、第二沟道构件2082和第三沟道构件2083上方。在一些实施例中，第一功函数层234可以是p型功函数层，并且可以包括氮化钛(TiN)、氮化硅钛(TiSiN)、氮化钽(TaN)、碳氮化钨(WCN)、钼(Mo)或其他合适的p型功函数材料。可以使用ALD工艺来形成第一功函数层234。因为剩余牺牲层230'保留在相邻的第一沟道构件2081和第三沟道构件2083之间，所以防止了第一功函数层234沉积在每个第一沟道构件2081和每个第三沟道构件2083的周围。反之，第二区域2000基本上没有剩余牺牲层230'，并且允许第一功函数层234以其围绕在每个第二沟道构件2082周围的方式形成。
在常规技术中，允许较早沉积的功函数层沉积在相邻的沟道构件之间。当要去除较早沉积的功函数层时，可能需要过蚀刻或增强蚀刻以去除沟道构件之间的空间中的功函数材料。过蚀刻或增强蚀刻工艺可能会损坏相邻晶体管中所需的功函数层。如果允许较早沉积的功函数层保留在沟道构件之间的空间中，则由于较早沉积的功函数层的存在，可以防止随后沉积的功函数层进入相邻的沟道构件之间。获得的器件的阈值电压可以大于必要的阈值电压，或者一个晶体管中的不同沟道构件可以具有不同的阈值电压。如在下面的描述和说明中将看到的，剩余牺牲层230'用于防止难以去除的功函数层沉积在相邻的第一沟道构件2081和相邻的第三沟道构件2083之间。这样，从一个或多个功函数层释放第一沟道构件2081或第三沟道构件2083的随后的蚀刻工艺不需要过蚀刻来去除相邻的第一沟道构件2081和相邻的第三沟道构件2083之间的功函数层材料。为了在不过蚀刻的情况下允许期望的功函数层围绕沟道构件，本公开的工艺可以生产低阈值电压晶体管、提高阈值电压均匀性并提高产量。
参考图1、图14、图15和图16，方法100包括框122，其中，第一功函数层234和第一沟道构件2081上方的剩余牺牲层230'被选择性地去除。在图14所示的一些实施例中，可以形成图案化的硬掩模236，使得第二区域2000和第三区域3000被图案化的硬掩模236覆盖，并且暴露第一区域1000。在示例性工艺中，首先在工件200上方毯式沉积硬掩模，在沉积的硬掩模上方沉积底部抗反射涂层(BARC)，然后在BARC层上方沉积光刻胶层。将光刻胶层预烘烤、通过暴露于穿过掩模或从掩模反射的图案化辐射进行图案化、后烘烤以及在使用显影剂的显影工艺中显影以形成图案化的光刻胶层。图案化的光刻胶层用作蚀刻掩模以图案化BARC层。然后，图案化的BARC层用作蚀刻掩模以图案化硬掩模层。在一些情况下，硬掩模层可以是单层或多层。现在参考图15，从暴露的第一区域1000去除第一功函数层234和剩余牺牲层230'，同时第二区域2000和第三区域3000仍被图案化的硬掩模236掩蔽。在一些实施方式中，可以在两个不同的蚀刻工艺中使用不同的蚀刻剂来去除第一功函数层234和剩余牺牲层230'，使得每个蚀刻工艺都针对待去除的材料。现在参考图16。使用适当的蚀刻工艺去除图案化的硬掩模236。在一些情况下，第一功函数层234具有在约0.5nm与约2nm之间的厚度。
参考图1和图17，方法100包括框124，其中，第二功函数层238沉积在第一沟道构件2081、第二沟道构件2082和第三沟道构件2083上方。第二功函数层238不同于第一功函数层234。在一些实施例中，第二功函数层238可以是n型功函数层，并且可以包括铝(Al)、钛铝(TiAl)、碳化钛铝(TiAlC)、碳化钽铝(TaAlC)、硅化钽铝(TaSiAl)、碳化硅钽(TaSiC)、硅化钽(TaSi)、碳化铪(HfC)、含铝层或其他合适的n型功函数层。第二功函数层238可以使用ALD工艺形成。因为从第一区域1000和第二区域2000去除了剩余牺牲层230'，所以第二功函数层238被允许以第二功函数层238围绕每个第一沟道构件2081和每个第二沟道构件2082的方式沉积。关于第三区域3000，第二功函数层238沉积在第一功函数层234上方，并且不允许围绕每个第三沟道构件2083。在一些情况下，第二功函数层238的厚度在约1nm和约3nm之间。如图18所示，第二功函数层238不会夹断相邻第一沟道构件2081之间以及相邻第二沟道构件2082之间的空间，使得随后的层(例如，图18所示的钝化层240)可以沉积在相邻第一沟道构件2081之间和相邻第二沟道构件2082之间。
参考图1和图18，方法100包括框126，其中，钝化层240沉积在第二功函数层238上方。框126的操作是可选的，并且当执行时，它们在第二功函数层238的沉积之后在同一工艺室中立即执行而不破坏真空。这是因为当第二功函数层238包括铝时，钝化层240起到防止第二功函数层238中的铝氧化的作用。当第二功函数层238不包括铝时，省略框126处的操作。在第二功函数层238包括铝的实施例中，执行框126处的操作。钝化层240也可以被称为保护层240。选择用于钝化层240的材料，使得钝化层240可以阻挡氧扩散或具有比铝更低的还原电势。当用于钝化层240的材料具有比铝更低的还原电势时，其通过优先氧化而充当氧沉。在一些实施例中，钝化层240可以由氮化钛(TiN)、氮化钛硅(TiSiN)、硅(Si)、氮化钽(TaN)、碳氮化钨(WCN)或其他合适的材料形成。在一些情况下，钝化层240可以形成为约0.5nm和约2nm之间的厚度。在一些其他情况下，可以省略钝化层240。在实施钝化层240的实施例中，沉积钝化层240以夹断相邻第一沟道构件2081之间和相邻第二沟道构件2082之间的空间，使得随后的层可以不沉积在相邻第一沟道构件2081之间和相邻第二沟道构件2082之间。
参考图1、图19、图20和图21，方法100包括框128，其中，第三区域3000中的第二功函数层238、钝化层240、第一功函数层234和剩余牺牲层230'被选择性地去除。在图19所示的一些实施例中，可以形成图案化的硬掩模242，使得第一区域1000和第二区域2000被图案化的硬掩模242覆盖并且暴露第三区域3000。在示例性工艺中，首先在工件200上方毯式沉积硬掩模，在沉积的硬掩模上方沉积底部抗反射涂层(BARC)，然后在BARC层上方沉积光刻胶层。将光刻胶层预烘烤、通过暴露于穿过掩模或从掩模反射的图案化辐射进行图案化、后烘烤以及在使用显影剂的显影工艺中显影以形成图案化的光刻胶层。图案化的光刻胶层用作蚀刻掩模以图案化BARC层。然后，图案化的BARC层用作蚀刻掩模以图案化硬掩模层。在一些情况下，硬掩模层可以是单层或多层。现在参考图20，从暴露的第三区域3000去除钝化层240、第二功函数层238、第一功函数层234和剩余牺牲层230'，同时第一区域1000和第二区域2000仍被图案化的硬掩模242掩蔽。现在参考图21。使用适当的蚀刻工艺去除图案化的硬掩模242。
参考图1和图22，方法100包括框130，其中，胶层244沉积在第一沟道构件2081、第二沟道构件2082和第三沟道构件2083上方。在一些实施例中，胶层244可以是p型功函数层，并且可以包括氮化钛(TiN)、氮化硅钛(TiSiN)、氮化钽(TaN)、碳氮化钨(WCN)、钼(Mo)或其他合适的p型功函数材料。即，胶层244的组成可以与第一功函数层234相同。在一些实施方式中，胶层244可以通过ALD形成为约2nm和约5nm之间的厚度。在一些情况下，沉积胶层244，使得相邻第三沟道构件2083之间的空间被夹断，使得后续层可以不沉积在相邻第三沟道构件2083之间。
参考图1和图23，方法100可以包括框132，其中，执行其他工艺。这样的其他工艺的示例可以包括在沟道区域(包括第一沟道区域1100、第二沟道区域2100和第三沟道区域3100)上方沉积金属填充层246。金属填充层246可以包括钨(W)或钴(Co)。在沉积金属填充层246时，在第一区域1000中形成第一金属栅极堆叠件250A，在第二区域2000中形成第二金属栅极堆叠件250B，并且在第三区域3000中形成第三金属栅极堆叠件250C。第一金属栅极堆叠件250A包括界面层222、栅极介电层228、第二功函数层238、钝化层240、胶层244和金属填充层246。第二金属栅极堆叠件250B包括界面层222、栅极介电层228、第一功函数层234、第二功函数层238、钝化层240、胶层244和金属填充层246。第三金属栅极堆叠件250C包括界面层222、栅极介电层228、胶层244和金属填充层246。框132处的其他工艺的示例还可以包括层间介电(ILD)层的形成、穿过ILD层以耦合至源极/漏极部件的源极/漏极接触件的形成以及耦合至栅极结构的栅极连接件的形成。
在方法100中的操作结束时，在第一区域1000中形成第一GAA晶体管260A，在第二区域2000中形成第二GAA晶体管260B，并且在第三区域3000中形成第三GAA晶体管260C。第一GAA晶体管260A具有第一金属栅极堆叠件250A。第二GAA晶体管260B具有第二金属栅极堆叠件250B。第三GAA晶体管260C具有第三金属栅极堆叠件250C。如图23所示，因为第二功函数层238是n型功函数层，其直接形成在栅极介电层228上而没有中间的p型功函数层(即，第一功函数层234)，所以第一GAA晶体管260A可以是n型GAA晶体管，其阈值电压低于可能的阈值电压，而没有中间的p型功函数层。通过使用剩余牺牲层230'(如图13所示)，能够或至少促使第一区域1000中不存在中间p型功函数层，这防止第一功函数层234(或过多的第一功函数层234)进入相邻第一沟道构件2081之间。由于相邻第一沟道构件2081之间的第一功函数层234的数量减少或缺乏，所以不需要湿法过蚀刻来从第一沟道构件2081之间的空间中去除难以去除的第一功函数层234。
类似地，因为胶层244是p型功函数层，其直接形成在栅极介电层228上而没有相邻的n型功函数层(即，第二功函数层238)，所以第三GAA晶体管260C可以是p型GAA晶体管，其阈值电压低于可能的阈值电压，而没有相邻的n型功函数层。N型功函数层可以包括高扩散性成分，其可以扩散到相邻的p型功函数层中，以不期望地使功函数从偏离价带。例如，n型功函数层中的铝可以扩散到p型器件的p型功函数层中，从而使功函数远离价带并且不期望地增加阈值电压。通过从第三区域3000去除第二功函数层238(即，n型功函数层)，可以使得没有来自n型功函数层的高扩散性成分扩散到胶层244(即，p型功函数层)中。通过使用剩余的牺牲层230'(如图13和图17所示)，能够或至少促使第三区域3000中不存在相邻的n型功函数层，这防止第一功函数层234(或太多的第一功函数层234)和第二功函数层238(或太多的第二功函数层238)进入相邻第三沟道构件2083之间。因为相邻第三沟道构件2083之间的第一功函数层234和第二功函数层238的数量减少或缺乏，所以不需要湿法过蚀刻来从第三沟道构件2083之间的空间中去除难以去除的第一功函数层234和第二功函数层238。
在图23所示的实施例中，第二GAA晶体管260B包括处于第一GAA晶体管260A的n型阈值电压和第三GAA晶体管260C的p型阈值电压之间的中级阈值电压。与第一金属栅极堆叠件250A和第三金属栅极堆叠件250C不同，第二GAA晶体管260B的第二金属栅极堆叠件250B包括第一功函数层234和第二功函数层238。
在本文中未明确示出的一些实施例中，一个或多个偶极层可以可选地结合在第一金属栅极堆叠件250A、第二金属栅极堆叠件250B和第三金属栅极堆叠件250C中，以进一步使半导体器件200中的阈值电压多样化。例如，取决于电子亲和力和氧原子密度，偶极层可以是n偶极层或p偶极层。结合在第一金属栅极堆叠件250A、第二金属栅极堆叠件250B和第三金属栅极堆叠件250C的每一个中的偶极层可以进一步将功函数移近价带或导带，从而偏移获得的第一GAA晶体管260A、第二GAA晶体管260B和第三GAA晶体管260C的阈值电压。用于n偶极层的示例性材料包括氧化镧、氧化镁或氧化钇。用于p偶极层的示例性材料包括氧化铝、氧化钛或氧化铌。在一些情况下，偶极材料可以被热引入栅极介电层228中而基本不增加栅极介电层228的厚度。通过在一些第一GAA晶体管260A中选择性地处理栅极介电层228，而在一些其他第一GAA晶体管260A中不这样处理，两个第一GAA晶体管260A可以进一步转变为具有不同阈值电压的第一GAA晶体管260A的两个子组。第二GAA晶体管260B和第三GAA晶体管260C也是如此。即，通过选择性地引入一种偶极材料，可以在具有6个阈值电压电平的六种类型的GAA晶体管中制造具有3个阈值电压电平的三种类型的GAA晶体管。因此可以看出，本公开的工艺和半导体器件为形成具有多种阈值电压的GAA晶体管打开了大门。
基于以上讨论，本公开提供了优于常规GAA晶体管的优点及其形成工艺。然而，应该理解，其他实施例可以提供额外的优势，并且不是所有优势都必需在本文中公开，且没有特定优势对于所有实施例都是必需的。本公开提供了一种半导体器件形成工艺，其利用牺牲层来防止待去除的功函数层进入相邻沟道构件之间的空间。这种布置允许令人满意地去除待去除的功函数层，而不需要可能会损坏相邻结构的过蚀刻。所公开的工艺允许n型功函数层完全围绕n型GAA晶体管中的沟道构件，并且基本上完全从p型GAA晶体管中的沟道构件周围去除n型功函数层。结果，根据本公开的n型GAA晶体管和p型GAA晶体管具有较低的阈值电压。
本公开的公开内容提供了半导体器件及其形成方法的实施例。在一个实施例中，提供了一种半导体器件。该半导体器件包括第一全环栅(GAA)晶体管、第二GAA晶体管和第三GAA晶体管。第一GAA晶体管包括多个第一沟道构件、位于多个第一沟道构件上方的界面层、位于界面层上方的栅极介电层、位于栅极介电层上方并与栅极介电层接触的第一功函数层以及位于第一功函数层上方的胶层。第二GAA晶体管包括多个第二沟道构件、位于多个第二沟道构件上方的界面层、位于界面层上方的栅极介电层、位于栅极介电层上方并与栅极介电层接触的第二功函数层、位于第二功函数层上方并与第二功函数层接触的第一功函数层以及位于第一功函数层上方的胶层。第三GAA晶体管包括多个第三沟道构件、位于多个第三沟道构件上方的界面层、位于界面层上方的栅极介电层以及位于栅极介电层上方的胶层。
在一些实施例中，第一功函数层包括铝(Al)、钛铝(TiAl)、碳化钛铝(TiAlC)、碳化钽铝(TaAlC)、硅化钽铝(TaSiAl)、碳化硅钽(TaSiC)、硅化钽(TaSi)或碳化铪(HfC)，第二功函数层包括氮化钛(TiN)、氮化钛硅(TiSiN)、氮化钽(TaN)、碳氮化钨(WCN)或钼(Mo)。在一些实施方案中，其中，胶层包括氮化钛(TiN)、氮化硅钛(TiSiN)、氮化钽(TaN)、碳氮化钨(WCN)或钼(Mo)。在一些情况下，第一GAA晶体管还包括设置在第一功函数层和胶层之间的钝化层，第二GAA晶体管还包括设置在第一功函数层和胶层之间的钝化层，并且第三GAA晶体管没有钝化层。在一些实施例中，第一功函数层包括介于1nm和约3nm之间的厚度，第二功函数层包括介于约0.5nm和约2nm之间的厚度，钝化层包括介于约0.5nm与约2nm之间的厚度，并且胶层包括介于约2nm和约5nm之间的厚度。在一些实施方式中，钝化层包括氮化钛(TiN)、氮化硅钛(TiSiN)、硅(Si)、氮化钽(TaN)或碳氮化钨(WCN)。在一些实施例中，第一GAA晶体管、第二GAA晶体管和第三GAA晶体管中的每一个还包括位于胶层上方的金属填充层，并且金属填充层包括钨(W)或钴(Co)。在一些实施方式中，第一功函数层完全围绕多个所述多个第一沟道构件中的每一个设置。
在另一实施例中，提供了一种方法。该方法包括：提供工件，该工件包括衬底、位于衬底的第一区域中的第一竖直堆叠沟道构件、位于衬底的第二区域中的第二竖直堆叠沟道构件和位于衬底的第三区域中的第三竖直堆叠沟道构件；在第一竖直堆叠沟道构件、第二竖直堆叠沟道构件和第三竖直堆叠沟道构件上方沉积栅极介电层；在栅极介电层上方沉积牺牲层；蚀刻牺牲层使得牺牲层的一部分保持设置在第一竖直堆叠沟道构件、第二竖直堆叠沟道构件和第三竖直堆叠沟道构件中的相邻沟道构件之间；选择性地去除第二区域中的所有牺牲层；在第一竖直堆叠沟道构件、第二竖直堆叠沟道构件和第三竖直堆叠沟道构件上方沉积第一功函数层；选择性地去除第一区域中的第一功函数层和牺牲层；在第一竖直堆叠沟道构件、第二竖直堆叠沟道构件和第三竖直堆叠沟道构件上方沉积第二功函数层，第二功函数层不同于第一功函数层；以及在第二功函数层上方沉积钝化层。
在一些实施例中，提供工件包括：在衬底的第一区域、第二区域和第三区域上方形成多个交替的半导体层；图案化多个交替的半导体层以在第一区域中形成第一有源区域、在第二区域中形成第二有源区域以及在第三区域中形成第三有源区域；以及选择性地去除多个第二半导体层，以在第一有源区域中形成第一竖直堆叠沟道构件、在第二有源区域中形成第二竖直堆叠沟道构件以及在第三有源区域中形成第三竖直堆叠沟道构件。多个交替的半导体层包括被多个第二半导体层交错的多个第一半导体层。在一些实施方式中，牺牲层的蚀刻暴露沉积在第一竖直堆叠沟道构件、第二竖直堆叠沟道构件和第三竖直堆叠沟道构件的侧表面上方的栅极介电层。在一些情况下，牺牲层包括氧化硅或氮化硅。在一些实施例中，第一功函数层包括铝(Al)、钛铝(TiAl)、碳化钛铝(TiAlC)、碳化钽铝(TaAlC)、硅化钽铝(TaSiAl)、碳化硅钽(TaSiC)、硅化钽(TaSi)或碳化铪(HfC)，第二功函数层包括氮化钛(TiN)、氮化钛硅(TiSiN)、氮化钽(TaN)、碳氮化钨(WCN)或钼(Mo)。在一些实施例中，钝化层包括氮化钛(TiN)、氮化硅钛(TiSiN)、硅(Si)、氮化钽(TaN)或碳氮化钨(WCN)。在一些实施例中，该方法还可以包括：选择性地去除第三区域中的钝化层、第一功函数层、第二功函数层和牺牲层；在第一竖直堆叠沟道构件、第二竖直堆叠沟道构件和第三竖直堆叠沟道构件上方沉积胶层；以及在胶层上方沉积金属填充层。在一些实施方式中，其中，胶层包括氮化钛(TiN)、氮化硅钛(TiSiN)、氮化钽(TaN)、碳氮化钨(WCN)或钼(Mo)，并且金属填充层包括钨(W)或钴(Co)。
在又一实施例中，提供了一种方法。该方法包括：提供工件，该工件具有衬底、位于衬底的第一区域中的第一竖直堆叠沟道构件、位于衬底的第二区域中的第二竖直堆叠沟道构件以及位于衬底的第三区域中的第三竖直堆叠沟道构件；在第一竖直堆叠沟道构件、第二竖直堆叠沟道构件和第三竖直堆叠沟道构件上方沉积栅极介电层；在栅极介电层上方沉积牺牲层；部分地和选择性地蚀刻牺牲层使得牺牲层的一部分设置在第一竖直堆叠沟道构件、第二竖直堆叠沟道构件和第三竖直堆叠沟道构件中的相邻沟道构件之间；选择性地去除第二区域中的所有牺牲层；在第一竖直堆叠沟道构件、第二竖直堆叠沟道构件和第三竖直堆叠沟道构件上方沉积第一功函数层；选择性地去除第一区域中的第一功函数层和牺牲层；在第一竖直堆叠沟道构件、第二竖直堆叠沟道构件和第三竖直堆叠沟道构件上方沉积第二功函数层，第二功函数层不同于第一功函数层；在第二功函数层上方沉积钝化层；选择性地去除第三区域中的钝化层、第一功函数层、第二功函数层和牺牲层；在第一竖直堆叠沟道构件、第二竖直堆叠沟道构件和第三竖直堆叠沟道构件上方沉积胶层；以及在胶层上方沉积金属填充层。第一功函数层不同于第二功函数层，并且第一功函数层的组成与胶层的组成基本相同。
在一些实施例中，第二功函数层包括铝(Al)。在一些实施方式中，牺牲层的设置在第三竖直堆叠沟道构件中的相邻沟道构件之间的部分防止第一功函数层和第二功函数层沉积在第三竖直堆叠沟道构件中的相邻沟道构件之间。在一些情况下，其中，选择性地去除第二区域中的所有牺牲层包括使用对牺牲层具有蚀刻选择性的蚀刻剂。
根据本申请的一个实施例，提供了一种半导体器件，包括：第一全环栅(GAA)晶体管，包括：多个第一沟道构件，位于多个第一沟道构件上方的界面层，位于界面层上方的栅极介电层，位于栅极介电层上方并与栅极介电层接触的第一功函数层，和位于第一功函数层上方的胶层；第二GAA晶体管，包括：多个第二沟道构件，位于多个第二沟道构件上方的界面层，位于界面层上方的栅极介电层，位于栅极介电层上方并与栅极介电层接触的第二功函数层，位于第二功函数层上方并与第二功函数层接触的第一功函数层，和位于第一功函数层上方的胶层；以及第三GAA晶体管，包括：多个第三沟道构件，位于多个第三沟道构件上方的界面层，位于界面层上方的栅极介电层，和位于栅极介电层上方的胶层。在一些实施例中，第一功函数层包括铝(Al)、钛铝(TiAl)、碳化钛铝(TiAlC)、碳化钽铝(TaAlC)、硅化钽铝(TaSiAl)、碳化硅钽(TaSiC)、硅化钽(TaSi)或碳化铪(HfC)，其中，第二功函数层包括氮化钛(TiN)、氮化硅钛(TiSiN)、氮化钽(TaN)、碳氮化钨(WCN)或钼(Mo)。在一些实施例中，胶层包括氮化钛(TiN)、氮化硅钛(TiSiN)、氮化钽(TaN)、碳氮化钨(WCN)或钼(Mo)。在一些实施例中，第一GAA晶体管还包括设置在第一功函数层和胶层之间的钝化层，其中，第二GAA晶体管还包括设置在第一功函数层和胶层之间的钝化层，其中，第三GAA晶体管没有钝化层。在一些实施例中，第一功函数层的厚度在1nm和约3nm之间，其中，第二功函数层的厚度在约0.5nm和约2nm之间，其中，钝化层的厚度在约0.5nm和约2nm之间，其中，胶层的厚度在约2nm和约5nm之间。在一些实施例中，钝化层包括氮化钛(TiN)、氮化硅钛(TiSiN)、硅(Si)、氮化钽(TaN)或碳氮化钨(WCN)。在一些实施例中，第一GAA晶体管、第二GAA晶体管和第三GAA晶体管中的每一个还包括位于胶层上方的金属填充层，其中，金属填充层包括钨(W)或钴(Co)。在一些实施例中，第一功函数层完全围绕多个第一沟道构件中的每一个设置。
根据本申请的另一个实施例，提供了一种制造半导体器件的方法，包括：提供工件，工件包括衬底、位于衬底的第一区域中的第一竖直堆叠沟道构件、位于衬底的第二区域中的第二竖直堆叠沟道构件和位于衬底的第三区域中的第三竖直堆叠沟道构件；在第一竖直堆叠沟道构件、第二竖直堆叠沟道构件和第三竖直堆叠沟道构件上方沉积栅极介电层；在栅极介电层上方沉积牺牲层；蚀刻牺牲层使得牺牲层的一部分保持设置在第一竖直堆叠沟道构件、第二竖直堆叠沟道构件和第三竖直堆叠沟道构件中的相邻沟道构件之间；选择性地去除第二区域中的所有牺牲层；在第一竖直堆叠沟道构件、第二竖直堆叠沟道构件和第三竖直堆叠沟道构件上方沉积第一功函数层；选择性地去除第一区域中的第一功函数层和牺牲层；在第一竖直堆叠沟道构件、第二竖直堆叠沟道构件和第三竖直堆叠沟道构件上方沉积第二功函数层，第二功函数层不同于第一功函数层；以及在第二功函数层上方沉积钝化层。在一些实施例中，提供工件包括：在衬底的第一区域、第二区域和第三区域上方形成多个交替的半导体层，多个交替的半导体层包括被多个第二半导体层交错的多个第一半导体层；图案化多个交替的半导体层以在第一区域中形成第一有源区域、在第二区域中形成第二有源区域以及在第三区域中形成第三有源区域；以及选择性地去除多个第二半导体层，以在第一有源区域中形成第一竖直堆叠沟道构件、在第二有源区域中形成第二竖直堆叠沟道构件以及在第三有源区域中形成第三竖直堆叠沟道构件。在一些实施例中，牺牲层的蚀刻暴露沉积在第一竖直堆叠沟道构件、第二竖直堆叠沟道构件和第三竖直堆叠沟道构件的侧表面上方的栅极介电层。在一些实施例中，牺牲层包括氧化硅或氮化硅。在一些实施例中，第一功函数层包括铝(Al)、钛铝(TiAl)、碳化钛铝(TiAlC)、碳化钽铝(TaAlC)、硅化钽铝(TaSiAl)、碳化硅钽(TaSiC)、硅化钽(TaSi)或碳化铪(HfC)，其中，第二功函数层包括氮化钛(TiN)、氮化硅钛(TiSiN)、氮化钽(TaN)、碳氮化钨(WCN)或钼(Mo)。在一些实施例中，钝化层包括氮化钛(TiN)、氮化硅钛(TiSiN)、硅(Si)、氮化钽(TaN)或碳氮化钨(WCN)。在一些实施例中，制造半导体器件的方法还包括：选择性地去除第三区域中的钝化层、第一功函数层、第二功函数层和牺牲层；在第一竖直堆叠沟道构件、第二竖直堆叠沟道构件和第三竖直堆叠沟道构件上方沉积胶层；以及在胶层上方沉积金属填充层。在一些实施例中，胶层包括氮化钛(TiN)、氮化硅钛(TiSiN)、氮化钽(TaN)、碳氮化钨(WCN)或钼(Mo)，其中，金属填充层包括钨(W)或钴(Co)。
根据本申请的又一个实施例，提供了一种制造半导体器件的方法，包括：提供工件，工件包括衬底、位于衬底的第一区域中的第一竖直堆叠沟道构件、位于衬底的第二区域中的第二竖直堆叠沟道构件和位于衬底的第三区域中的第三竖直堆叠沟道构件；在第一竖直堆叠沟道构件、第二竖直堆叠沟道构件和第三竖直堆叠沟道构件上方沉积栅极介电层；在栅极介电层上方沉积牺牲层；部分地和选择性地蚀刻牺牲层使得牺牲层的一部分设置在第一竖直堆叠沟道构件、第二竖直堆叠沟道构件和第三竖直堆叠沟道构件中的相邻沟道构件之间；选择性地去除第二区域中的所有牺牲层；在第一竖直堆叠沟道构件、第二竖直堆叠沟道构件和第三竖直堆叠沟道构件上方沉积第一功函数层；选择性地去除第一区域中的第一功函数层和牺牲层；在第一竖直堆叠沟道构件、第二竖直堆叠沟道构件和第三竖直堆叠沟道构件上方沉积第二功函数层，第二功函数层不同于第一功函数层；在第二功函数层上方沉积钝化层；选择性地去除第三区域中的钝化层、第一功函数层、第二功函数层和牺牲层；选择性地去除第三区域中的钝化层、第一功函数层、第二功函数层和牺牲层；在第一竖直堆叠沟道构件、第二竖直堆叠沟道构件和第三竖直堆叠沟道构件上方沉积胶层；以及在胶层上方沉积金属填充层，其中，第一功函数层不同于第二功函数层，其中，第一功函数层的组成与胶层的组成基本相同。在一些实施例中，第二功函数层包括铝(Al)。在一些实施例中，牺牲层的设置在第三竖直堆叠沟道构件中的相邻沟道构件之间的部分防止第一功函数层和第二功函数层沉积在第三竖直堆叠沟道构件中的相邻沟道构件之间。在一些实施例中，其中，选择性地去除第二区域中的所有牺牲层包括使用对牺牲层具有蚀刻选择性的蚀刻剂。
上述内容概括了几个实施例的特征使得本领域技术人员可更好地理解本发明的各个方面。本领域技术人员应该理解，可以很容易地使用本发明作为基础来设计或更改其他的处理和结构以用于达到与本发明所介绍实施例相同的目的和/或实现相同优点。本领域技术人员也应该意识到、这种等同构造并不背离本发明的精神和范围、并且在不背离本发明的精神和范围的情况下，本文中他们可以做出多种变化、替换以及改变。例如，通过对位线导体和字线导体实施不同的厚度，可以实现导体的不同电阻。但是，也可以使用改变金属导体的电阻的其他技术。

Claims (10)

1.一种半导体器件，包括：
第一全环栅晶体管，包括：
多个第一沟道构件，
位于所述多个第一沟道构件上方的界面层，
位于所述界面层上方的栅极介电层，
位于所述栅极介电层上方并与所述栅极介电层接触的第一功函数层，和
位于所述第一功函数层上方的胶层；
第二全环栅晶体管，包括：
多个第二沟道构件，
位于所述多个第二沟道构件上方的界面层，
位于所述界面层上方的栅极介电层，
位于所述栅极介电层上方并与所述栅极介电层接触的第二功函数层，
位于所述第二功函数层上方并与所述第二功函数层接触的第一功函数层，和
位于所述第一功函数层上方的胶层；以及
第三全环栅晶体管，包括：
多个第三沟道构件，
位于所述多个第三沟道构件上方的界面层，
位于所述界面层上方的栅极介电层，和
位于所述栅极介电层上方的胶层。
2.根据权利要求1所述的半导体器件，
其中，所述第一功函数层包括铝(Al)、钛铝(TiAl)、碳化钛铝(TiAlC)、碳化钽铝(TaAlC)、硅化钽铝(TaSiAl)、碳化硅钽(TaSiC)、硅化钽(TaSi)或碳化铪(HfC)，
其中，所述第二功函数层包括氮化钛(TiN)、氮化硅钛(TiSiN)、氮化钽(TaN)、碳氮化钨(WCN)或钼(Mo)。
3.根据权利要求2所述的半导体器件，其中，所述胶层包括氮化钛(TiN)、氮化硅钛(TiSiN)、氮化钽(TaN)、碳氮化钨(WCN)或钼(Mo)。
4.根据权利要求1所述的半导体器件，
其中，所述第一全环栅晶体管还包括设置在所述第一功函数层和所述胶层之间的钝化层，
其中，所述第二全环栅晶体管还包括设置在所述第一功函数层和所述胶层之间的钝化层，
其中，所述第三全环栅晶体管没有钝化层。
5.根据权利要求4所述的半导体器件，
其中，所述第一功函数层的厚度在1nm和约3nm之间，
其中，所述第二功函数层的厚度在约0.5nm和约2nm之间，
其中，所述钝化层的厚度在约0.5nm和约2nm之间，
其中，所述胶层的厚度在约2nm和约5nm之间。
6.根据权利要求4所述的半导体器件，其中，所述钝化层包括氮化钛(TiN)、氮化硅钛(TiSiN)、硅(Si)、氮化钽(TaN)或碳氮化钨(WCN)。
7.根据权利要求1所述的半导体器件，
所述第一全环栅晶体管、所述第二全环栅晶体管和所述第三全环栅晶体管中的每一个还包括位于所述胶层上方的金属填充层，
其中，所述金属填充层包括钨(W)或钴(Co)。
8.根据权利要求1所述的半导体器件，其中，所述第一功函数层完全围绕所述多个第一沟道构件中的每一个设置。
9.一种制造半导体器件的方法，包括：
提供工件，所述工件包括衬底、位于所述衬底的第一区域中的第一竖直堆叠沟道构件、位于所述衬底的第二区域中的第二竖直堆叠沟道构件和位于所述衬底的第三区域中的第三竖直堆叠沟道构件；
在所述第一竖直堆叠沟道构件、所述第二竖直堆叠沟道构件和所述第三竖直堆叠沟道构件上方沉积栅极介电层；
在所述栅极介电层上方沉积牺牲层；
蚀刻所述牺牲层使得所述牺牲层的一部分保持设置在所述第一竖直堆叠沟道构件、所述第二竖直堆叠沟道构件和所述第三竖直堆叠沟道构件中的相邻沟道构件之间；
选择性地去除所述第二区域中的所有牺牲层；
在所述第一竖直堆叠沟道构件、所述第二竖直堆叠沟道构件和所述第三竖直堆叠沟道构件上方沉积第一功函数层；
选择性地去除所述第一区域中的第一功函数层和牺牲层；
在所述第一竖直堆叠沟道构件、所述第二竖直堆叠沟道构件和所述第三竖直堆叠沟道构件上方沉积第二功函数层，所述第二功函数层不同于所述第一功函数层；以及
在所述第二功函数层上方沉积钝化层。
10.一种制造半导体器件的方法，包括：
提供工件，所述工件包括衬底、位于所述衬底的第一区域中的第一竖直堆叠沟道构件、位于所述衬底的第二区域中的第二竖直堆叠沟道构件和位于所述衬底的第三区域中的第三竖直堆叠沟道构件；
在所述第一竖直堆叠沟道构件、所述第二竖直堆叠沟道构件和所述第三竖直堆叠沟道构件上方沉积栅极介电层；
在所述栅极介电层上方沉积牺牲层；
部分地和选择性地蚀刻所述牺牲层使得所述牺牲层的一部分设置在所述第一竖直堆叠沟道构件、所述第二竖直堆叠沟道构件和所述第三竖直堆叠沟道构件中的相邻沟道构件之间；
选择性地去除所述第二区域中的所有牺牲层；
在所述第一竖直堆叠沟道构件、所述第二竖直堆叠沟道构件和所述第三竖直堆叠沟道构件上方沉积第一功函数层；
选择性地去除所述第一区域中的第一功函数层和牺牲层；
在所述第一竖直堆叠沟道构件、所述第二竖直堆叠沟道构件和所述第三竖直堆叠沟道构件上方沉积第二功函数层，所述第二功函数层不同于所述第一功函数层；
在所述第二功函数层上方沉积钝化层；
选择性地去除所述第三区域中的钝化层、第一功函数层、第二功函数层和牺牲层；
在所述第一竖直堆叠沟道构件、所述第二竖直堆叠沟道构件和所述第三竖直堆叠沟道构件上方沉积胶层；以及
在所述胶层上方沉积金属填充层，
其中，所述第一功函数层不同于所述第二功函数层，
其中，所述第一功函数层的组成与所述胶层的组成基本相同。
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