CN112510041A - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN112510041A
CN112510041A CN202010966587.7A CN202010966587A CN112510041A CN 112510041 A CN112510041 A CN 112510041A CN 202010966587 A CN202010966587 A CN 202010966587A CN 112510041 A CN112510041 A CN 112510041A
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gate
type
dielectric layer
region
channel
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CN202010966587.7A
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Inventor
廖忠志
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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    • H01L21/8232—Field-effect technology
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Abstract

一种半导体装置包括第一环绕式栅极晶体管和第二环绕式栅极晶体管，第一环绕式栅极晶体管包括多个第一通道构件和在第一通道构件上方的第一栅极介电层，第二环绕式栅极晶体管包括多个第二通道构件和在第二通道构件上方的第二栅极介电层。第一通道构件的每一个的第一宽度大于第二通道构件的每一个的第二宽度。第一栅极介电层的第一厚度小于第二栅极介电层的第二厚度。

Description

半导体装置
技术领域
本公开涉及一种半导体装置，尤其涉及用于高速和低漏电应用的半导体装置。
背景技术
半导体集成电路(integrated circuit；IC)工业呈指数成长。在IC材料及IC设计的技术进步产生多个IC世代，每一个IC世代比上一个IC世代有更小及更复杂的电路。在IC发展过程中，功能密度(例如:每一芯片区域的相连元件数量)通常都会增加，而几何尺寸(即工艺可作出的最小部件或线路)会下降。此微缩过程通常通过增加生产效率及降低相关成本提供了优势。这种微缩还增加了处理和制造IC的复杂性。
举例来说，随着集成电路(IC)技术朝着更小的技术节点发展，已经引入了多栅极装置以通过增加栅极-通道耦合、减小截止状态电流(off-state current)以及减小短通道效应(short-channel effect；SCE)来改善栅极控制。多栅极装置通常是指具有设置在通道区的一侧以上的栅极堆叠(或其一部分)的装置。鳍式场效应晶体管(Fin-like fieldeffect transistor；FinFET)和环绕式栅极(gate-all-around；GAA)晶体管(两者也称为非平面晶体管)是多栅极装置的示例，其已成为高效能和低漏电的受欢迎和有潜力的候选。FinFET具有被栅极在一个侧以上包裹的升高通道(例如：栅极包裹了从基板延伸的半导体材料的“鳍片”的顶部和侧壁)。与平面晶体管相比，这种配置提供了更好的通道控制，并大大降低了SCE，特别是通过减少次临界电流(sub-threshold leakage)，即在“截止(off)”状态的FinFET的源极和漏极之间的耦合。GAA晶体管的栅极堆叠可以部分或全部延伸围绕通道区，以在两侧或多侧上提供对通道区的访问。GAA晶体管的通道区可以由纳米线、纳米片、其他纳米结构及/或其他合适结构形成。在一些实施例中，这种通道区包括垂直堆叠的多个纳米线(其水平延伸，从而提供水平定向的通道)。这种GAA晶体管可以被称为垂直堆叠的水平GAA(vertically-stacked horizontal GAA；VGAA)晶体管。
IC装置对不同的应用需要不同的晶体管配置。例来说，用于逻辑装置的晶体管可能需要高速和高驱动电流，而用于存储器装置的晶体管可能需要低漏电。尽管现有的GAA晶体管和工艺通常足以制造具有不同阈值电压的晶体管，但它们并不是在每个方面都完全令人满意。
发明内容
本公开的目的在于提供一种半导体装置，以解决上述至少一个问题。
本公开提供一种半导体装置。半导体装置包括第一环绕式栅极晶体管和第二环绕式栅极晶体管。第一环绕式栅极晶体管包括多个第一通道构件和在第一通道构件上方的第一栅极介电层。第二环绕式栅极晶体管包括多个第二通道构件和在第二通道构件上方的第二栅极介电层。第一通道构件的每一个的第一宽度(W1)大于第二通道构件的每一个的第二宽度(W2)。第一栅极介电层的第一厚度(GL1)小于第二栅极介电层的第二厚度(GL2)。
本公开提供一种半导体装置。半导体装置包括基板、第一N型环绕式栅极晶体管和第一P型环绕式栅极晶体管、第二N型环绕式栅极晶体管和第二P型环绕式栅极晶体管。第一N型环绕式栅极晶体管和第一P型环绕式栅极晶体管在第一区中，其中第一N型环绕式栅极晶体管和第一P型环绕式栅极晶体管的每一个包括多个第一通道构件和在第一通道构件上方的第一栅极介电层。第二N型环绕式栅极晶体管和第二P型环绕式栅极晶体管在第二区中，其中第二N型环绕式栅极晶体管和第二P型环绕式栅极晶体管的每一个包括多个第二通道构件和在第二通道构件上方的第二栅极介电层。第一通道构件的每一个的第一宽度(W1)大于第二通道构件的每一个的第二宽度(W2)。第一栅极介电层的第一厚度(GL1)小于第二栅极介电层的第二厚度(GL2)。
本公开提供一种半导体装置的形成方法。半导体装置的形成方法包括在基板的第一区和第二区上方形成多个交替半导体层，交替半导体层包括被多个第二半导体层插入的多个第一半导体层；图案化在第一区上方的交替半导体层，以形成具有第一宽度(W1)的第一有源区；图案化在第二区上方的交替半导体层，以形成具有第二宽度(W2)的第二有源区，第二宽度(W2)小于第一宽度(W1)；从第二半导体层中释放第一半导体层，以在第一有源区的第一通道区中形成多个第一通道构件，并且在第二有源区的第二通道区中形成多个第二通道构件；在上第一通道构件上方形成第一栅极介电层，第一栅极介电层具有第一厚度(GL1)；以及在第二通道构件上方形成第二栅极介电层，第二栅极介电层具有大于第一厚度(GL1)的第二厚度(GL2)。
本公开的有益效果在于，本公开提出了一种半导体装置，其包括用于高效能应用的第一环绕式栅极晶体管和用于低功耗应用的第二环绕式栅极晶体管。两者均由相同的交替半导体层堆叠形成，第一环绕式栅极晶体管具有较宽的通道构件和较薄的栅极介电层，并且第二环绕式栅极晶体管具有较窄的通道构件和较厚的栅极介电层。第一环绕式栅极晶体管提供高速和高驱动电流，并且第二环绕式栅极晶体管提供低漏电和低功耗。
附图说明
本公开的观点从后续实施例以及附图可以更佳理解。须知示意图为范例，并且不同特征并无示意于此。不同特征的尺寸可能任意增加或减少以清楚论述。还应强调的是，所附附图仅显示了本公开的典型实施例，因此不应视为对本公开范围的限制，本公开可以同等地应用于其他实施例。
图1是根据本公开实施例的形成半导体装置的方法的流程图。
图2、图3、图4、图5、图6、图7、图8、图9A、图9B以及图10是根据本公开实施例的在各种工艺站点的工件的局部剖面图。
图11是根据本公开实施例的具有两个相邻标准单元的半导体装置的俯视图。
图12是根据本公开实施例的的图11中的半导体装置的局部剖面图。
附图标记如下：
100:方法
102-120:操作
200:工件
2040:交替半导体层
202:基板
10:第一区
20:第二区
2021P,2022P:P型掺杂区
2021N,2022N:N型掺杂区
204A:第一半导体层
204B:第二半导体层
L1:第一厚度
L2:第二厚度
205A:第一鳍片结构
205B:第二鳍片结构
W1:第一宽度
W2:第二宽度
206:介电隔离特征
209A:第一通道区
209B:第二通道区
207:冗余栅极堆叠
208:金属栅极堆叠
218:介电冗余栅极堆叠
220:栅极间隔物
210:栅极端介电特征
222:源极/漏极特征
214-1:第一通道构件
214-2:第二通道构件
P:间距
MT:构件厚度
S:间隔
216-1:第一栅极介电层
GL1:第一栅极介电层厚度
216-2:第二栅极介电层
GL2:第二栅极介电层厚度
211-1:N型金属栅极堆叠
211-2:P型金属栅极堆叠
217:栅极顶部硬掩模
224:硅化物层
226:源极/漏极接点
228:层间介电层
1000:第一类型环绕式栅极晶体管
2000:第二类型环绕式栅极晶体管
1100:第一标准单元
1200:第二标准单元
202N:公共N型掺杂区
1000N:N型第一类型环绕式栅极晶体管
1000P:P型第一类型环绕式栅极晶体管
2000N:N型第二类型环绕式栅极晶体管
2000P:P型第二类型环绕式栅极晶体管
C1:第一单元高度
C2:第二单元高度
具体实施方式
本公开提供许多不同的实施例或范例以实施本案的不同特征。以下的公开内容叙述各个构件及其排列方式的特定实施例，以简化说明。当然，这些特定的范例并非用以限定。举例来说，若是本公开叙述了一第一特征形成于一第二特征之上或上方，即表示其可能包含上述第一特征与上述第二特征是直接接触的实施例，亦可能包含了有附加特征形成于上述第一特征与上述第二特征之间，而使上述第一特征与第二特征可能未直接接触的实施例。另外，以下本公开不同实施例可能重复使用相同的参考符号及/或标记。这些重复为了简化与清楚的目的，并非用以限定所讨论的不同实施例及/或结构之间有特定的关系。
此外，其与空间相关用词。例如“在…下方”、“下方”、“较低的”、“上方”、“较高的”及类似的用词，为了便于描述图示中一个元件或特征与另一个(些)元件或特征之间的关系。除了在附图中示出的方位外，这些空间相关用词意欲包含使用中或操作中的装置的不同方位。除此之外，设备可能被转向不同方位(旋转90度或其他方位)，则在此使用的空间相关词也可依此相同解释。
此外，当数字或数字范围以“约”、“近似”等描述时，该术语旨在涵盖包括所述数量的合理范围内的数量，例如+/-10％内的数值或本技术领域中技术人员理解的其他数值。举例来说，术语“约5nm”包括4.5nm至5.5nm的尺寸范围。
本公开关于GAA晶体管，尤其是用于高速和低漏电应用的GAA晶体管。通常来说，即使当纳米线GAA晶体管和纳米片GAA晶体管皆形成在工件上时，在纳米线GAA晶体管和纳米片GAA晶体管的通道区上方也形成相同的栅极介电层。这些公知方法可能无法达到理想的装置区分准位(levels of device differentiation)来同时满足高速应用和低漏电应用的要求。根据本公开实施例的半导体装置包括具有纳米片通道构件和薄栅极介电层的第一类型GAA晶体管和具有纳米线通道构件和厚栅极介电层的第二类型GAA晶体管。薄栅极介电层增强了第一类型GAA晶体管的效能(在速度和驱动电流方面)，而厚栅极介电层增强了第二类型GAA晶体管的控制并降低了功率消耗。另外，不同的栅极介电层厚度也提供了形成不同阈值电压的GAA晶体管的手段。这是理想的，因为现代IC装置需要多阈值布置以平衡功率和效能。
图1显示了根据本公开实施例的用于制造半导体装置的方法100的流程图。下面将结合图2至图8、图9A、图9B以及图10描述图1，其是根据图1中的方法100在半导体装置被制造在工件上之前的各整工艺站点的工件的局部剖面图。在整个本公开中，为了便于参考，工件和半导体装置可以互换地指代，因为在工艺结束时工件将变成半导体装置，并且可以共享相同的附图标记。可以在方法100之前、之间以及之后提供额外步骤，并且对于方法100的其他实施例，可以移动、替换或移除所述的一些步骤。可以在图2至图8、图9A、图9B以及图10所示的半导体装置中加入额外特征，并且在半导体装置的其他实施例中可以替换、修改或移除下面描述的一些特征。
现在参照图1和图2，方法100包括操作102，其中多个交替半导体层2040在工件200中的基板202的第一区10和第二区20上方。在一些实施例中，基板202包括硅。替代地或附加地，基板202包括另一元素半导体，例如锗；化合物半导体，例如碳化硅、砷化镓、磷化镓、磷化铟、砷化铟及/或锑化铟；合金半导体，例如硅锗(SiGe)、磷砷化镓(GaAsP)、砷化铝铟(AlInAs)、砷化铝镓(AlGaAs)、砷化镓铟(GaInAs)、磷化镓铟(GaInP)及/或磷砷化镓铟(GaInAsP)；或其组合。在一些实施例中，基板202包括一或多种III-V族材料、一或多种II-IV族材料或其组合。在一些实施例中，基板202是绝缘体上半导体基板，例如绝缘体上硅(silicon-on-insulator；SOI)基板、绝缘体上硅锗(silicon germanium-on-insulator；SGOI)基板或绝缘体上锗(germanium-on-insulator；GOI)基板。绝缘体上半导体基板可以通过氧注入(separation by implantation of oxygen；SIMOX)、晶片键结(waferbonding)及/或其他合适方法使用分离来制造。基板202可以包括根据半导体装置200的设计要求配置的各种掺杂区(或井)，例如P型掺杂区(或P井)2021P和2022P以及N型掺杂区(或N井)2021N和2022N，或其组合。P型掺杂区，例如2021P和2022P，包括P型掺杂剂，例如硼、铟、其他P型掺杂剂或其组合。N型掺杂区，例如2021N和2022N，包括N型掺杂剂，例如磷、砷、其他N型掺杂剂或其组合。在一些实施例中，基板202包括由P型掺杂物和N型掺杂物的组合形成的掺杂区。各种掺杂区可直接形成在基板202上及/或基板202中，来提供P井结构、N井结构、双井结构、凸起结构或其组合。可以执行离子注入工艺、扩散工艺及/或其他合适掺杂工艺以形成各种掺杂区。在一些实施例中，在N型井上方形成P型GAA装置，并且在P型井上方形成N型GAA装置。取决于设计要求，就掺杂物或掺杂浓度而言，第一区10中的N型掺杂区(N井)2021N可以不同于第二区域20中的N型掺杂区(N井)2022N。相似地，第一区10中的P型掺杂区(P井)2021P可以不同于第二区20中的P型掺杂区(P井)2022P。
第一区10和第二区20是包括对不同应用满足不同要求或实现的晶体管的装置区。在一些实施例中，第一区10可以是用于高驱动电流(Ion)和高开关速度应用的区域，其中功率消耗和漏电较少顾虑。举例来说，第一区10可以是逻辑装置区，其包括反相器、NAND闸、NOR闸、AND闸、OR闸或触发器装置。在一些实施例中，可以在第一区10中制造多个GAA晶体管以形成用于高驱动电流(Ion)和高开关速度应用的标准单元。在其他实施例中，第二区20可以是用于低漏电和省电(power-conserving)应用的区域，其中对效能和速度的顾虑较小。在一些实施例中，第二区20也可以是逻辑装置区，其包括反相器、NAND闸、NOR闸、AND闸、OR闸或触发器装置。相似地，可以在第一区10中制造多个GAA晶体管以形成用于低漏电和省能应用的标准单元。在一些实施例中，在第一区10和第二区20中包括标准单元的IC装置可以具有不同的操作模式。举例来说，IC装置可以具有省电模式和效能模式。在计算功率需求低的省电模式下，第一区10中的高效能晶体管可以处于待机或睡眠状态，而第二区20中的省电晶体管承担操作。在计算功率要求高的效能模式下，可以使第一区10中的高效能晶体管运作以提高速度。
在图2所示的实施例中，多个交替半导体层2040包括被多个第二半导体层204B插入(interleaved)的多个第一半导体层204A。意即两个相邻的第一半导体层204A将一个第二半导体层204B夹设在中间。多个第一半导体层204A由第一半导体材料形成，并且多个第二半导体层204B由与第一半导体材料不同的第二半导体材料形成。在一些实施例中，第一半导体材料是硅(Si)或大抵由硅组成，并且第二半导体材料是锗(Ge)或大抵由锗组成。在一些其他实施例中，第一半导体材料是硅(Si)或大抵由硅组成，并且第二半导体材料包括具有锗含量在约15％至约40％之间的硅锗(SiGe)。可以通过交替地沉积或外延成长多个第一半导体层204A和多个第二半导体层204B来形成多个交替半导体层2040。在图2所示的实施例中，多个第一半导体层204A中的每一个包括第一厚度L1，并且多个第二半导体层204B中的每一个包括第二厚度L2。在一些情况下，第一厚度L1与第二厚度L2的比率(L1/L2)在约0.5和约2.0之间。在一些实施例中，在将多个交替半导体层2040图案化为鳍片结构(鳍状有源区)之后，可以选择性地移除通道区中的多个第二半导体层204B的一部分，以释放由多个第一半导体层204A形成的通道构件。就这一点来说，第二半导体层204B用作牺牲半导体层，并且可以这样称呼。
现在参照图1和图3，方法100包括操作104，其中在第一区10中形成第一鳍片结构205A，并且在第二区20中形成第二鳍片结构205B。在图3所示的一些实施例中，可以图案化第一区10上方的多个交替半导体层2040，以形成第一鳍片结构(或第一鳍状有源区)205A，并且图案化在第二区20上方的多个交替半导体层2040，以形成第二鳍片结构(或第二鳍状有源区)205B。在操作104中，可以通过使用合适工艺(例如光刻和蚀刻工艺)来图案化第一鳍片结构205A和第二鳍片结构205B。在一些实施例中，使用干式蚀刻或等离子体工艺从个别的交替半导体层蚀刻第一鳍片结构205A和第二鳍片结构205B。在一些其他实施例中，第一鳍片结构205A和第二鳍片结构205B可以通过双重图案化光刻(double-patterninglithography；DPL)工艺，四重图案化光刻(quadruple-patterning lithography；QPL)工艺或多重图案光刻(multiple-patterning lithography；MPL)工艺形成。通常来说，DPL、QPL以及MPL工艺将光刻和自我对准工艺结合在一起，从而允许创建间距小于使用单一、直接光刻工艺可获得的间距的图案。如图3所示，第一鳍片结构205A可以从个别的掺杂区延伸，包括在第一区10中的P型掺杂区2021P和N型掺杂区2021N，并且第二鳍片结构205B可以从个别的掺杂区延伸，包括在第二区20中的P型掺杂区2022P和N型掺杂区2022N。如图3所示，在一些实施例中，在操作104中也蚀刻基板202。
第一鳍片结构205A和第二鳍片结构205B可以沿着Y方向具有不同的宽度，栅极堆叠沿着Y方向延伸。在本公开实施例中，每一个第一鳍片结构205A具有第一宽度W1，并且每一个第二鳍片结构205B具有第二宽度W2。为了使将由第一鳍片结构205A形成的通道构件适合用于高驱动电流/低阈值电压的应用，以及使将由第二鳍片结构205B形成的通道构件适合用于低驱动电流/高阈值电压的应用，第二宽度W2小于第一宽度W1。第一宽度W1与第二宽度W2的比率基于驱动电流和阈值电压的不同要求以及相关的考虑来选择。给定相同的通道构件厚度，通道的剖面面积与通道构件的宽度成正比。就阈值电压而言，通道构件的宽度大抵上与阈值电压成反比。意即，通道宽度增加20％可能会赚换成阈值电压减少约20％。尽管通道构件宽度的增加可以带来驱动电流和低阈值电压的益处，但是通道构件的宽度并非没有成本，因为这可能导致半导体装置的尺寸增大并且基板上的装置数量减少。另外，很难在设计中自由包含通道构件宽度增加。已经观察到，除非通道宽度差异小于约20％，否则设计公司不愿意增加装置尺寸并解决所有麻烦。考虑到前面描述，在本公开实施例中，第一宽度W1与第二宽度W2的比率在约1.2和约6之间，包括在约1.4和约4之间。
现在参照图4，在一些实施例中，通过在相邻鳍片结构之间的凹陷中沉积介电材料，接着将所沉积的介电材料拉回，以暴露多个交替半导体层2040，来形成介电隔离特征206。介电隔离特征206也可以称为浅沟槽隔离(STI)特征206。
参照图1和图5，方法100包括操作106，其中在第一鳍片结构205A的第一通道区209A和第二鳍片结构205B的第二通道区209B上方形成冗余栅极堆叠207。就这一点来说，图5显示了跨越第一通道区209A和第二通道区209B的第一区10和第二区20中的工件200的局部剖面图。在一些实施例中，采用栅极后工艺流程(gate-last process flow)，并且首先形成冗余栅极堆叠207作为用于后续形成的金属栅极堆叠208(在图9A中显示；或者用于在图9B中所示的N型栅极堆叠211-1和P型栅极堆叠211-2)的占位符(placeholder)。因为金属栅极堆叠208在稍后的工艺中形成以替换冗余栅极堆叠207，所以可以避免各种工艺对金属栅极堆叠208的损坏。在一些实施方式中，冗余栅极堆叠207包括冗余栅极介电层。冗余栅极堆叠207可以由多晶硅形成，并且冗余栅极介电层可以由氧化硅或掺杂氮的氧化硅形成。
在一些实施例中，一或多个栅极间隔物(或栅极间隔物层)220(如图10所示)形成在冗余栅极堆叠207上方。一或多个栅极间隔物220设置在冗余栅极堆叠207的表面(或侧壁)上方并在其旁边。一或多个栅极间隔物220可以在金属栅极堆叠208(在栅极替换工艺之后)和相邻的源极/漏极接点之间提供隔离，并且还可以在稍后移除冗余栅极堆叠207时保护与冗余栅极堆叠207相邻的结构。在一些实施例中，一个或多个介电冗余栅极堆叠218(在图10中显示)可以随着冗余栅极堆叠207形成，以将有源区分开成多个片段或将半导体装置的单元分开。在一些实施例中，一或多个栅极间隔物220中的每一个可以包括择自氧化硅、氮氧化硅、氮化硅、碳氮氧化硅、介电常数低于4的低k介电材料或其组合的一或多种介电材料。
在一些实施例中，图5中的冗余栅极堆叠207可以经历冗余栅极切割工艺，从而得到栅极端介电特征(gate end dielectric feature)，例如图5中所示的栅极端介电特征210。尽管在图5中仅将冗余栅极堆叠207显示为在冗余栅极切割工艺中分成多于一个片段，但在栅极替换工艺之后，栅极端介电特征210可以用作分离特征以将金属栅极堆叠208分成多个片段。
参照图1，方法100包括操作108，其中源极/漏极特征222形成相邻于冗余栅极堆叠207。尽管图10主要用于显示在操作120中可能对工件200执行的其他工艺，但它显示了在方法100的操作108中形成的源极/漏极特征222的相对位置和结构。在一些实施例中，图5中的第一鳍片结构205A和第二鳍片结构205B的源极/漏极区被凹陷以暴露第一鳍片结构205A和第二鳍片结构205B的通道区的侧壁。在一些实施例中，第一鳍片结构205A和第二鳍片结构205B的多个第二半导体层204B可以被部分且选择性地蚀刻以形成凹陷。接着可以将间隔物介电材料沉积在工件200上，包括在凹陷内。接着将沉积的间隔物介电材料拉回以在凹陷中形成内部间隔物，从而暴露出第一鳍片结构205A和第二鳍片结构205B的多个第一半导体层204A。意即第一鳍片结构205A和第二鳍片结构205B的多个第一半导体层204A在沿着通道的长度的任一端被内部间隔物部分地分开。接着，可以在基板202和多个第一半导体层204A上的源极/漏极区中外延形成N型半导体材料，例如磷掺杂的硅(SiP)、碳掺杂的硅(SiC)、砷掺杂的硅(SiAs)、硅(Si)或其组合，或P型半导体材料(例如硅锗(SiGe)、碳掺杂的硅锗(SiGeC)、锗(Ge)或其组合)，以形成源极/漏极特征222。尽管未单独显示，但是源极/漏极特征222可以包括由上述N型半导体材料形成的N型源极/漏极特征和由上述P型半导体材料形成的P型源极/漏极特征。可以使用光刻技术和一个以上的掩模顺序且个别地形成N型源极/漏极特征和P型源极/漏极特征。举例来说，可以先在通过光刻图形化硬掩模覆盖P型源极/漏极区的同时形成N型源极/漏极特征，并接着在通过光刻图形化硬掩模覆盖N型源极/漏极区的同时形成P型源极/漏极特征。在一些其他实施例中，可以首先形成P型源极/漏极特征。
参照图1，方法100包括操作110，其中在基板202上方形成介电层。介电层可以被称为层间介电(interlayer dielectric；ILD)层。在一些实施例中，介电层可以包括氧化硅、四乙氧基硅烷(tetraethylorthosilicate；TEOS)、未掺杂的硅酸盐玻璃或掺杂的氧化硅，例如硼磷硅酸盐玻璃(borophosphosilicate glass；BPSG)、熔融石英玻璃(fused silicaglass；FSG)、磷硅酸盐玻璃(phosphosilicate glass；PSG)、硼掺杂硅玻璃(boron dopedsilicon glass；BSG)、其他合适介电材料或其组合。在一些实施方案中，可以使用化学气相沉积(chemical vapor deposition；CVD)、流动式CVD(flowable CVD；FCVD)或旋涂玻璃在工件200上方形成介电层。在一些情况下，操作110可以进一步包括平坦化工艺，以在进一步的工艺之前平坦化介电层的顶表面。
参照图1和图6，方法100包括操作112，其中第一鳍片结构205A的第一通道区209A中的第一通道构件214-1和第二鳍片结构205B的第二通道区209B中的第二通道构件214-2被释放。在一些实施例中，在操作112中，移除第一鳍片结构205A的第一通道区209A和第二鳍片结构205B的第二通道区209B中的冗余栅极堆叠207以暴露第一通道区209A和第二通道区209B。接着，对暴露的第一通道区209A和第二通道区209B进行选择性蚀刻工艺，以选择性地移除第一鳍片结构205A和第二鳍片结构205B中的多个第二半导体层204B。在移除多个第二半导体层204B之后，释放第一鳍片结构205A中的第一半导体层204A以成为第一通道构件214-1，并且释放第二鳍片结构205B中的第一半导体层204A以成为第二通道构件214-2。在一些实施方式中，多个第二半导体层204B由硅锗形成。在那些实施例中，多个第二半导体层204B可以首先被氧化剂(例如臭氧)氧化，并接着通过对硅锗氧化物具有选择性的选择性蚀刻工艺移除。第一通道构件214-1和第二通道构件214-2基于沿着Z方向的每一个第一通道构件214-1和每一个第二通道构件214-2的中线共享间距P。在一些情况下，间距P可以在约10nm和约20nm之间。第一通道构件214-1和第二通道构件214-2中的每一个具有沿着Z方向的构件厚度MT。在一些情况下，构件厚度MT可以在约4nm和约8nm之间。相邻的第一通道构件214-1或相邻的第二通道构件214-2的任何两者由间隔S分开。在一些情况下，间隔S可以在约6nm和约15nm之间。间距P也可以被定义为构件厚度MT和间隔S的总和。
第一通道构件214-1可以继承第一鳍片结构205A的第一宽度W1，并且第二通道构件214-2可以继承第二鳍片结构205B的第二宽度W2。当第一宽度W1与第二宽度W2的比率在约1.2和约10.0之间时，每一个第一通道构件214-1可具有片状外观，而每一个第二通道构件214-2可具有线状外观。因此，第一通道构件214-1可以被称为纳米片，并且第二通道构件214-2可以被称为纳米线。在一些情况下，第一通道构件214-1和第二通道构件214-2可以被统称为纳米结构或纳米-结构。
参照图1和图7，方法100可以包括操作114，其中在第一通道构件214-1和第二通道构件214-2上方形成第一栅极介电层216-1。在一些实施例中，第一栅极介电层216-1可以包括界面层和高k介电层。在那些实施例中的一些中，界面层可以包括未掺杂或掺杂有氮的氧化硅。在一些实施例中，高k介电层可以包括一或多种金属氧化物，例如一氧化锆(ZrO)、氧化钇(Y2O3)、五氧化二镧(La2O5)、五氧化二钆(Gd2O5)、二氧化钛(TiO2)、五氧化二钽(Ta2O5)、氧化铪铒(HfErO)、氧化铪镧(HfLaO)、氧化铪钇(HfYO)、氧化铪钆(HfGdO)、氧化铪铝(HfAlO)、氧化铪锆(HfZrO)、氧化铪钛(HfTiO)、氧化铪钽(HfTaO)、氧化锶钛(SrTiO)或其组合。高k介电层的介电常数大于9，包括大于13。可以使用原子层沉积(atomic layerdeposition；ALD)、等离子体辅助原子层沉积(plasma-enhanced atomic layerdeposition；PEALD)或其他合适方法来沉积第一栅极介电层216-1。在一些实施例中，第一栅极介电层216-1具有第一栅极介电层厚度GL1。在一些情况下，第一栅极介电层厚度GL1在约
Figure BDA0002682549270000131
和约
Figure BDA0002682549270000132
之间。
参照图1和图8，方法100可以包括操作116，其中在第二通道区209B中的第二通道构件214-2上方形成第二栅极介电层216-2。在一些实施例中，可以使用光刻工艺来遮蔽第一通道区209A中的第一通道构件214-1，并且可以在第二通道构件214-2上方的第一栅极介电层216-1之上沉积额外的栅极介电层，以形成第二栅极介电层216-2。举例来说，可以通过合适工艺(例如旋转涂布(spin-on coating))将介电填充材料沉积在第一区10和第二区20上方。接着将沉积的介电填充材料平坦化。之后，可以在第一区10和第二区20上方形成一或多个硬掩模层。在一些实施例中，一或多个硬掩模层可以由半导体氧化物(例如氧化硅)或半导体氮化物(例如氮化硅)形成，并且可以使用化学气相沉积(CVD)、流动式CVD(FCVD)、旋转涂布或其他合适技术来沉积。之后，使用CVD，FCVD，旋涂或其他合适技术在一或多个硬掩模层上沉积光刻胶层。接着将光刻胶层暴露于从图案化掩模反射或穿过图案化掩模的辐射。在经受曝光后烘烤之后，曝光的光刻胶层可以经历化学变化，其允许光刻胶层的曝光或未曝光部分被显影剂去除以形成图案化的光刻胶层。在操作116中，图案化的光刻胶层可以在覆盖第一区10上方的一或多个硬掩模层的同时，暴露第二区20上方的一或多个硬掩模层。接着可以将图案化的光刻胶层用作蚀刻掩模，以图案化一或多个硬掩模层，来形成图案化的硬掩模。图案化的硬掩模覆盖第一区10并暴露第二区20。接着可以将图案化的硬掩模用作蚀刻掩模，以移除第二通道区209B上方的介电填充材料，来暴露第二区20中的第一栅极介电层216-1。在一些实施例中，额外的栅极介电层可以包括高k介电材料，例如一氧化锆(ZrO)、氧化钇(Y2O3)、五氧化二镧(La2O5)、五氧化二钆(Gd2O5)、二氧化钛(TiO2)、五氧化二钽(Ta2O5)、氧化铪铒(HfErO)、氧化铪镧(HfLaO)、氧化铪钇(HfYO)、氧化铪钆(HfGdO)、氧化铪铝(HfAlO)、氧化铪锆(HfZrO)、氧化铪钛(HfTiO)、氧化铪钽(HfTaO)、氧化锶钛(SrTiO)或其组合。额外的栅极介电层堆叠在第一栅极介电层216-1上方以形成第二栅极介电层216-2。因此，第二栅极介电层216-2具有大于第一栅极介电层厚度GL1的第二栅极介电层厚度GL2。值得注意的是，第二栅极介电层厚度GL2受到第二栅极介电层厚度GL2是否留有足够的空间以形成下面将要描述的金属栅极堆叠的限制。在一些情况下，第二栅极介电层厚度GL2在约
Figure BDA0002682549270000141
和约
Figure BDA0002682549270000142
之间。在一些实施例中，第二栅极介电层厚度GL2与第一栅极介电层厚度GL1的比率(GL2/GL1)可以在约1.05和约1.3之间。在一些情况下，第二栅极介电层厚度GL2和第一栅极介电层厚度GL1之间的差值可以在
Figure BDA0002682549270000143
和
Figure BDA0002682549270000144
之间。在一些实施例中，第一栅极介电层216-1和第二栅极介电层216-2在成分上可以相似，而第二栅极介电层216-2的第二栅极介电层厚度GL2包括比第一栅极介电层216-1的第一栅极介电层厚度GL1更厚的高k介电层。由于较厚的第二栅极电介质层216-2，由于更好的DIBL性能，将在第二区域20中形成的GAA晶体管具有较高的阈值电压，并且适合于要求低泄漏的应用。由于第二栅极介电层216-2较厚，将在第二区20中形成的GAA晶体管由于更好的漏极引发能带降低(drain-induced barrier lowering；DIBL)效能具有更高的阈值电压，并且适合于要求低漏电的应用。
参照图1、图9A以及图9B，方法100包括操作118，其中在第一区10中的第一通道区209A和第二区20中的第二通道区209B上方形成金属栅极堆叠。在图9A所示的一些实施例中，可以在第一通道区209A中的第一通道构件214-1上方和第二通道区209B中的第二通道构件214-2上方形成公共的金属栅极堆叠208。公共的金属栅极堆叠208可以包括功函数金属层和填充金属层。功函数金属层的材料的选择可以由第一区10或第二区20中的GAA晶体管所期望的总体阈值电压来确定。示例性的p型功函数金属包括氮化钛(TiN)、氮化钽(TaN)、钌(Ru)、钼(Mo)、铝(Al)、氮化钨(WN)、硅化锆(ZrSi2)、硅化钼(MoSi2)、硅化钽(TaSi2)、硅化镍(NiSi2)及/或其他合适P型功函数材料。合适的n型功函数金属包括钛(Ti)、银(Ag)、钽铝(TaAl)、碳化钽铝(TaAlC)、氮化钛铝(TiAlN)、碳化钽(TaC)、氮碳化钽(TaCN)、碳化钽硅(TaSiN)、锰(Mn)、锆(Zr)及/或其他合适N型功函数材料。此外，在功函数金属层上方形成的填充金属层可以包括铜(Cu)、钌(Ru)、钨(W)、铝(Al)、钴(Co)及/或其他合适材料。可以通过ALD、CVD、物理气相沉积(physical vapor deposition；PVD)、电镀及/或其他合适工艺来形成填充金属层。在一些实施例中，可以执行化学机械研磨(Chemical-MechanicalPolishing；CMP)工艺以将公共的金属栅极堆叠208的高度减小到期望准位。
替代地，在图9B所示的实施例中，代替公共的金属栅极堆叠208，在P型井(P型掺杂区2021P和2022P)上方的第一通道构件214-1和第二通道构件214-2上方形成N型金属栅极堆叠211-1，并且在N型井(N型掺杂区2021N和2022N)上方的第一通道构件214-1和第二通道构件214-2上方形成P型金属栅极堆叠211-2。在这些替代实施例中，N型金属栅极堆叠211-1可以包括由N型功函数金属层形成的第一功函数金属堆叠，并且P型金属栅极堆叠211-2可以包括由P型功函数金属层形成的第二功函数金属堆叠。在一些实施例中，当个别地在N型金属栅极堆叠211-1中形成N型功函数金属堆叠和在P型金属栅极堆叠211-2中形成P型功函数金属堆叠时，可以个别地遮蔽N井和P井。在一些实施例中，N型金属栅极堆叠211-1和P型金属栅极堆叠211-2之间的差异大抵在于不同的功函数金属堆叠，并且可以包括公共的金属填充层。
参照图1和图10，方法100包括操作120，执行进一步的工艺。这种进一步的工艺可以包括在公共的金属栅极堆叠208(或N型金属栅极堆叠211-1和P型金属栅极堆叠211-2)上方的栅极顶部硬掩模217的形成、硅化物层224的形成、源极/漏极接点226的形成以及另一个ILD层228的形成。在一些实施例中，源极/漏极接点226可以包括选自钛(Ti)、氮化钛(TiN)、镍(Ni)、钼(Mo)、铂(Pt)、钴(Co)、钌(Ru)、钨(W)、氮化钽(TaN)、铜(Cu)或其组合的一或多个金属层。图10显示了在第一区10中的第一类型GAA晶体管1000和在第二区20中的第二类型GAA晶体管2000。取决于井的类型和功函数金属堆叠的配置，第一类型GAA晶体管1000可以是N型或P型。相似地，第二类型GAA晶体管2000可以是N型或P型。
现在参照图11和图12。图11显示了具有两个相邻标准单元的半导体装置200的俯视图，其包括在第一区10中的第一标准单元1100和在第二区20中的第二标准单元1200。图12显示了图11中的半导体装置在Y方向上的剖面A-A’的局部剖面图。在图11所示的实施例中，第一标准单元1100和第二标准单元1200可以沿着栅极方向(Y方向)彼此邻接，并且被一或多个栅极端介电特征210分开。在图11中未显示的其他实施例中，第一标准单元1100和第二标准单元1200可以沿着鳍片结构方向(X方向)彼此邻接，并且可以被一或多个介电冗余栅极堆叠、填充有层间介电层的间隙或一或多个栅极永久关闭的晶体管分开。在一些情况下，第一标准单元1100包括具有第一通道构件214-1和第一栅极介电层216-1的第一类型GAA晶体管，并且第二标准单元1200包括具有第二通道构件214-2和第二栅极介电层216-2的第二类型GAA晶体管。如上面所述，每一个第一通道构件214-1比每一个第二通道构件214-2宽；并且第二栅极介电层216-2比第一栅极介电层216-1厚。第一标准单元1100中的第一类型GAA晶体管可以用于高效能应用，并且第二标准单元1200中的第二类型GAA晶体管可以用于低功耗应用。在多阈值方案的省电模式下，可以在第一标准单元1100进入睡眠或待机状态时激活第二标准单元1200，从而降低功耗。在多阈值方案的效能模式中，第一标准单元1100可以被激活以在开关速度和驱动电流准位方面提高效能。
在一些实施例中，第一标准单元1100和第二标准单元1200可以共享公共的N井或公共的P井。参照图11。在一些实施例中，第一标准单元1100包括两组第一通道构件214-1，每一组由一个第一鳍片结构205A形成。一组第一通道部件214-1设置在P型掺杂区(p井)2021P上方，并且是用于N型第一类型GAA晶体管1000N的通道构件。另一组第一通道部件214-1设置在公共N型掺杂区(N井)202N上方，并且是用于P型第一类型GAA晶体管1000P的通道构件。相似地，在这些实施例中，第二标准单元1200包括两组第二通道构件214-2，每一组由一个第二鳍片结构205B形成。一组第二通道构件214-2设置在P型掺杂区(p井)2022P上方，并且是用于N型第二类型GAA晶体管2000N的通道构件。另一组第二通道构件214-2设置在公共N型掺杂区(N井)202N上方，并且是用于P型第二类型GAA晶体管2000P的通道构件。因此，图11中的第一标准单元1100和第二标准单元1200共享公共N型掺杂区(公共N井)202N。图12中也显示了这种配置。如图12所示，关于设置在STI上方的结构，第一标准单元1100通过两个栅极端介电特征210与第二标准单元1200分开。尽管图11和图12显示了用于每一个标准单元的两组通道构件，并且两个标准单元共享公共N井，但是本公开不限于此。本公开包括每一个标准单元包括多于两组的通道构件，并且两个相邻的标准单元可以共享公共的P井而不是公共的N井的实施例。
仍参照图11和图12。在一些实施例中，由于第二通道构件214-2较窄，所以第二标准单元1200沿着Y方向具有较小的单元高度。在图11和图12中，第一标准单元1100具有第一单元高度C1，并且第二标准单元1200具有第二单元高度C2。如图12所示，标准单元(例如第一标准单元1100和第二标准单元1200)的高度大抵由介电隔离特征206的宽度和通道构件的宽度(例如第一宽度W1和第二宽度W2)组成。根据经验，通道构件的宽度大约占单元高度的一半。意即通道构件的宽度的增加量的一半将转化为单元高度的增加。如上面所述，在本公开实施例中，第一宽度W1与第二宽度W2的比率在约1.2和约6之间，包括在约1.4和约4之间。因此，在那些实施例中，第一单元高度C1与第二单元高度C2的比率在约1.1和约3.5之间，包括在约1.2和约2.5之间。
基于以上讨论，本公开提供了公知半导体装置之上的优点。然而，应理解其他实施例可以提供额外的优点，并且在此不必公开所有优点，并且对于所有实施例都不需特定优点。本公开提出了一种半导体装置，其包括用于高效能应用的第一类型GAA晶体管和用于低功耗应用的第二类型GAA晶体管。两者均由相同的交替半导体层堆叠形成，第一类型GAA晶体管具有较宽的通道构件和较薄的栅极介电层，并且第二类型GAA晶体管具有较窄的通道构件和较厚的栅极介电层。第一类型GAA晶体管提供高速和高驱动电流，并且第二类型GAA晶体管提供低漏电和低功耗。
本公开提供了半导体装置的实施方式及其形成方法。在一个实施例中，提供了一种半导体装置。半导体装置包括第一环绕式栅极(GAA)晶体管和第二环绕式栅极晶体管。第一环绕式栅极(GAA)晶体管包括多个第一通道构件和在第一通道构件上方的第一栅极介电层。第二环绕式栅极晶体管包括多个第二通道构件和在第二通道构件上方的第二栅极介电层。第一通道构件的每一个的第一宽度(W1)大于第二通道构件的每一个的第二宽度(W2)，并且第一栅极介电层的第一厚度(GL1)小于第二栅极介电层的第二厚度(GL2)。
在一些实施例中，第一环绕式栅极晶体管用于高驱动电流应用，并且第二环绕式栅极晶体管用于低漏电应用。在一些实施例中，第一宽度(W1)与第二宽度(W2)的比率在约1.2和约10.0之间。在一些实施例中，第二厚度(GL2)和第一厚度(GL1)之间的差值在约
Figure BDA0002682549270000181
和约
Figure BDA0002682549270000182
之间。在一些情况下，第一宽度(W1)在约12nm和约30nm之间，并且第二宽度(W2)在约4nm和约15nm之间。
在另一个实施例中，提供了一种半导体装置。半导体装置包括基板，包括第一区和第二区；第一N型环绕式栅极(GAA)晶体管和第一P型环绕式栅极晶体管，在第一区中，其中第一N型环绕式栅极晶体管和第一P型环绕式栅极晶体管的每一个包括多个第一通道构件和在第一通道构件上方的第一栅极介电层；以及第二N型环绕式栅极晶体管和第二P型环绕式栅极晶体管，在第二区中，其中第二N型环绕式栅极晶体管和第二P型环绕式栅极晶体管的每一个包括多个第二通道构件和在第二通道构件上方的第二栅极介电层。第一通道构件的每一个的第一宽度(W1)大于第二通道构件的每一个的第二宽度(W2)。第一栅极介电层的第一厚度(GL1)小于第二栅极介电层的第二厚度(GL2)。
在一些实施例中，第一区邻接第二区。在一些实施例中，第一区包括第一区高度(C1)，并且第二区包括第二区高度(C2)，其中第一区高度(C1)与第二区高度(C2)的比率在约1.1和约2.0之间。在一些情况下，第一区中的第一P型环绕式栅极晶体管和第二区中的第二环绕式栅极晶体管设置在N型井上方。在一些实施例中，第一N型环绕式栅极晶体管包括在第一通道构件上方的第一功函数堆叠，第一P型环绕式栅极晶体管包括在第一通道构件上方的第二功函数堆叠，并且第一功函数堆叠不同于第二功函数堆叠。在一些情况下，第一区用于高驱动电流应用，并且第二区用于低漏电应用。在一些情况下，第一宽度(W1)与第二宽度(W2)的比率在约1.2和约10.0之间。在一些实施例中，第二厚度(GL2)和第一厚度(GL1)之间的差值在约
Figure BDA0002682549270000183
和约
Figure BDA0002682549270000184
之间。在一些实施例中，述第一宽度(W1)在约12nm和约30nm之间，并且第二宽度(W2)在约4nm和约15nm之间。
在另一个实施例中，提供了一种半导体装置的形成方法。半导体装置的形成方法包括在基板的第一区和第二区上方形成多个交替半导体层，交替半导体层包括被多个第二半导体层插入的多个第一半导体层；图案化在第一区上方的交替半导体层，以形成具有第一宽度(W1)的第一有源区；图案化在第二区上方的交替半导体层，以形成具有第二宽度(W2)的第二有源区，第二宽度(W2)小于第一宽度(W1)；从第二半导体层中释放第一半导体层，以在第一有源区的第一通道区中形成多个第一通道构件，并且在第二有源区的第二通道区中形成多个第二通道构件；在第一通道构件上方形成第一栅极介电层，第一栅极介电层具有第一厚度(GL1)；以及在第二通道构件上方形成第二栅极介电层，第二栅极介电层具有大于第一厚度(GL1)的第二厚度(GL2)。
在一些实施例中，第一宽度(W1)与第二宽度(W2)的比率在约1.2和约10.0之间。在一些实施例中，第二厚度(GL2)和第一厚度(GL1)之间的差值在约
Figure BDA0002682549270000191
和约
Figure BDA0002682549270000192
之间。在一些情况下，在第一通道构件上方形成第一栅极介电层的步骤包括在第二通道构件上方同时形成第一栅极介电层。在一些实施例中，形成第二栅极介电层的步骤包括在设置在第二通道构件上方的第一栅极介电层上方形成额外栅极介电层。在一些情况下，形成第二栅极介电层的步骤包括遮蔽在第一沟道构件上方的第一栅极介电层。
前述内文概述了许多实施例的特征，使本技术领域中技术人员可以从各个方面更佳地了解本公开。本技术领域中技术人员应可理解，且可轻易地以本公开为基础来设计或修饰其他工艺及结构，并以此达到相同的目的及/或达到与在此介绍的实施例等相同的优点。本技术领域中技术人员也应了解这些相等的结构并未背离本公开的发明精神与范围。举例来说，通过对位元线导体和字元线导体实现不同的厚度，可以实现导体的不同电阻。然而，也可以使用改变金属导体的电阻的其他技术。

Claims (1)

1.一种半导体装置，包括：
一第一环绕式栅极晶体管，包括：
多个第一通道构件，以及
一第一栅极介电层，在上述第一通道构件上方；以及
一第二环绕式栅极晶体管，包括：
多个第二通道构件，以及
一第二栅极介电层，在上述第二通道构件上方，
其中上述第一通道构件的每一个的一第一宽度大于上述第二通道构件的每一个的一第二宽度，
其中上述第一栅极介电层的一第一厚度小于上述第二栅极介电层的一第二厚度。
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