CN113964123A - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN113964123A
CN113964123A CN202110782521.7A CN202110782521A CN113964123A CN 113964123 A CN113964123 A CN 113964123A CN 202110782521 A CN202110782521 A CN 202110782521A CN 113964123 A CN113964123 A CN 113964123A
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substrate
semiconductor
gate
depth
stack
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CN202110782521.7A
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Inventor
廖忠志
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种半导体装置及其制造方法。一示例半导体装置包括：一基板，包括多个顶部分，其中所述顶部分是由一隔离结构所隔离开；多个第一半导体层，位于一第一区域中的该基板的一第一顶部分之上；以及一第一栅极结构，包裹所述第一半导体层的每一者，并覆盖住延伸于该隔离结构的上方的该基板的该第一顶部分的一顶表面和多个侧壁。所述第一半导体层是堆叠起来并彼此分离，而所述第一半导体层的每一者皆具有一第一宽度。该第一栅极结构的一底表面是位于该基板的该顶表面的下方达一第一深度，而该第一深度至少为该第一宽度的一半。

Description

半导体装置
技术领域
本公开是关于一种半导体装置、一种集成电路及其形成方法。
背景技术
半导体集成电路(Integrated Circuit，亦称「IC」)产业已经历指数增长。三维及多栅极装置(Three-Dimensional and Multi-gate Device)已被引入以改善装置性能。这样的多栅极装置其中一种是纳米结构装置(Nanostructure Device)。纳米结构装置实质上是指具有包括分离的半导体通道(Semiconductor Channel)的通道区域(ChannelRegion)，以及形成在半导体通道上多于一侧(例如，围绕半导体通道)的栅极结构或其一部分的任何装置。在一些情况下，纳米结构装置也被称为纳米片装置(Nanosheet Device)、纳米线装置(Nanowire Device)、纳米环装置(Nanoring Device)、栅极包围装置(Gate-Surrounding Device)、环绕栅极(Gate-All-Around，GAA)装置，或是多通道桥接装置(Multi-Channel Bridge Device)。纳米结构晶体管与传统的互补金属氧化物半导体(Complementary Metal-Oxide-Semiconductor CMOS)的制程兼容，并且可以大幅地缩小装置尺寸。然而，纳米结构晶体管的制造却存在一些挑战。例如，由纳米结构制造的静态随机存取存储器(Static Random Access Memory，SRAM)单元会承受待机漏电(StandbyLeakage)的问题和临界电压不匹配(Threshold Voltage Mismatch)的问题。因此，实有必要对纳米结构装置来提出改进。
发明内容
在一些实施例中，本公开提出一种半导体装置，包括：一基板，包括多个顶部分(top portion)，其中所述顶部分是由一隔离结构所隔离开；多个第一半导体层，位于一第一区域中的该基板的一第一顶部分之上，其中所述第一半导体层是堆叠起来并彼此分离，而所述第一半导体层的每一者皆具有一第一宽度；以及一第一栅极结构，包裹所述第一半导体层的每一者，并覆盖住延伸于该隔离结构的上方的该基板的该第一顶部分的一顶表面和多个侧壁，其中该第一栅极结构的一底表面是位于该基板的该顶表面的下方达一第一深度，而该第一深度至少为该第一宽度的一半。
在一些实施例中，本公开提出一种集成电路，包括：一基板，包括一P型区域和一N型区域，其中该基板包括多个顶部分，而所述顶部分是由一隔离结构所隔离开；一第一半导体堆叠，设置于该基板的该P型区域之上；一第二半导体堆叠，设置于该基板的该N型区域之上，其中该第一半导体堆叠和该第二半导体堆叠的每一者皆包括多个半导体层，而所述半导体层是堆叠起来并彼此分离；一第一源/漏极(S/D)部件，形成于该基板的该P型区域之上；以及一第二源/漏极部件，形成于该基板的该N型区域之上，其中该第一源/漏极部件的一底表面是位于该基板的一顶表面的下方达一第一深度，该第二源/漏极部件的一底表面是位于该基板的该顶表面的下方达一第二深度，而该第二深度是小于该第一深度。
在一些实施例中，本公开提出一种形成集成电路的方法，包括：接收一基板，其中该基板包括一第一区域和一第二区域；于基板之上交替地生长出多个第一半导体层和多个第二半导体层，其中所述第一半导体层和所述第二半导体层包括不同半导体材料；蚀刻所述第一半导体层、所述第二半导体层，以及该基板的多个部分以形成一第一半导体堆叠和一第二半导体堆叠，其中该第一半导体堆叠于该第一区域中具有一第一宽度，该第二半导体堆叠于该第二区域中具有一第二宽度，该第二宽度是大于该第一宽度，而该第一半导体堆叠和该第二半导体堆叠的每一者皆包括所述第一半导体层、所述第二半导体层，以及该基板的一顶部分；于该基板的所述顶部分之间形成一隔离结构；使该隔离结构发生凹陷，此导致一通道区域中的该隔离结构的一顶表面是位于该基板的一顶表面的下方达一第一深度，其中该第一深度是至少为该第一半导体堆叠的该第一宽度的一半；以及形成一第一栅极结构和一第二栅极结构，其中该第一栅极结构包裹该第一半导体堆叠的所述第一半导体层的每一者，该第二栅极结构包裹该第二半导体堆叠的所述第一半导体层的每一者，而该第一栅极结构和该第二栅极结构的多个底表面是位于该基板的该顶表面的下方达该第一深度。
附图说明
本公开实施例可通过阅读以下的详细说明以及范例并配合相应的图式以更详细地了解。须要注意的是，依照业界的标准操作，各种特征部件并未依照比例绘制。事实上，为了清楚论述，各种特征部件的尺寸可以任意地增加或减少。
图1是显示根据本公开的一些实施例的制造示例半导体装置的示例方法100的流程图。
图2A是显示六个晶体管(6T)的SRAM单元的示意图。
图2B是显示根据本公开的一实施例的示例SRAM单元的俯视图。
图3A-图9A、图3B-图9B、图3C-图9C、图3D-图9D是分别显示根据本公开的一些实施例的图1的方法100的中间阶段的8个示例SRAM单元沿着图2B的线段A-A’、B-B’、C-C’、D-D’的横截面图。
图10是显示根据本公开的另一实施例的示例逻辑单元的俯视图。
图11A、图11B、图11C、图11D是分别显示根据本公开的一些实施例的示例逻辑单元沿着图10的线段E-E’、F-F’、G-G’、H-H’的横截面图。
其中，附图标记说明如下：
100：方法
102，104，106，108，110，112，114，116，118：操作
200：SRAM单元
202：基板
202N，202P：区域
202N-T，202P-T：顶部分(顶部基板部分)
204：隔离结构
210，210N，210P：堆叠
210A，210B：半导体层
220：虚置栅极结构
222：栅极间隔物
224，224N，224P：S/D沟槽
226：内部间隔物
230，230N，230P：S/D部件
232：层间介电质层
236：栅极沟槽
240，240N，240P：金属栅极结构
242：栅极介电层
244，244N，244P：金属栅极电极
250：栅极硬掩膜层
252：栅极端介电部件
260：S/D接触点
262：硅化物层
270：接触点
280：贯通元件
300：逻辑单元
A-A’，B-B’，C-C’，D-D’，E-E’，F-F’，G-G’，H-H’：线段
BL：位元线
BLB：反位元线
CVdd：正电源供应
CVss：负电源供应
D1，D2，D3，D5，D6，D7：深度
GL：长度
PD：下拉晶体管
PG：通道闸晶体管
PU：上拉晶体管
S1，S2，S5，S6：垂直片间距
T1，T2，T5，T6：厚度
W1，W2，W3，W5，W6：宽度
WL：字元线
X：X轴
Y：Y轴
Z：Z轴
具体实施方式
以下公开提供了用于实现本发明不同特征的许多不同实施例或示例。下面描述组件和布置的特定示例以简化本公开。当然，这些仅是示例，而非用于限制。例如，在下面的描述中，「第一特征在第二特征之上」可以包括第一和第二特征直接接触形成的实施例，亦可包括在第一特征和第二特征之间形成附加特征的实施例，使得第一和第二特征可以不直接接触。
另外，本公开可以在各个示例中重复参考数字且/或字母。前述重复是出于简单和清楚的目的，并且其本身并不指示所讨论的各种实施例且/或配置之间的关系。此外，以下在本公开中「一特征连接且/或耦合至另一特征」的形成方式可以包括直接接触的实施方式，亦可包括附加特征介于其中的实施方式，使得此二特征可能不会直接接触。另外，在空间上相对的用语，例如「较低」、「较高」、「水平」、「垂直」、「上方」、「之上」、「下方」、「之下」、「上」、「下」、「顶部」、「底部」等等及其衍生词(例如，「水平」，「向下」，「向上」等)是为了使本公开易于描述一特征与另一特征的关系。空间相对用词旨在覆盖包括特征的装置的不同方向。更进一步地说，当用「约」、「近似」等描述数值或数值范围时，该用词旨在涵盖在包括所述数值的合理范围内的数值，例如+/-10％内，为本领域技术人员所理解的数量的或其他值。又例如，用词「约5nm」可涵盖从4.5nm至5.5nm的尺寸范围。
本公开大致上涉及半导体装置及其制造方式，并且更具体地，是涉及制造场效晶体管(Field-Effect Transistors FETs)的方法，例如：纳米结构FET。
在纳米结构装置中，单一装置的通道区可以包括堆叠并彼此物理分离的多个通道半导体层(Channel Semiconductor Layer)。在一些示例中，装置的一栅极结构(包括一栅极介电层和一栅极电极)是设置在通道半导体层的周围(亦即，包裹(Wrap))。与传统的平面晶体管(Planar Transistor)和鳍式场效晶体管(FinFET)相比，由包裹通道半导体层的栅极结构所形成的晶体管(或称为包裹栅极晶体管(Wrapping Gate Transistor，WGT))可提供更好的栅极控制。栅极结构的底部可覆盖基板(Substrate)的上表面的一部分，而不是包裹一通道半导体层，从而可形成一底部平面晶体管(Bottom Planar Transistor，BPT)。BPT的栅极控制不如WGT好。因此，BPT的临界电压将不同于WGT的临界电压，此被称为电压不匹配(Threshold Voltage Mismatch)的问题，并可能会使静态随机存取存储器(StaticRandom Access Memory，SRAM)装置的性能下滑。此外，BPT可能具有较大的待机漏电(Standby Leakage)(Ioff)，这可能导致待机状态下的能量消耗量更大。因此，待机漏电是SRAM装置的另一个问题。
本公开提供了一种半导体装置，其中此半导体装置具有比传统半导体装置更进一步的栅极凹陷(Gate Recess)。在一些实施例中，栅极结构是延伸到基板(亦即，栅极结构的下表面在基板的上表面的下方)的至少一半通道宽度(Channel Width)。因此，纳米结构装置的BPT可以提供额外的侧壁栅极控制(Sidewall Gate Control)，并且可以减轻电压不匹配和待机漏电的问题。额外的侧壁栅极控制还可允许降低抗穿通(Anti-Punch-Through；APT)剂量以减少接面漏电(Junction Leakage)，从而可减轻APT掺杂剂向外扩散(Out-diffusion)的影响。在一些其他实施例中，P型外延S/D部件(S/D Epitaxial Feature)(例如：包括硅锗)比N型外延S/D部件更深地凹陷(Deeper Recess)，因此P型外延S/D部件可提供更大压力(Strain)给P型晶体管，其有利于改善电流(Ion)。因此，半导体装置的性能和可靠性皆能被改进。
图1是显示根据本公开的一些实施例所述的一示例半导体装置(例如：SRAM单元200或逻辑单元300的制造方法100的流程图。方法100仅是示例，并非用于限制本公开中权利要求所明确记载的以外内容。可以在方法100之前、期间，以及之后执行其他附加操作，而对于此方法的其他实施例，可以替换、消除或移动所描述的一些操作。如图2A是显示六个晶体管(Six-Transistor，6T)的SRAM单元(Cell)200的示意图。图2B是显示根据本公开的一实施例所述的示例SRAM单元200的俯视图。图3A-图3D至图9A-图9D是显示根据本公开的一些实施例所述的方法100的中间阶段的示例SRAM单元200的剖面图。图10、图11A-图11D是显示根据本公开的另一实施例所述的示例逻辑单元300的俯视图和剖面图。
示例半导体装置是不限于SRAM单元200或逻辑单元300。示例半导体装置可以是集成电路(Integrated Circuit，IC)或其一部分的处理期间所制造的中间装置，其可以包括SRAM且/或其他逻辑电路、被动元件(例如电阻器、电容器，以及电感器)和主动元件(例如P型FET(PFET)、N型FET(NFET)、金属氧化物半导体场效应晶体管(Metal-OxideSemiconductor Field Effect Transistors，MOSFET)、互补金属氧化物半导体(Complementary Metal-Oxide Semiconductor，CMOS)晶体管、双极性晶体管(BipolarTransistor)、高压晶体管、高频晶体管，且/或其他存储器单元(Memory Cell)。示例半导体装置可以是集成电路的核心区域(Core Region)(通常称为逻辑区域)、存储器区域(MemoryRegion)、模拟区域(Analog Region)、外围区域(Peripheral Region)(通常称为输入/输出(I/O)区域、虚置区域(Dummy Region)、其他合适区域，或是上述的组合的一部分。在一些实施例中，示例半导体装置可以是IC晶片(IC Chip)、系统上晶片(System-on-Chip，SOC)，或是其一部分。本公开不限于任何特定数量的装置或装置区域，或任何特定装置配置。
如图2A所示，6T SRAM单元200典型包括二个P型上拉晶体管(Pull-Up，PU)、二个N型下拉晶体管(Pull-Down，PD)，以及二个N型通道闸(Pass-Gate，PG)晶体管。下拉晶体管是与上拉晶体管形成交叉耦合反相器(Cross-Coupled Inverter)。此二反相器是交叉耦合以形成数据存储节点(Data Storage Node)。通道闸晶体管是耦接至数据存储节点，以进行写入和读取。图1更显示字元线(Word Line，WL)、位元线(Bit Line，BL)，以及反位元线(BiteLine Bar)，其可用于存取SRAM单元200的数据存储节点、正电源供应(Positive PowerSupply)CVdd，以及负电源供应(Negative Power Supply)(或大地)CVss。图2B是显示SRAM单元200的俯视图。
请参考图1、图3A-图3D，于操作102中，可接收SRAM单元的一起始结构(StartStructure)。SRAM单元200的起始结构包括一基板(Substrate)202。在一些实施例中，基板202是体硅(Bulk Silicon)(Si)基板。替代或附加地，基板202包括另一种单晶半导体(Single Crystalline Semiconductor)，例如锗(Ge)；复合半导体(CompoundSemiconductor)；合金半导体(Alloy Semiconductor)；或其组合。在一些实施例中，基板202是绝缘体上半导体(Semiconductor-on-Insulator)基板，例如：绝缘体上硅(Silicon-on-Insulator，SOI)基板、绝缘体上硅锗(Silicon Germanium-on-Insulator，SGOI)基板，或是绝缘体上锗(Germanium-on-Insulator，GOI)基板。绝缘体上半导体基板可以通过氧注入(Implantation of Oxygen，SIMOX)，晶片键合(Wafer Bonding)，且/或其他合适的方法来进行制造。
基板202包括根据SRAM单元200的设计要求配置的各种掺杂区(Doped Region)。在一些实施例中，基板202包括用于掺杂有P型掺杂剂(即P型井，P-type Well)的N型FET的区域202N。在一些实施例中，P型掺杂剂包括硼(例如，BF2)、铟、其他P型掺杂剂或其组合。基板202还包括用于掺杂有N型掺杂剂(即N型井，N-type Well)的P型FET的区域202P。在一些实施例中，N型掺杂剂包括磷、砷、其他N型掺杂剂或其组合。各种掺杂区可以通过各种注入制程(Implant Process)而直接形成在基板202之上且/或基板202之中。
在一些实施例中，基板202的顶部可以包括一些抗穿通(Anti-Punch Through，APT)掺杂剂，以减轻源极和漏极区域之间的穿通问题(Punch Through Issue)。可以执行注入制程以将掺杂剂(例如：硼、BF2、铟、碳、氮，或上述的组合)注入至用于N型FET的区域202N的顶部，抑或执行注入制程以将掺杂剂(例如：磷、砷、碳、氮，或上述的组合)至用于P型FET的区域202P的顶部，从而增强SRAM单元200的抗穿通能力。由于本公开中BPT的额外侧壁栅极控制，在维持相同或甚至更好的接面泄漏减少(Junction Leakage Reduction)的同时，至基板顶部的APT剂量可以小于传统的纳米结构装置。较少剂量的APT掺杂剂可以减轻APT掺杂剂向外扩散的影响，此有利于电压不匹配的性能。
交替的半导体层210A和210B是形成于基板202之上。在一些实施例中，半导体层210A包括一第一半导体材料，而半导体层210B包括一第二半导体材料，其是异于前述的第一半导体材料。半导体层210A和210B的不同半导体材料可具有不同的氧化速率(OxidationRate)且/或不同的蚀刻选择性(Etch Selectivity)。在一些实施例中，半导体层210A的半导体材料与基板202相同。在所示的实施例中，半导体层210A包括硅(Si，类似于基板202)，而半导体层210B包括硅锗(SiGe)。因此，交替的SiGe/Si/SiGe/Si…层可从底部到顶部布置于基板202之上。在一些实施例中，顶部半导体层的材料可以与底部半导体层相同或不同。半导体层210A和210B的数量是取决于SRAM单元200的设计要求。例如，其可以包括各自为两层到十层的半导体层210A或210B。在一些实施例中，不同的半导体层210A和210B在Z方向上具有相同厚度。在一些其他实施例中，不同的半导体层210A和210B具有不同的厚度。在一些实施例中，半导体层210A且/或210B是通过适当的外延制程(Epitaxy Process)来形成。例如，可通过分子束外延(Molecular Beam Epitaxy，MBE)制程、化学气相沉积(ChemicalVapor Deposition，CVD)制程、金属有机化学气相沉积(Metalorganic Chemical VaporDeposition，MOCVD)制程、其他合适的外延生长(Epitaxy Growth)制程，或是上述的组合，以在基板202的上方交替地形成包括SiGe和Si的半导体层。
交替的半导体层210A和210B被图案化，以分别形成区域202N和202P中的半导体堆叠(Semiconductor Stacks)210N和210P。半导体堆叠210N和210P皆可被称为半导体堆叠210(之后亦可称为堆叠210)。如图3A-图3C所示，可以对半导体层210A和210B执行光阻和蚀刻制程(Photoresist and Etching Process)以形成鳍形(Fin-Shape)堆叠210。例如，首先，在基板202上形成一图案化的抗光蚀遮罩(Photoresist Mask)。根据SRAM单元200的设计要求，图案化的抗光蚀遮罩可覆盖住鳍位置(Fin Position)。随后，使用图案化的抗光蚀遮罩执行一个或多个蚀刻制程，以形成堆叠210。前述的蚀刻制程包括干蚀刻(DryEtching)、湿蚀刻(Wet Etching)、其他合适的蚀刻制程，或上述的组合。然后通过任何适当的方法(例如：灰化制程，Ashing Process)来去除抗光蚀遮罩。然后，在堆叠210之间形成沟槽(Trench)。在所描绘的实施例中，一或多种蚀刻制程是沿着图案化的抗光蚀遮罩来除去半导体层210A、210B以及基板202的一些顶部分以形成鳍形堆叠210。换言之，堆叠210N包括半导体层210A、210B以及基板的剩余顶部分202N-T(亦即，N型的顶部基板部分202N-T)。并且，堆叠210P包括半导体层210A、210B，以及基板的剩余顶部分202P-T(亦即，P型的顶部基板部分202N-P)。参考如图3A所示，堆叠210P的宽度W1(在X方向上)是小于堆叠210N的宽度W2(在X方向上)。在一些实施例中，宽度W1约介于4nm至10nm之间，而宽度W2约介于6nm至20nm之间。每一堆叠210包括一通道区(Channel)，以及由通道区所插入(Interposed)的一源极区(Source Region)和一漏极区(Drain)。宽度W1和W2也称为纳米结构晶体管的通道宽度(Channel Width)。
仍然可参考图1和图3A-图3D，于操作104中，可在堆叠210之间的沟槽中形成一隔离结构(Isolation Structure)204(例如，一浅沟槽隔离(Shallow Trench Isolation，STI)结构)以分离并隔离SRAM单元200的主动区域或(且)被动区域。在一些实施例中，一种或多种介电材料(Dielectric Material)，例如：二氧化硅、氮化硅、且/或氮氧化硅，其他合适的隔离材料(例如：包括硅、氧，氮、碳或其他合适的隔离成分)，可沉积在堆叠210之间的沟槽中。可以通过CVD(例如：等离子体增强CVD，Plasma Enhanced CVD，PECVD)、物理气相沉积(Physical Vapor Deposition，PVD)、热氧化(Thermal Oxidation)，或其他方法技术来沉积介电材料。随后，介电材料会凹陷(例如，通过蚀刻且/或化学机械抛光(ChemicalMechanical Polishing，CMP))以形成隔离结构204。
现在，参考图1和图4A-图4D，于操作106中，可在堆叠210的上方形成虚置栅极结构(Dummy Gate Structure)220。每一虚置栅极结构220可作为一占位结构(Placeholder)，用于随后形成一金属栅极结构(Metal Gate Structure)。虚置栅极结构220是沿着X方向作延伸并穿越(Traverse)各个堆叠210。虚置栅极结构220可覆盖堆叠210中介于源极区和漏极区之间的通道区。每一虚置栅极结构220可以包括各种虚置层(Dummy Layer)。在一些实施例中，虚置栅极结构220可以包括设置于堆叠210和隔离结构204上方的一界面层(Interfacial Layer)(例如：包括氧化硅)、设置于界面层上方的一虚置栅极电极(DummyGate Electrode)(例如：包括多晶硅)、位于虚置栅极电极上的一或多个硬掩膜层(HardMask Layer)(例如：包括例如氮化硅、碳氮化硅、氧化硅等等的介电材料)且/或其他合适的层。可通过沉积制程、微影制程(Lithography Process)、蚀刻制程、其他合适制程，或上述的组合来形成虚置栅极结构220。例如，可将不同的虚置层沉积在堆叠210和隔离结构204的上方。然后，执行一微影制程以形成覆盖堆叠210的通道区的一掩膜(Mask)。此后，使用微影掩膜来将不同的虚置层作蚀刻，以形成虚置栅极结构220。然后，可使用任何适当的方法(例如：灰化制程)来去除微影掩膜。可参照图4B、图4C，每一虚置栅极结构220各具有一长度GL(在Y方向上)。在一些实施例中，栅极长度GL约介于4nm至30nm之间。
仍于操作106中，可沿着堆叠210上的虚置栅极结构220的侧壁来形成栅极间隔物(Gate Spacer)222。在一些实施例中，栅极间隔物222包括一介电材料，例如：氧化硅、氮化硅、碳掺杂的氧化物、氮掺杂的氧化物、多孔氧化物，或上述的组合。栅极间隔物222可通过任何合适的制程来形成。例如，首先，沿着虚置栅极结构220的侧壁和上表面之上来沉积一间隔物层(Spacer Layer)(例如，通过原子层沉积(Atomic Layer Deposition，ALD)、CVD、PVD，或其他适当的制程)，其中间隔物层包括介电材料。可针对间隔物层作各向异性蚀刻(Anisotropically Etch)以除去XY平面中的部分(XY平面为基板202的上表面所在的平面)。间隔物层的其余部分会变成为栅极间隔物(Gate Spacer)222。在一些实施例中，栅极间隔物222在Y方向上具有约介于3nm至12nm之间的宽度。
此后，仍然参考图1和图4A-图4D，于操作108中，在堆叠210的S/D(Source/Drain)区域的上方形成源极/漏极(S/D)沟槽224N和224P(均称为S/D沟槽224)。可参照图4B和图4C，堆叠210的S/D区域是沿着栅极间隔物222的侧壁发生凹陷，以形成S/D沟槽224。在一些实施例中，堆叠210的S/D区域可通过S/D蚀刻制程而发生凹陷，其中S/D蚀刻制程可以是一干蚀刻(例如：反应离子蚀刻，Reactive Ion Etching，RIE)、湿蚀刻，或其组合。可以控制S/D蚀刻制程的持续时间(Duration)，使得S/D沟槽224N和224P的底表面可位于基板202的顶表面的下方(亦即，最下方的半导体层210B的底表面)。在一些实施例中，可用以不同的操作来形成N型S/D沟槽224N和P型S/D沟槽224P，使得基板202的顶表面下方的N型S/D沟槽224N的深度D1(在Z方向上)可小于基板202的顶表面下方的P型S/D沟槽224P的深度D2(在Z方向上)。例如，首先，可形成一掩膜以覆盖P型区域202P，故可仅于N型区域202N中执行S/D蚀刻制程以形成S/D沟槽224N；在去除覆盖P型区域202P的掩膜之后，可形成另一个掩膜以覆盖N型区域202N，故可仅于P型区域202P中执行S/D蚀刻制程以形成S/D沟槽224P，而且，反之亦然。在一些实施例中，深度D1约介于5nm至40nm之间，深度D2约介于5nm至50nm之间，并且深度D2较深度D1更多出约5nm至30nm。
仍再参考图1和图4A-图4D，于操作108中，在半导体层210A的边缘之间可形成内部间隔物(Inner Spacer)226。由于S/D沟槽224的底表面在基板的顶表面下方，故所有半导体层210A和210B的侧壁皆完全暴露于S/D沟槽224之中。足够的暴露可以使内部间隔物的形成具有更好的品质和效率。在一些实施例中，通过适当的蚀刻制程，可以选择性地除去S/D沟槽224中的半导体层210B的暴露部分(边缘)，以于半导体层210A之间形成间隙(Gap)。易言之，半导体层210A的边缘是悬挂(Suspend)于S/D沟槽224中。由于半导体层210B(例如：SiGe)和210A(例如：Si)的材料具有不同氧化率且/或蚀刻选择性，仅有半导体层210B的暴露部分(边缘)会被去除，但半导体层210A基本保持不变。在一些实施例中，半导体层210B的暴露部分的选择性移除可以包括一氧化制程(Oxidation Process)，接着是一选择性蚀刻制程(Selective Etching Process)。例如，首先可选择性地氧化半导体层210B的边缘部分以纳入SiGeOx的材料。然后，可执行选择性蚀刻制程，以用合适的蚀刻剂(例如：氢氧化铵(NH4OH)或氟化氢(HF))来去除SiGeOx。可以控制氧化过程和选择性蚀刻过程的持续时间，使得仅有半导体层210B的边缘部分被选择性地去除。
此后，可形成内部隔离物226以填充半导体层210A之间的间隙。内部间隔物226可包括一介电材料(Dielectric Material)，其中此介电材料具有比栅极间隔物222更高的K值。例如，内部间隔物226包括例如氧化硅、氮化硅、氮氧化硅、碳氧化硅，或上述的组合。内部间隔物的介电材料可以通过ALD、CVD、PVD，或上述的组合，来沉积于S/D沟槽224之中以及半导体层210A的边缘之间的间隙之中。然后，可沿着栅极间隔物222的侧壁来除去额外的介电材料，直到半导体层210A的侧壁暴露于S/D沟槽224之中为止。在一些实施例中，内部间隔物226的厚度在Y方向上约介于3nm至12nm之间。
请参考图1和图5A-图5D，于操作110中，可以分别在S/D沟槽224N和224P中形成外延S/D部件230N和230P(均称为S/D部件230)。在一些实施例中，N型S/D部件230N包括硅，并可以掺杂有碳、磷、砷、其他N型掺杂剂，或上述的组合(例如，可形成Si：C外延S/D部件、Si：P外延S/D部件，或是Si：C：P外延S/D部件)。在一些实施例中，P型S/D部件230P包括硅锗或锗，并可以掺杂有硼、其他P型掺杂剂，或上述的组合(例如，可形成Si：Ge：B外延S/D部件)。可以实施外延制程，以从基板202和S/D沟槽224中暴露的半导体材料(亦即，半导体层210A的边缘部分)来外延生长(Epitaxially Grow)出S/D部件230。外延制程包括CVD沉积(用于例如：气相外延(Vapor-Phase Epitaxy，VPE)、超高真空(Ultra-High Vacuum)CVD(UHV-CVD)、LPCVD，且/或PECVD)、分子束外延(Molecular Beam Epitaxy)，其他合适的SEG制程，或上述的组合。在一些实施例中，外延S/D部件230可以包括多个外延半导体层(EpitaxialSemiconductor Layers)，其中不同的外延半导体层所包括的掺杂剂用量不同。S/D部件230的N型掺杂剂且/或P型掺杂剂可以扩散至半导体层210A的边缘部分中，从而形成半导体层210A的低掺杂边缘区域(Low Doped Edge Region)。
参照图5B和图5C所示，N型S/D部件230N延伸至基板的部分202N有一段深度D1，P型S/D部件230P延伸至基板的部分202P亦有一段深度D2。换句话说，N型S/D部件230N的底表面在基板202的顶表面下方有达深度D1，而P型S/D部件230P的底表面在基板202的顶表面下方有达深度D2。在一些实施例中，深度D2是大于深度D1达至少5nm。例如，深度D1可约介于5nm至40nm之间，深度D2可约介于5nm至50nm之间，并且深度D1和D2两者之间的差值可约介于5nm至30nm之间。因此，P型S/D部件230P具有比N型S/D部件230N更大的尺寸，P型S/D部件230P的材料(例如：Si：Ge：B)可以提供更大压力给P型晶体管以改善离子性能(IonPerformance)。
此后，仍然参考图1和图5A-图5D，于操作110中，可将一层间介电质层(InterlayerDielectric Layer，ILD Layer)232设置于相邻的的虚置栅极结构220和栅极间隔物222之间。在一些实施例中，ILD层232包括一介电材料，例如：氧化硅、氮化硅、氮氧化硅、四乙氧基硅烷(Tetraethylorthosilicate，TEOS)所形成的氧化物、磷硅酸盐玻璃(PhosphosilicateGlass，PSG)、硼磷硅酸盐玻璃(Borophosphosilicate Glass，BPSG)、低k值介电材料(K<3.9)、其他合适的介电材料，或上述的组合。可以通过沉积制程(例如：CVD、PVD、ALD、电镀、其他合适的方法，或上述的组合)来形成ILD层232。在一些实施例中，可以执行CMP制程且/或其他平面化(Planarization)制程，直到延伸(暴露)虚置栅极结构220的虚置栅极为止。
现在参考图1和图6A至图6D。于操作112中，可以去除虚置栅极结构220，以形成暴露于堆叠210的通道区(Channel Region)的栅极沟槽(Gate Trench)236。在一些实施例中，去除虚置栅极结构220的操作可包括一或多个蚀刻制程，例如：湿蚀刻、干蚀刻(例如，反应离子蚀刻(Reactive-Ion Etching，RIE))，或是其他蚀刻技术。半导体层210A和210B、顶部基板部分202N-T和202P-T的顶表面，以及顶部基板部分202N-T和202P-T的侧壁的一部分可在栅极沟槽236中暴露出来。
仍可参考图1和图6A至图6D。于操作114中，隔离结构204将可进一步凹陷，使得通道区域中的隔离结构204的顶表面是位于基板202的顶表面(亦即，顶部基板部分202N-T和202P-T的顶表面，或最下面的半导体层210B的底表面)的下方达一深度D3(沿Z方向)。在一些实施例中，可以通过一蚀刻制程(例如：干蚀刻、湿蚀刻，或上述的组合)或其他适当的凹陷制程来进一步使隔离结构204发生凹陷。在一些实施例中，深度D3为堆叠210P的通道宽度(Channel Width)W1的至少一半。例如，通道宽度W1可约介于4nm至10nm之间，而深度D3可至少约为5nm。因此，顶部基板部分202N-T和202P-T上的BPT将具有足够的栅极侧壁控制，以减轻电压不匹配的问题及待机泄漏的问题。可参考第6A、6C、6D图，在所描绘的实施例中，隔离结构204在源极区或漏极区(均称为源极/漏极(S/D)区域)中的顶表面是大致与基板202的顶表面呈现一共面关系(Coplanar)，其中基板202是位于通道区域中的隔离结构204的顶表面的上方。
在一些其他实施例中，隔离结构204在形成虚置栅极结构220之前会进一步凹陷。也就是说，可以在操作106之前执行操作114。在这种情况下，通道区域和S/D区域中的隔离结构204皆会发生凹陷，使得通道区域和S/D区域中的隔离结构204的顶表面可位于基板202的顶表面的下方皆达深度D3。
现在参照图1和图7A-图7D，于操作116中，可从栅极沟槽236中选择性地除去半导体层210B。由于半导体层210A和210B的材料不同，所以通过一选择性氧化/蚀刻制程来去除半导体层210B，其可类似于除去半导体层210B的边缘部分的方式。在一些实施例中，在选择性除去半导体层210B的过程期间，半导体层210A会被略微蚀刻或未被蚀刻。因此，半导体层210A可悬挂于堆叠210的通道区域中，并且大致沿着垂直于基板202的顶表面(亦即，X-Y平面)的方向(亦即，Z方向)来进行堆叠。悬置的半导体层210A也被称为通道半导体层(Channel Semiconductor Layer)210A。
参照图7A，堆叠210P包括通道半导体层210A和顶部基板部分202P-T，而堆叠210N包括通道半导体层210A和顶部基板部分202N-T。P型堆叠210P的通道半导体层210A具有在X方向上的宽度W1(亦即，通道宽度W1)和在Y方向上的厚度T1(亦即，通道厚度T1)。堆叠210P的相邻半导体层210A在Y方向上的间距为S1(亦即，垂直片间距(Vertical Sheet Pitch)S1)。N型堆叠210N的通道半导体层210A具有在X方向上的宽度W2(亦即，通道宽度W2)和在Y方向上的厚度T2(亦即，通道厚度T2)。堆叠210N的相邻半导体层210A之间在Y方向上的间距为S2(亦即，垂直片间距S2)。在一些实施例中，通道宽度W1约介于4nm至10nm之间，通道宽度W2约介于6nm至20nm之间，通道厚度T1或T2约介于4nm至8nm之间，垂直片间距S1或S2约介于6nm至15nm之间。顶部基板部分202P-T和202N-T的顶表面皆位于隔离结构204的顶表面的上方达一深度D3，其中深度D3为P型晶体管的通道宽度W1的至少一半。因此，稍后形成的金属栅极结构240(在图8A-图8D中)可以具有更佳的侧壁控制，以减轻电压不匹配和待机泄漏问题。在一些实施例中，深度D3为至少约5nm。
参照图1和图8A-图8D，仍在操作116中，在堆叠210的通道区中可以形成金属栅极结构240N和240P(均称为金属栅极结构240)。金属栅极结构240可以包裹(Wrap)每个悬置的通道半导体层210A。在一些实施例中，每一金属栅极结构240包括一栅极介电层242、一金属栅极电极244，且/或其他金属栅极层。在一些实施例中，栅极介电层242包括具有氮掺杂的介电材料的氧化物(Oxide with Nitrogen Doped Dielectric Material)，其是与金属含量的高K值介电材料(Metal Content High-K Dielectric Material)(K>13)互相结合。在一些实施例中，栅极介电层242的材料是选自氧化钽(Ta2O5)、氧化铝(Al2O3)、铪(Hf)含量氧化物、钽(Ta)含量氧化物、钛(Ti)含量氧化物、锆(Zr)含量的氧化物、铝(Al)含量氧化物、镧(La)含量的氧化物、高K值材料(K>或＝9)、其他合适的高k值介电材料，或上述的组合。在一些实施例中，栅极介电质层242具有约介于0.5nm至3nm的厚度，并且可通过CVD、PVD、ALD，且/或其他合适的方法来进行沉积。然后将金属栅极电极244填充于栅极介电层242之间的空间中。每一金属栅极电极244包括一或多个功函数金属(Work Function Metal，WFM)层和一块状金属(Bulk Metal)。WFM层是用于调整其对应晶体管的一功函数(Work Function)，以实现期望的临界电压(Threshold Voltage)Vt。并且，块状金属是用作功能栅极结构(Functional Gate Structure)的主要导电部分(Main Conductive Portion)。在一些实施例中，P型WFM层材料包括：TiN、TaN、TaSN、Ru、Mo、Al、WN、WCN、ZrSi2、MoSi2、TaSi2、NiSi2、其他P型功函数材料，或上述的组合。N型WFM层材料包括：Ti、Al、Ag、Mn、Zr、TiAl、TiAlC、TiAlSiC、TaC、TaCN、氮化硅、TaAl、TaAlC、TaSiAlC、TiAlN、其他N型功函数材料，或上述的组合。块状金属可以包括Al、W、Cu，或上述的组合。金属栅极电极244的各个层可以通过任何合适的方法形成，例如：CVD、ALD、PVD、电镀、化学氧化、热氧化、其他合适的方法，或上述的组合。此后，可再应用一或多种抛光制程(Polishing Process)(例如：CMP)以去除任何多余的导电材料，并使得SRAM单元200的顶表面变得平坦化。
可参照图8A，金属栅极结构240的底部(包括栅极介电层242和金属栅极电极244)可覆盖顶部基板部分202N-T和202P-T的顶表面和侧壁的一部分，从而形成三闸BPT(Tri-gate BPT)。由于被金属栅极结构240的底部所覆盖的侧壁的一部分在Z方向上具有足够的深度D3(深度D3为P型晶体管的通道宽度W1的至少一半)，故三栅极BPT可提供更佳的栅极控制，以缓解电压不匹配问题并减少待机泄漏。在一些实施例中，深度D3为至少约5nm。
现在，参照图1和图9A-图9D，于操作118中，可形成各种其他结构以完成(Finalize)SRAM单元200。例如，在栅极结构240和栅极间隔物222的顶部上方可形成栅极硬掩膜层(Gate Hard Mask Layer)250。栅极硬掩膜层250可作为接触蚀刻保护层(ContactEtch Protection Layer)。在一些实施例中，栅极硬掩膜层250具有约介于2nm至60nm之间的厚度，并且包括介电材料，例如：基于氧化物的介电质、基于氮化物的介电质(例如：碳氧化硅、氧氮化硅，或是氧碳氮化硅)、金属氧化物的介电材料(例如：氧化铪(HfO2)、氧化钽(Ta2O5)、氧化钛(TiO2)、氧化锆(ZrO2)、氧化铝(Al2O3)、氧化钇(Y2O3))，或上述的组合。栅极硬掩膜层250的形成可以包括各种操作。例如，金属闸回蚀(Metal Gate Etching Back)、硬掩膜层沉积(Hard Mask Layer Deposition)，以及平坦化制程等等。
在所描绘的实施例中，根据SRAM单元200的设计，可形成栅极端介电部件(GateEnd Dielectric Feature)252并用于分离金属栅极结构240。栅极端介电部件252包括介电材料，并且可以通过包括微影、蚀刻，以及沉积等等在内的各种操作来形成。
S/D接触点(S/D Contact)260可形成在外延S/D部件230的上方。S/D接触点260包括例如Al、W、Cu或其组合的导电材料。可以在外延S/D部件230和S/D接触点260之间形成一硅化物层262(例如：包括硅化镍、硅化钴、硅化钨、硅化钽、硅化钛，硅化铂、硅化铒，硅化钯，或上述的组合)。S/D接触点260和硅化物层262的形成可以涉及多个微影、蚀刻、沉积、退火(Annealing)，以及平坦化制程。在一些实施例中，S/D接触件260通过一自对齐接触形成制程(Self-aligned Contact Forming Process)来形成。
然后，在SRAM单元200的顶部的上方可形成各种其他互连结构(InterconnectionStructure)。在一些实施例中，各种互连结构可以包括多个介电ILD层、接触点(Contact)270、贯通元件(Via，亦可称为导电通孔)280、金属线(Metal Line)且/或其他结构，用于连接各种部件以形成一功能性SRAM单元(Functional SRAM Cell)。
在一些实施例中，包括SRAM单元200的一集成电路(IC)还可以包括其他SRAM单元。在一些实施例中，同一IC中可包括一第二SRAM单元，其具有比SRAM单元200更大的通道宽度。例如，第二SRAM单元的PU晶体管(亦即，P型晶体管)的通道宽度可约介于6nm至10nm之间，而第二SRAM单元的PG/PD晶体管(亦即，N型晶体管)的通道宽度可约介于10nm至40nm之间。因此，第二SRAM单元的单元尺寸可为SRAM单元200的单元尺寸的大约1.1倍至1.4倍。
图10是显示根据本公开的另一实施例的逻辑单元300的俯视图。图11A-图11D分别显示出沿图10中的线段E-E’、F-F’、G-G’、H-H’的逻辑单元300的横截面图。逻辑单元300中相同的附图标记可表示SRAM单元200中相同的半导体结构/元件，除非在以下叙述中特别指出，否则它们皆具有相同的尺寸和相同的制造制程。
如图11A所示，堆叠210P包括通道半导体层210A和顶部基板部分202P-T。堆叠210P的通道宽度为W5。堆叠210P的通道厚度为T5，而堆叠210P的垂直片间距为S5。堆叠210N包括通道半导体层210A和顶部基板部分202N-T。堆叠210N的通道宽度为W6。堆叠210N的通道厚度为T6，而堆叠210N的垂直片间距为S6。在一些实施例中，通道宽度W5或W6可约介于30nm至40nm之间。通道厚度T5或T6可约介于4nm至8nm之间。垂直片间距S5或S6可约介于6nm至15nm之间。在所描述的实施例中，包括栅极介电层242和金属栅极电极244(亦即，244P和244N)的金属栅极结构的底部可覆盖顶部基板部分202N-T和202P-T的顶表面和侧壁的一部分，从而可形成三栅极BPT。由于被金属栅极结构240的底部所覆盖的侧壁的一部分在Y方向上具有足够的深度D5，因此三栅极BPT可以提供更佳的栅极控制，以减轻电压不匹配的问题同时降低待机泄漏。在一些实施例中，距离D5至少约为5nm。
参考图11B，S/D部件230N可延伸进入N型基板部分202N之中达一深度D6。换句话说，S/D部件230N的底表面可位于基板的顶表面的下方达一深度D6。参考图11C，S/D部件230P可延伸进入P型基板部分202P之中达一深度D7。换句话说，S/D部件230P的底表面可位于基板的顶表面下方达一深度D7。在一些实施例中，深度D6可约介于5nm至40nm之间，深度D7可约介于5nm至50nm之间，而深度D7较深度D6可约多出5nm至30nm，使得P型S/D部件230P(例如：包括Si：Ge：B)可以向P型纳米结构晶体管提供更大的压力以利于离子改善(IonImprovement)。
尽管不是为了作限制，但是本公开的一或多个实施例为集成电路及其形成制程提供了许多益处。例如，本公开的实施例提供了一种半导体装置，该半导体装置包括在基板中延伸的凹陷栅极结构。凹陷栅极结构的底表面是位于基板的顶表面的下方达到FET的通道宽度的一半，以形成三栅极BPT。与纳米结构晶体管的常规BPT相比，三栅极BPT具有更好的侧壁栅极控制，这可以减轻电压不匹配和待机泄漏的问题。额外的侧壁栅极控制还允许降低APT剂量以减少接面泄漏，因此可以减轻APT掺杂剂向外扩散的影响。另外，在本公开中，与N型外延S/D部件相比，P型外延S/D部件在基板中可延伸得更多。P型外延S/D部件的较大尺寸可以为P型FET提供更大的压力，这有利于离子改善，因此能改善半导体装置的性能和可靠程度。
本公开提供许多不同实施例。在一方面，提供一种半导体装置，包括：一基板，包括多个顶部分，其中所述顶部分是由一隔离结构所隔离开；多个第一半导体层，位于一第一区域中的该基板的一第一顶部分之上，其中所述第一半导体层是堆叠起来并彼此分离，而所述第一半导体层的每一者皆具有一第一宽度；以及一第一栅极结构，包裹所述第一半导体层的每一者，并覆盖住延伸于该隔离结构的上方的该基板的该第一顶部分的一顶表面和多个侧壁，其中该第一栅极结构的一底表面是位于该基板的该顶表面的下方达一第一深度，而该第一深度至少为该第一宽度的一半。
在一些实施例中，该第一深度约至少为5nm，而所述第一半导体层的该第一宽度约小于或等于10nm。在一些实施例中，该半导体装置还包括：一第一源/漏极(S/D)部件，形成于该基板的该第一区域之中，其中该第一源/漏极部件的一底表面是位于该基板的该顶表面的下方达一第二深度。在一些实施例中，该第二深度约至少为5nm。在一些实施例中，该半导体装置还包括：一第二源/漏极(S/D)部件，形成于该基板的一第二区域之中，其中该第二源/漏极部件的一底表面是位于该基板的该顶表面的下方达一第三深度，而该第三深度是大于该第二深度。在一些实施例中，该半导体装置还包括：多个第二半导体层，位于该第二区域中的该基板的一第二顶部分之上，其中所述第二半导体层是堆叠起来并彼此分离，所述第二半导体层的每一者皆具有一第二宽度，而该第二宽度是大于所述第一半导体层的该第一宽度。在一些实施例中，该半导体装置还包括：一第二栅极结构，包裹所述第二半导体层的每一者，并覆盖住延伸于该隔离结构的上方的该基板的该第二顶部分的一顶表面和多个侧壁，其中该第二栅极结构的一底表面是位于该基板的该顶表面的下方达该第一深度。
在另一方面，提供一种集成电路，包括：一基板，包括一P型区域和一N型区域，其中该基板包括多个顶部分，而所述顶部分是由一隔离结构所隔离开；一第一半导体堆叠，设置于该基板的该P型区域之上；一第二半导体堆叠，设置于该基板的该N型区域之上，其中该第一半导体堆叠和该第二半导体堆叠的每一者皆包括多个半导体层，而所述半导体层是堆叠起来并彼此分离；一第一源/漏极(S/D)部件，形成于该基板的该P型区域之上；以及一第二源/漏极部件，形成于该基板的该N型区域之上，其中该第一源/漏极部件的一底表面是位于该基板的一顶表面的下方达一第一深度，该第二源/漏极部件的一底表面是位于该基板的该顶表面的下方达一第二深度，而该第二深度是小于该第一深度。
在一些实施例中，该第一深度约介于5nm至50nm之间。在一些实施例中，该第二深度约介于5nm至40nm之间。在一些实施例中，该集成电路还包括：一第一栅极结构，形成于该基板的该P型区域之上；以及一第二栅极结构，形成于该基板的该N型区域之上，其中该第一栅极结构和该第二栅极结构的多个底表面是位于该基板的该顶表面的下方达一第三深度。在一些实施例中，该第三深度约至少为5nm。在一些实施例中，该基板的所述顶部分包括APT(Anti-Punch-Through)掺杂剂。
在又一方面，提供一种形成集成电路的方法，包括：接收一基板，其中该基板包括一第一区域和一第二区域；于基板之上交替地生长出多个第一半导体层和多个第二半导体层，其中所述第一半导体层和所述第二半导体层包括不同半导体材料；蚀刻所述第一半导体层、所述第二半导体层，以及该基板的多个部分以形成一第一半导体堆叠和一第二半导体堆叠，其中该第一半导体堆叠于该第一区域中具有一第一宽度，该第二半导体堆叠于该第二区域中具有一第二宽度，该第二宽度是大于该第一宽度，而该第一半导体堆叠和该第二半导体堆叠的每一者皆包括所述第一半导体层、所述第二半导体层，以及该基板的一顶部分；于该基板的所述顶部分之间形成一隔离结构；使该隔离结构发生凹陷，此导致一通道区域中的该隔离结构的一顶表面是位于该基板的一顶表面的下方达一第一深度，其中该第一深度是至少为该第一半导体堆叠的该第一宽度的一半；以及形成一第一栅极结构和一第二栅极结构，其中该第一栅极结构包裹该第一半导体堆叠的所述第一半导体层的每一者，该第二栅极结构包裹该第二半导体堆叠的所述第一半导体层的每一者，而该第一栅极结构和该第二栅极结构的多个底表面是位于该基板的该顶表面的下方达该第一深度。
在一些实施例中，该方法还包括：于该第一区域之中形成一第一源/漏极(S/D)沟槽，并于该第二区域之中形成一第二源/漏极沟槽，其中该第一源/漏极沟槽和该第二源/漏极沟槽的多个底表面是位于该基板的该顶表面的下方；以及于该第一源/漏极沟槽之中外延生长一第一源/漏极部件，并于该第二源/漏极沟槽之中外延生长一第二源/漏极部件。在一些实施例中，该第一源/漏极沟槽的该底表面是位于该基板的该顶表面的下方达一第二深度，该第二源/漏极沟槽的该底表面是位于该基板的该顶表面的下方达一第三深度，而该第三深度是小于该第二深度。在一些实施例中，形成该第一栅极结构和该第二栅极结构的操作包括：于该第一半导体堆叠和该第二半导体堆叠之上形成一虚置栅极结构；沿着该虚置栅极结构的多个侧壁来形成多个栅极间隔物；除去该虚置栅极结构以形成一栅极沟槽；经由该栅极沟槽，选择性地除去该第一半导体堆叠和该第二半导体堆叠的所述第二半导体层；形成多个栅极介电层，以包裹所述第一半导体层的每一者，并覆盖该基板的所述顶部分的一暴露部分；以及将一导体材料沉积于所述栅极介电层之上。
在一些实施例中，使该隔离结构发生凹陷的操作是于形成该虚置栅极结构的操作之前被执行。在一些实施例中，使该隔离结构发生凹陷的操作是于除去该虚置栅极结构的操作之后被执行。在一些实施例中，该方法还包括：在形成该第一源/漏极沟槽和该第二源/漏极沟槽的操作之后，选择性地除去所述第二半导体层的多个边缘部分；以及于所述第二半导体层的已移除的所述边缘部分之中形成多个内部间隔物，其中所述内部间隔物包括不同于多个顶部间隔物的材料。
前述内文概述了许多实施例的特征，使本技术领域中具有通常知识者可以从各个方面更佳地了解本公开。本技术领域中具有通常知识者应可理解，且可轻易地以本公开为基础来设计或修饰其他制程及结构，并以此达到相同的目的及/或达到与在此介绍的实施例等相同的优点。本技术领域中具有通常知识者也应了解这些相等的结构并未背离本公开的发明精神与范围。在不背离本公开的发明精神与范围的前提下，可对本公开进行各种改变、置换或修改。

Claims (1)

1.一种半导体装置，包括：
一基板，包括多个顶部分，其中所述顶部分是由一隔离结构所隔离开；
多个第一半导体层，位于一第一区域中的该基板的一第一顶部分之上，其中所述第一半导体层是堆叠起来并彼此分离，而所述第一半导体层的每一者皆具有一第一宽度；以及
一第一栅极结构，包裹所述第一半导体层的每一者，并覆盖住延伸于该隔离结构的上方的该基板的该第一顶部分的一顶表面和多个侧壁，其中该第一栅极结构的一底表面是位于该基板的该顶表面的下方达一第一深度，而该第一深度至少为该第一宽度的一半。
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