WO2023197828A1 - 晶体管及其制备方法、半导体器件及其制备方法 - Google Patents

晶体管及其制备方法、半导体器件及其制备方法 Download PDF

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Publication number
WO2023197828A1
WO2023197828A1 PCT/CN2023/082328 CN2023082328W WO2023197828A1 WO 2023197828 A1 WO2023197828 A1 WO 2023197828A1 CN 2023082328 W CN2023082328 W CN 2023082328W WO 2023197828 A1 WO2023197828 A1 WO 2023197828A1
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Prior art keywords
layer
dielectric layer
work function
type work
gate
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PCT/CN2023/082328
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English (en)
French (fr)
Inventor
张珂豪
黄伟川
刘熹
刘旭
陈磊
叶约翰
林军
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华为技术有限公司
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Publication of WO2023197828A1 publication Critical patent/WO2023197828A1/zh

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    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
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    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66409—Unipolar field-effect transistors
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    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present application relates to the field of semiconductor technology, and in particular to transistors and their preparation methods, semiconductor devices and their preparation methods.
  • Fin Field-Effect-Transistor with high dielectric constant metal gate (High K Metal Gate, HKMG) is often used as the transistor unit.
  • the HKMG may include a gate dielectric layer and a gate metal layer, and a P-type work function layer and an N-type work function layer located between the gate dielectric layer and the gate metal layer.
  • the threshold voltage of the transistor can be controlled by controlling the thickness of the P-type work function layer.
  • HKMG's gate length has been reduced to about 20nm. The gate length limits the filling space of multiple film layers in HKMG.
  • Embodiments of the present application provide a transistor and its preparation method, a semiconductor device and its preparation method, and electronic equipment, which are used to improve the problem that the thickness of each film layer in the gate structure of the transistor is limited due to the reduction in the size of the semiconductor device. .
  • a transistor in a first aspect, includes a fin, a gate dielectric layer, a gate metal layer, a source electrode and a drain electrode.
  • the fin includes a source region, a drain region, and a channel region between the source region and the drain region.
  • a gate dielectric layer spans the channel region, the gate dielectric layer contains aluminum atoms, and the aluminum atoms are close to a surface of the gate dielectric layer away from the channel region.
  • a gate metal layer is located on the gate dielectric layer.
  • the source electrode is located on the source electrode region, and the drain electrode is located on the drain electrode region.
  • the gate dielectric layer contains aluminum atoms, and the aluminum atoms are close to the surface of the gate dielectric layer away from the channel region, so that a dipole can be formed on the surface of the gate dielectric layer away from the channel region.
  • the dipole is used to regulate the work function and thereby control the threshold voltage of the transistor.
  • the allowable thickness range of other film layers in the gate structure eg, gate dielectric layer and gate metal layer
  • the allowable thickness range of the gate metal layer can be thicker, which is beneficial to reducing the gate resistance of the transistor and improving the performance of the transistor.
  • the transistor further includes a P-type work function layer, and the P-type work function layer is located between the gate dielectric layer and the gate metal layer. Since there is no need to provide an N-type work function layer between the gate dielectric layer and the gate metal layer, when the filling space of the gate structure is fixed, the allowable thickness range of other film layers in the gate structure is larger. so, In the case where the transistor further includes a P-type work function layer, the allowable thickness range of the P-type work function layer may also be larger. Since the thickness of the P-type work function layer is related to the threshold voltage of the transistor, when the allowable thickness range of the P-type work function layer is larger, the adjustable range of the threshold voltage of the transistor can also be larger. In this way, after the transistor is applied to the semiconductor device, by setting the thickness of the P-type work function layer in the transistor to be different, the semiconductor device can include more transistors with different threshold voltages, thereby improving the performance of the semiconductor device.
  • the transistor further includes an etching barrier layer located between the gate dielectric layer and the P-type work function layer.
  • the etching barrier layer can be used as a stop layer during the process of etching the P-type work function layer, thereby preventing the gate dielectric layer from being etched during the process of etching the P-type work function layer.
  • the transistor further includes a protective layer.
  • the protective layer is located between the gate dielectric layer and the gate metal layer, and is in contact with the gate dielectric layer.
  • a protective layer is provided in the gate structure.
  • the protective layer contacts the gate dielectric layer and can also prevent the oxygen atoms in the gate dielectric layer from diffusing to the outside, thereby effectively It improves the problem that the gate leakage current of the transistor increases due to the outward diffusion of oxygen atoms in the gate dielectric layer and the degradation of the gate structure performance.
  • the transistor further includes an adhesive layer.
  • the adhesive layer is located between the gate dielectric layer and the gate metal layer and is in contact with the gate metal layer. In this way, the adhesive layer is located between the gate dielectric layer and the gate metal layer and is in contact with the gate metal layer, so that it can be used to bond the gate metal layer, improve the adhesion between the gate metal layer and the gate dielectric layer, and prevent the gate metal layer from Separation between the gate dielectric layer and the gate dielectric layer occurs.
  • the material of the gate dielectric layer includes hafnium dioxide.
  • the content of aluminum element in the gate dielectric layer is higher than the content of aluminum element in other film layers, and the other film layers at least include the gate metal layer.
  • the transistor further includes a gate insulating layer located between the gate structure and the channel region.
  • a semiconductor device in a second aspect, includes a substrate and a plurality of transistors provided on the substrate.
  • the transistors are the transistors described in any of the above embodiments.
  • the plurality of transistors include an N-type field effect transistor and a P-type field effect transistor, and the P-type field effect transistor includes a P-type work function layer.
  • the thicknesses of the P-type work function layers in the plurality of P-type field effect transistors are not exactly the same. Such an arrangement makes the work functions of the gate structures of multiple P-type field effect transistors not exactly the same, and the threshold voltages of multiple P-type field effect transistors are not exactly the same, which is conducive to the realization of a multi-threshold voltage system of semiconductor devices and improves the efficiency of semiconductor devices. device performance.
  • At least one of the N-type field effect transistors includes a P-type work function layer.
  • a plurality of the N-type field effect transistors include a P-type work function layer, and the thicknesses of the P-type work function layers in the plurality of N-type field effect transistors are not exactly the same.
  • the work functions of the gate structures in multiple N-type field effect transistors are not exactly the same, and the threshold voltages of multiple N-type field effect transistors are not exactly the same, which is beneficial to realizing a multi-threshold voltage system of semiconductor devices and improving the performance of semiconductor devices. performance.
  • a method for manufacturing a transistor includes: forming a fin on a substrate, the fin including a source region, a drain region, and a region between the source region and the drain region. channel area between.
  • a source is formed on the source region, and the drain is formed on the drain region;
  • a gate dielectric layer is formed, and the gate dielectric layer spans the channel region;
  • the gate dielectric layer contains aluminum atoms, and the aluminum atoms are close to the gate dielectric layer and away from
  • a gate metal layer is formed on the gate dielectric layer.
  • forming a gate dielectric layer includes: forming an initial dielectric layer spanning the channel region; forming an N-type work function layer on the initial dielectric layer, so that The N-type work function layer includes aluminum atoms; an annealing process is used to move the aluminum atoms in the N-type work function layer to the initial dielectric layer to form the gate dielectric layer; and the N-type work function layer is removed. function layer.
  • the preparation method further includes: forming a P-type work function layer on the initial dielectric layer before forming an N-type work function layer on the initial dielectric layer.
  • the preparation method further includes: forming an etching barrier layer on the initial dielectric layer before forming a P-type work function layer on the initial dielectric layer.
  • the preparation method further includes: after forming the initial dielectric layer, forming a protective layer on the initial dielectric layer.
  • the preparation method further includes: forming an adhesive layer on the gate dielectric layer.
  • the preparation method further includes: forming a gate insulating layer, the gate insulating layer spanning the channel. area.
  • a method for manufacturing a semiconductor device includes: providing a substrate, the substrate including an N-type field effect transistor region and a P-type field effect transistor region.
  • a plurality of fins are formed on the substrate, the fins include a source region, a drain region, and a channel region between the source region and the drain region; the plurality of fins include a source region located between the source region and the drain region.
  • a source is formed on the source region, and a drain is formed on the drain region; an initial dielectric layer is formed, and the initial dielectric layer spans the channel region.
  • a P-type work function layer is formed on the initial dielectric layer, and the P-type work function layer is at least located in the P-type field effect transistor region.
  • An N-type work function layer is formed on the P-type work function layer.
  • the N-type work function layer is located in the N-type field effect transistor area and the P-type field effect transistor area, and the N-type work function layer includes aluminum atoms. .
  • An annealing process is used to target and move the aluminum atoms in the N-type work function layer to the initial dielectric layer to form the gate dielectric layer.
  • the aluminum atoms are close to the surface of the gate dielectric layer away from the channel region.
  • the N-type work function layer is removed.
  • the gate metal layer is formed on the P-type work function layer.
  • forming a P-type work function layer on the initial dielectric layer includes: forming a first intermediate P-type work function layer on the initial dielectric layer; patterning the first intermediate P-type work function layer layer; forming a second intermediate P-type work function layer on the patterned first intermediate P-type work function layer; repeating the above steps at least once until the P-type work function layers of the plurality of transistors reach the target thickness.
  • an electronic device in a fifth aspect, includes a printed circuit board and a semiconductor device as described in any of the above embodiments; the semiconductor device and the printed circuit board are electrically connected.
  • Figure 1A is a perspective view of a transistor provided by an embodiment of the present application.
  • Figure 1B is a top view of a transistor provided by an embodiment of the present application.
  • Figure 2 is a cross-sectional view of the transistor shown in Figure 1A at D-D’;
  • Figure 3 is a cross-sectional view of the transistor shown in Figure 1A at E-E’;
  • Figure 4 is another cross-sectional view of the transistor shown in Figure 1A at DD';
  • Figure 5 is another cross-sectional view of the transistor shown in Figure 1A at D-D';
  • Figure 6 is another cross-sectional view of the transistor shown in Figure 1A at D-D';
  • Figure 7 shows the detection results of aluminum and hafnium elements in a transistor using a secondary ion mass spectrometer
  • Figure 8 shows the detection results of aluminum and hafnium elements in another transistor using a secondary ion mass spectrometer
  • Figure 9 is a perspective view of a semiconductor device provided by an embodiment of the present application.
  • Figure 10 is a top view of a semiconductor device provided by an embodiment of the present application.
  • Figure 11 is a cross-sectional view of the semiconductor device shown in Figure 10 at F-F';
  • Figure 12 is another cross-sectional view of the semiconductor device shown in Figure 10 at F-F';
  • Figure 13 is a flow chart of a method for manufacturing a transistor provided by an embodiment of the present application.
  • Figure 14 is a perspective view of another transistor provided by an embodiment of the present application.
  • Figure 15 is a top view of a transistor provided by an embodiment of the present application.
  • Figure 16 is a structural diagram of a transistor provided by an embodiment of the present application.
  • Figure 17 is a flow chart of another method of manufacturing a transistor provided by an embodiment of the present application.
  • Figure 18 is a structural diagram of another transistor provided by an embodiment of the present application.
  • Figure 19 is a structural diagram of yet another transistor provided by an embodiment of the present application.
  • Figure 20 is a structural diagram of another transistor provided by an embodiment of the present application.
  • Figure 21 is a flow chart of yet another method of manufacturing a transistor provided by an embodiment of the present application.
  • Figure 22 is a structural diagram of another transistor provided by an embodiment of the present application.
  • Figure 23 is a flow chart of yet another method of manufacturing a transistor provided by an embodiment of the present application.
  • Figure 24 is a structural diagram of another transistor provided by an embodiment of the present application.
  • Figure 25 is a flow chart of yet another method of manufacturing a transistor provided by an embodiment of the present application.
  • Figure 26 is a structural diagram of another transistor provided by an embodiment of the present application.
  • Figure 27 is a flow chart of yet another method of manufacturing a transistor provided by an embodiment of the present application.
  • Figure 28 is a structural diagram of another transistor provided by an embodiment of the present application.
  • Figure 29 is a flow chart of yet another method of manufacturing a transistor provided by an embodiment of the present application.
  • Figure 30 is a structural diagram of another transistor provided by an embodiment of the present application.
  • Figure 31 is a flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present application.
  • Figures 32 to 39 are state diagrams of the semiconductor device corresponding to the flow chart shown in Figure 31;
  • Figure 40 is a flow chart of another method for manufacturing a semiconductor device provided by an embodiment of the present application.
  • Figure 41 is a state diagram of the semiconductor device corresponding to the flow chart shown in Figure 40;
  • Figure 42 is a structural diagram of an electronic device provided by some embodiments of the present application.
  • A/B can mean A or B; "and/or” in this application "It is just an association relationship that describes related objects. It means that there can be three relationships.
  • a and/or B can mean: A exists alone, A and B exist simultaneously, and B exists alone.
  • a ,B can be singular or plural.
  • plural means two or more than two.
  • At least one of the following or similar expressions refers to any combination of these items, including single items (items) or plural items (items) any combination of.
  • at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, c can be single or multiple .
  • words such as “first” and “second” are used to distinguish identical or similar items with basically the same functions and effects. Those skilled in the art can understand that words such as “first” and “second” do not limit the number and execution order, and words such as “first” and “second” do not limit the number and execution order.
  • words such as “exemplary” or “for example” are used to represent examples, illustrations or explanations. Any embodiment or design described as “exemplary” or “such as” in the embodiments of the present application is not to be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as “exemplary” or “such as” is intended to present related concepts in a concrete manner that is easier to understand.
  • Transistor 100 includes fin 10 , gate structure 20 , source 30 and drain 40 .
  • the fin 10 includes a source region AA, a drain region BB, and a channel region CC located between the source region AA and the drain region BB.
  • the material of fin 10 may include silicon, germanium, silicon germanium, or the like. It can be understood that the material of the fin 10 in this application is not limited to this.
  • the gate structure 20 spans the channel region CC, and the gate structure 20 includes a gate dielectric layer 21 and a gate metal layer 22 .
  • the gate dielectric layer 21 is provided across the channel region CC.
  • the gate dielectric layer 21 contains aluminum atoms (ie, Al atoms), and the aluminum atoms are close to the surface of the gate dielectric layer 21 away from the channel region CC.
  • the gate metal layer 22 is located on the gate dielectric layer 21 .
  • the gate dielectric layer 21 may be a high dielectric constant layer.
  • the dielectric constant of the high dielectric constant layer is greater than 3.9.
  • the material of the high dielectric constant layer may include hafnium dioxide (HfO 2 ).
  • the material of the interface layer may include silicon oxide (SiO 2 ), for example.
  • the interface layer may be used to increase the adhesion between the gate dielectric layer 21 (or high dielectric constant layer) and the fin 10 .
  • the material of gate metal layer 22 may include a low-resistance metal.
  • the material of the gate metal layer 22 may include tungsten (W).
  • the source electrode 30 and the drain electrode 40 are respectively located on both sides of the gate structure 20.
  • the source electrode 30 is located on the source area AA
  • the drain electrode 40 is located on the drain area BB.
  • the extension direction of the fin 10 is the first direction X, that is, the direction from the source region AA to the drain region BB (or the direction from the drain region BB to the source region AA) is the first direction X
  • the extension direction of the gate structure 20 may be the second direction Y.
  • the gate structure 20 is disposed across the channel region CC of the fin 10 , that is, the first direction X and the second direction Y intersect.
  • the third direction Z is perpendicular to the first direction X and the second direction Y.
  • the specific shapes of the source electrode 30 and the drain electrode 40 are not limited.
  • the source electrode 30 and the drain electrode 40 are rectangular as an example.
  • the size of the source 30 in the second direction Y may be larger than the size of the fin 10 (or the source region AA) in the second direction Y.
  • the size of the drain electrode 40 in the second direction Y may be larger than the size of the fin 10 (or the drain region BB) in the second direction Y.
  • the gate structure 20 includes a gate dielectric layer 21 and a gate metal layer 22.
  • the gate dielectric layer 21 contains aluminum atoms, and the aluminum atoms are close to the surface of the gate dielectric layer 21 away from the channel region CC. , Therefore, a dipole can be formed on the surface of the gate dielectric layer 21 away from the channel region CC, and the dipole can be used to regulate the work function and thereby control the threshold voltage of the transistor.
  • the thickness of the gate metal layer 22 can be thicker, which is beneficial to reducing the gate resistance of the transistor 100 and improving the performance of the transistor 100 .
  • the allowable thickness range of the gate metal layer 22 can be correspondingly expanded by 4 nm.
  • the width range of the gate metal layer 22 in the first direction X can be expanded by 8 nm.
  • the transistor 100 further includes a shallow trench isolation structure 110 .
  • the shallow trench isolation structure 110 is located on both sides of the fin 10 along the second direction Y, and the shallow trench isolation structure 110 is located on both sides of the fin 10 along the second direction Y.
  • the size of the structure 110 in the third direction Z is smaller than the size of the channel region CC in the third direction Z. That is, part of the channel region CC is embedded in the shallow trench isolation structure 110 , and the remaining part of the channel region CC protrudes from the shallow trench isolation structure 110 .
  • the gate structure 20 spans the channel region CC, the gate structure 20 also covers at least part of the surface of the shallow trench isolation structure 110 .
  • the material of the shallow trench isolation structure 110 may include binary or multi-component compounds composed of silicon (Si), carbon (C), nitrogen (N), oxygen (O) and other elements.
  • it may include carbon oxynitride.
  • the material of the shallow trench isolation structure 110 may also contain one or more elements such as hydrogen (H), fluorine (F), chlorine (Cl), and the like.
  • the shallow trench isolation structure 110 can isolate the fins 10 of two adjacent transistors 100 .
  • the transistor 100 provided in the above embodiments of the present application may be an N-type field effect transistor or a P-type field effect transistor, and this application is not limited thereto.
  • the transistor 100 may be, for example, an N-type metal-oxide-semiconductor (NMOS) transistor.
  • NMOS N-type metal-oxide-semiconductor
  • PMOS P-type metal-oxide-semiconductor
  • the gate structure 20 further includes a P-type work function layer 23 .
  • the P-type work function layer 23 is located between the gate dielectric layer 21 and the gate metal layer 22 .
  • the P-type work function layer 23 is used to regulate the work function of the gate structure 20 and thereby adjust the threshold voltage of the transistor 100 .
  • the transistor 100 is an N-type field effect transistor
  • the transistor 100 is a P-type field effect transistor
  • the material of the P-type work function layer 23 may include titanium nitride (TiN).
  • the gate structure 20 since there is no need to provide an N-type work function layer between the gate dielectric layer 21 and the gate metal layer 22, when the filling space of the gate structure 20 is fixed, the gate structure 20 The allowable thickness range of other film layers in the film is larger. In this way, when the gate structure 20 also includes the P-type work function layer 23, the allowable thickness range of the P-type work function layer 23 can also be larger. Since the thickness of the P-type work function layer 23 is different from that of the transistor 100 Therefore, when the allowable thickness range of the P-type work function layer 23 is larger, the adjustable range of the threshold voltage of the transistor 100 can also be larger.
  • the semiconductor device can include more transistors 100 with different threshold voltages, thereby improving Semiconductor device performance.
  • the gate structure 20 further includes an etching barrier layer 24 , and the etching barrier layer 24 is located between the gate dielectric layer 21 and the P-type work function layer 23 .
  • the etching barrier layer 24 can be used as a stop layer in the process of etching the P-type work function layer 23, thereby avoiding the situation that the gate dielectric layer 21 is also etched during the process of etching the P-type work function layer 23.
  • the material of the etching barrier layer 24 may include tantalum nitride (TaN).
  • the gate structure 20 further includes a protective layer 25 .
  • the protective layer 25 is located between the gate dielectric layer 21 and the gate metal layer 22 and is in contact with the gate dielectric layer 21 .
  • the material of the protective layer 25 may include titanium nitride (TiN).
  • the protective layer 25 is in contact with the gate dielectric layer 21 and can also prevent the oxygen atoms in the gate dielectric layer 21 from diffusing to the outside, thereby effectively improving the efficiency of the gate dielectric layer. Oxygen atoms diffuse outward and the performance of the gate structure is reduced, causing the problem of increased gate leakage current of the transistor.
  • the gate structure 20 further includes an adhesive layer 26 .
  • the adhesive layer 26 is located between the gate dielectric layer 21 and the gate metal layer 22 and is in contact with the gate metal layer 22 .
  • the material of the adhesive layer 26 may also include titanium nitride (TiN).
  • the adhesive layer 26 is located between the gate dielectric layer 21 and the gate metal layer 22 and is in contact with the gate metal layer 22 , so that it can be used to bond the gate metal layer 22 and improve the adhesion between the gate metal layer 22 and the gate dielectric layer 21 . Efforts should be made to avoid separation between the gate metal layer and the gate dielectric layer.
  • the adhesive layer 26 can also prevent the aluminum atoms located in the gate dielectric layer 21 from diffusing outward during the subsequent process or the use of the transistor, thereby avoiding the occurrence of The problem of threshold voltage drift due to out-diffusion of aluminum atoms.
  • the gate structure 20 when the gate structure 20 includes a gate dielectric layer 21 , a gate metal layer 22 , a P-type work function layer 23 , an etching barrier layer 24 , a protective layer 25 and an adhesive layer 26 , the protective layer 25 can Located between the etching barrier layer 24 and the gate dielectric layer 21, the P-type work function layer 23 can be located between the etching barrier layer 24 and the adhesive layer 26. The adhesive layer 26 can be located between the P-type work function layer 23 and the gate metal. between layers 22.
  • the transistor 100 further includes a gate insulating layer 50 located between the gate dielectric layer 21 and the channel region CC.
  • the gate insulating layer 50 only covers the top surface of the channel region CC and part of the side surfaces close to the top surface.
  • the material of the gate insulating layer 50 may include oxide.
  • the content of the aluminum element in the gate dielectric layer 21 is higher than the content of the aluminum element in other film layers, and the other film layers at least include the gate metal layer 22 .
  • the other film layers may also include at least one of a P-type work function layer 23, an etching barrier layer 24, a protective layer 25 and an adhesive layer 26.
  • a secondary ion mass spectrometer can be used to detect metal elements (eg, hafnium, aluminum) in the gate structure 20 .
  • the secondary ion mass spectrometer uses ions to bombard the sample to ionize the sample and generate secondary ions that represent the sample components.
  • the mass spectrometer is then used to conduct qualitative and quantitative analysis of the secondary ions.
  • FIG. 7 is a diagram showing the content analysis results of aluminum element (Al) and hafnium element (Hf) in the gate structure 20 provided by the embodiment of the present application using a secondary ion mass spectrometer.
  • the ordinate represents the element intensity, and the unit is arbitrary unit (AU). From bottom to top, the element intensity gradually increases.
  • the abscissa represents the height, in nanometers (nm), and the height gradually increases from left to right.
  • hafnium element (Hf) in Figure 7 it can be seen that as the height gradually increases, the element intensity of the detected hafnium element first increases and then decreases. Since the material of the gate dielectric layer 21 includes hafnium dioxide, the abscissa corresponding to the highest point of the hafnium element intensity is the height corresponding to the gate dielectric layer 21 . According to the detection curve of aluminum element (Al) in Figure 7, it can be seen that as the height gradually increases, the element intensity of the detected aluminum element first increases and then decreases.
  • the gate dielectric layer 21 also includes an aluminum element, and the aluminum element is close to the surface of the gate dielectric layer 21 away from the channel region CC, the abscissa of the highest element intensity point of the aluminum element is equal to the abscissa of the highest element intensity point of the hafnium element. The distance between them is relatively close.
  • Figure 8 is a diagram showing the content analysis results of aluminum element (Al) and hafnium element (Hf) in the gate structure provided by the related technology using a secondary ion mass spectrometer.
  • Al aluminum element
  • Hf hafnium element
  • the detection curve of hafnium element (Hf) in Figure 8 it can be seen that as the height gradually increases, the element intensity of the detected hafnium element first increases and then decreases. Since the material of the gate dielectric layer includes hafnium dioxide, the abscissa corresponding to the highest point of the hafnium element intensity is the height corresponding to the gate dielectric layer.
  • the N-type work function layer in the related art includes Al atoms, but Al atoms are not provided in the gate dielectric layer, the element intensity of the detected aluminum element increases as the height gradually increases.
  • some embodiments of the present application provide a semiconductor device 200 .
  • the semiconductor device 200 includes a plurality of transistors.
  • the transistor is the transistor 100 described in any of the above implementations.
  • the semiconductor device 200 may further include a substrate 210 .
  • the plurality of transistors 100 are provided on the substrate 210 .
  • the material of the substrate 210 may include silicon, germanium, silicon germanium, or the like.
  • the plurality of transistors 100 include an N-type field effect transistor 101 and a P-type field effect transistor 102 .
  • the P-type field effect transistor 102 includes a P-type work function layer 23 .
  • N-type field effect transistors 101 and P-type field effect transistors 102 there is no limit to the number of N-type field effect transistors 101 and P-type field effect transistors 102 in the semiconductor device 200.
  • the distribution position on the bottom 210 is not limited, and the number and arrangement of N-type field effect transistors 101 and P-type field effect transistors 102 can be designed according to the actual needs of the semiconductor device 200.
  • the circuit structure may be a memory, a pixel circuit structure, an amplification circuit structure, a power management circuit structure, a charging protection circuit structure, a control (logic) circuit structure, and an image sensor circuit structure.
  • the embodiments of this application do not limit this.
  • the thicknesses of the P-type work function layers 23 in the multiple P-type field effect transistors 102 are not exactly the same.
  • the thicknesses of the P-type work function layers 23 in the plurality of P-type field effect transistors 102 are not exactly the same, and the work functions of the gate structures 20 in the plurality of P-type field effect transistors 102 are not exactly the same.
  • the threshold voltages of 102 are also not exactly the same, which is beneficial to realizing a multi-threshold voltage system of the semiconductor device 200 and improving the performance of the semiconductor device 200 .
  • At least one N-type field effect transistor 101 includes a P-type work function layer 23 .
  • At least one N-type field effect transistor 101 includes a P-type work function layer 23.
  • the P-type work function layer 23 can be used to regulate the work function of the gate structure 20 in the N-type field effect transistor 101, thereby adjusting the N-type field effect. threshold voltage of tube 101.
  • the plurality of N-type field effect transistors 101 include P-type work function layers 23 , and the thicknesses of the P-type work function layers 23 in the plurality of N-type field effect transistors 101 are not exactly the same.
  • the thicknesses of the P-type work function layers 23 in the multiple N-type field effect transistors 101 are not exactly the same, and the work functions of the gate structures 20 in the multiple N-type field effect transistors 101 are not exactly the same.
  • the threshold voltages of 101 are also not exactly the same, which is beneficial to realizing a multi-threshold voltage system of the semiconductor device 200 and improving the performance of the semiconductor device 200 .
  • some embodiments of the present application provide a method of manufacturing a transistor 100.
  • the preparation method includes:
  • fins 10 are formed on the substrate 210.
  • the fins 10 include a source region AA, a drain region BB, and a channel region between the source region AA and the drain region BB. CC.
  • a shallow trench isolation structure 110 may also be formed on the substrate 210.
  • an isolation layer can be formed on the substrate, and the isolation layer covers the fin 10, and then the isolation layer is planarized to expose the top surface of the fin 10, and finally the isolation layer is etched using an etch-back process to remove part of the isolation layer on both sides of the fin 10.
  • a shallow trench isolation structure 110 is formed. As shown in Figure 14, the lower end of the fin 10 is embedded in the shallow trench isolation structure 110, and the upper end of the fin 10 protrudes from the shallow trench isolation structure 110. Subsequent structures can be fabricated on the shallow trench isolation structure 110. on the trench isolation structure 110 .
  • the source electrode 30 is formed on the source region AA, and the drain electrode 40 is formed on the drain region BB.
  • an epitaxial growth process may be used to form the source electrode 30 on the source region AA and the drain electrode 40 on the drain region BB.
  • a sacrificial gate structure may be formed first, and the sacrificial gate structure may be formed across the channel region CC. . In this way, the source electrode 30 and the drain electrode 40 can be formed on both sides of the sacrificial gate structure based on the sacrificial gate structure.
  • a gate dielectric layer 21 is formed, and the gate dielectric layer 21 spans the channel region CC.
  • the gate dielectric layer 21 contains aluminum atoms (Al atoms), and the aluminum atoms are close to the surface of the gate dielectric layer 21 away from the channel region CC.
  • the above sacrificial gate structure may be removed first.
  • step S3 forming the gate dielectric layer 21 includes:
  • an initial dielectric layer 211 is formed, and the initial dielectric layer 211 spans the channel region CC.
  • the material of the initial dielectric layer 211 may include hafnium oxide.
  • an atomic layer deposition process may be used to form the initial dielectric layer 211 .
  • the N-type work function layer 27 includes aluminum atoms (Al atoms).
  • the material of the N-type work function layer 27 may include titanium aluminum carbide (TiAlC) or titanium aluminide (TiAl).
  • an annealing process is used to target and move the aluminum atoms (Al atoms) in the N-type work function layer 27 to the initial dielectric layer 211 to form the gate dielectric layer 21.
  • a high-temperature annealing process may be used to targetedly move aluminum atoms in the N-type work function layer 27 to the initial dielectric layer 211 .
  • a laser annealing process may be used to targetedly move the aluminum atoms in the N-type work function layer 27 to the initial dielectric layer 211 .
  • a microwave annealing process can be used to targetedly move the aluminum atoms in the N-type work function layer 27 to the initial dielectric layer 211 .
  • a high-temperature annealing process When a high-temperature annealing process is used to target and move the aluminum atoms in the N-type work function layer 27 to the initial dielectric layer 211, for example, a high-temperature annealing process with a furnace tube temperature of 400 degrees Celsius to 500 degrees Celsius can be used, and Control the annealing time between 10 minutes and 30 minutes.
  • a dry etching process may be used to remove the N-type work function layer 27 .
  • a wet etching process may be used to remove the N-type work function layer 27 .
  • the etching solution may include ammonia (NH 4 OH) and hydrogen peroxide (H 2 O 2 ). This application does not limit the ratio of ammonia water (NH 4 OH) and hydrogen peroxide (H 2 O 2 ) in the etching solution.
  • a gate metal layer 22 is formed on the gate dielectric layer 21 .
  • the material of the gate metal layer 22 may include tungsten (W).
  • an N-type work function layer 27 is first formed on the initial dielectric layer 211, and then an annealing process is used to target and move the aluminum atoms (Al atoms) in the N-type work function layer 27. After reaching the initial dielectric layer 211 , the gate dielectric layer 21 is formed, and finally the N-type work function layer 27 is removed, so that the N-type work function layer 27 is not finally provided in the gate structure 20 .
  • the allowable thickness range of other film layers in the gate structure can be larger.
  • the thickness of the gate metal layer 22 can be thicker, which is beneficial to reducing the gate resistance of the transistor 100 and improving the performance of the transistor 100 .
  • the preparation method further includes:
  • the P-type work function layer 23 can be formed on the initial dielectric layer 211.
  • the material of the P-type work function layer 23 may include titanium nitride (TiN).
  • the preparation method further includes:
  • the etching barrier layer 24 may be formed on the initial dielectric layer 211.
  • the material of the etching barrier layer 24 may include tantalum nitride (TaN).
  • the preparation method further includes:
  • the protective layer 25 is formed on the initial dielectric layer 211.
  • the preparation method further includes:
  • an adhesive layer 26 is formed on the gate dielectric layer 21.
  • the adhesive layer 26 can be formed on the gate dielectric layer 21.
  • the preparation method may further include:
  • a gate insulating layer 50 is formed, and the gate insulating layer 50 is disposed across the channel region CC.
  • the gate insulation may be formed after forming the fins 10 on the substrate 210 in step S1, and before forming the source electrode 30 on the source region AA and forming the drain electrode 40 on the drain region BB in step S2.
  • Layer 50 may be formed after forming the fins 10 on the substrate 210 in step S1, and before forming the source electrode 30 on the source region AA and forming the drain electrode 40 on the drain region BB in step S2.
  • some embodiments of the present application provide a method of manufacturing a semiconductor device 200 .
  • the preparation method includes:
  • the substrate 210 includes an N-type field effect transistor region W1 and a P-type field effect transistor region W2.
  • the substrate 210 may include an N-type field effect transistor region W1 and a P-type field effect transistor region W2.
  • the semiconductor device 200 may include an N-type field effect transistor 101 and a P-type field effect transistor 102.
  • the substrate 210 may include multiple N-type field effect transistor regions W1 and multiple P-type field effect transistor regions W2.
  • the semiconductor device 200 may include multiple N-type field effect transistors 101 and multiple P-type field effect transistors 102 .
  • the plurality of N-type field effect transistors 101 and the plurality of P-type field effect transistors 102 can be electrically connected to form at least one circuit structure, so as to realize different functions.
  • the substrate 210 includes multiple N-type field effect transistor regions W1 and multiple P-type field effect transistor regions W2, the distribution of the multiple N-type field effect transistor regions W1 and the multiple P-type field effect transistor regions W2 is not specified in this application. Limitations can be set according to actual needs.
  • a plurality of fins 10 are formed on the substrate 210.
  • the fins 10 include a source region AA, a drain region BB, and a trench between the source region AA and the drain region BB.
  • Road District CC The plurality of fins 10 include a first fin 11 located in the N-type field effect transistor region W1 and a second fin 12 located in the P-type field effect transistor region W2.
  • the source electrode 30 is formed on the source region AA
  • the drain electrode 40 is formed on the drain region BB.
  • an initial dielectric layer 211 is formed, and the initial dielectric layer 211 spans the channel region CC.
  • the initial dielectric layer 211 spans the channel region CC may mean that as shown in FIG. 34 , the initial dielectric layer 211 spans the channel regions CC of the plurality of fins 10 .
  • the initial dielectric layer 211 may be disposed across the channel regions CC of the plurality of first fins 11 and the plurality of second fins 12 at the same time, or the initial dielectric layer 211 may be disposed across the channels of the plurality of first fins 11 at the same time. on the channel area CC, or the initial dielectric layer 211 may be disposed across the channel area CC of multiple second fins 12 at the same time.
  • a P-type work function layer 23 is formed on the initial dielectric layer 211.
  • the P-type work function layer 23 is at least located in the P-type field effect transistor region W2.
  • the P-type work function layer 23 is at least located in the P-type field effect transistor region W2", which can be as shown in Figure 35, P The P-type work function layer 23 is only located in the P-type field effect transistor region W2. Alternatively, the P-type work function layer 23 is located in the P-type field effect transistor region W2 and the N-type field effect transistor region W1.
  • an N-type work function layer 27 is formed on the P-type work function layer 23.
  • the N-type work function layer 27 is located in the N-type field effect transistor area W1 and the P-type field effect transistor area W2, and the N-type work function layer 27 is located in the N-type field effect transistor area W1 and the P-type field effect transistor area W2.
  • Aluminum atoms Al atoms are included in layer 27 .
  • an annealing process is used to target and move the aluminum atoms in the N-type work function layer 27 to the initial dielectric layer 211 to form the gate dielectric layer 21.
  • the aluminum atoms are close to the surface of the gate dielectric layer 21 away from the channel region CC.
  • a gate metal layer 22 is formed on the P-type work function layer 23.
  • step S500 forming the P-type work function layer 23 on the initial dielectric layer 211, includes:
  • the first intermediate P-type work function layer 231 may be patterned using a photolithography process.
  • the target thickness of the P-type work function layer 23 in different transistors 100 can be designed according to the required threshold voltages of the different transistors 100 . There are no specific restrictions on the value of the target thickness in this application.
  • the thickness of the first intermediate P-type work function layer 231 and the thickness of the second intermediate P-type work function layer 232 may be the same. In other examples, the thickness of the first intermediate P-type work function layer 231 and the thickness of the second intermediate P-type work function layer 232 may be different.
  • the thickness of the first intermediate P-type work function layer 231 and the thickness of the second intermediate P-type work function layer 232 there is no limit on the thickness of the first intermediate P-type work function layer 231 and the thickness of the second intermediate P-type work function layer 232.
  • the thickness of the first intermediate P-type work function layer 231 may be 10 Angstroms ⁇ 5 Angstroms.
  • the thickness of the second intermediate P-type work function layer 232 may be 10 Angstroms ⁇ 5 Angstroms.
  • the electronic device 1000 is, for example, a consumer electronic product, a household electronic product, a vehicle-mounted electronic product, or a financial terminal product.
  • consumer electronic products include mobile phones, tablets, laptops, e-readers, personal computers (PC), personal digital assistants (PDA), desktop monitors, Smart wearable products (such as smart watches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc.
  • Home electronic products include smart door locks, TVs, remote controls, refrigerators, rechargeable small household appliances (such as soymilk machines, sweeping robots), etc.
  • Vehicle-mounted electronic products include car navigation systems, car DVDs, etc.
  • Financial terminal products include ATM machines, self-service terminals, etc. The embodiment of the present application does not place any special restrictions on the specific form of the electronic device 1000 mentioned above.
  • the above-mentioned electronic device 1000 may include components such as a semiconductor device 200 and a printed circuit board (PCB) 300.
  • the semiconductor device 200 and the printed circuit board 300 are electrically connected to achieve signal interoperability.

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Abstract

本申请提供一种晶体管及其制备方法、半导体器件及其制备方法，涉及半导体技术领域，用于改善因半导体器件尺寸减小，所带来的晶体管的栅结构中各个膜层厚度受限的问题。晶体管包括鳍、栅介质层、栅金属层、源极和漏极。鳍包括源极区、漏极区，以及位于源极区和漏极区之间的沟道区。栅介质层跨设在沟道区上。栅介质层含有铝原子，且铝原子靠近栅介质层远离沟道区的表面。栅金属层位于栅介质层上。源极位于源极区上，漏极位于漏极区上。上述晶体管应用于半导体器件中，以提高半导体器件的性能。

Description

晶体管及其制备方法、半导体器件及其制备方法
本申请要求于2022年04月15日提交国家知识产权局、申请号为202210398540.4、申请名称为“晶体管及其制备方法、半导体器件及其制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体技术领域，尤其涉及晶体管及其制备方法、半导体器件及其制备方法。
背景技术
在半导体器件中，常采用具有高介电常数金属栅(High K Metal Gate，HKMG)的鳍式场效应晶体管(Fin Field-Effect-Transistor，FinFET)作为晶体管单元。HKMG可以包括栅介质层和栅金属层，以及位于栅介质层和栅金属层之间的P型功函数层和N型功函数层。可以通过控制P型功函数层的厚度，控制晶体管的阈值电压(threshold voltage)。
随着半导体器件的尺寸的日益减小，晶体管的尺寸也随之减小。例如，在7nm的半导体工艺节点中，HKMG的栅长度(gate length)已微缩至20nm左右。栅长度限制了HKMG中多个膜层的填充空间。
发明内容
本申请实施例提供一种晶体管及其制备方法、半导体器件及其制备方法、电子设备，用于改善因半导体器件尺寸减小，所带来的晶体管的栅结构中各个膜层厚度受限的问题。
为达到上述目的，本申请的实施例采用如下技术方案：
第一方面，提供了一种晶体管，该晶体管包括鳍、栅介质层、栅金属层，源极和漏极。所述鳍包括源极区、漏极区，以及位于所述源极区和所述漏极区之间的沟道区。栅介质层跨设在所述沟道区上，所述栅介质层含有铝原子，且所述铝原子靠近所述栅介质层远离所述沟道区的表面。栅金属层位于所述栅介质层上。所述源极位于所述源极区上，所述漏极位于所述漏极区上。
本申请的上述实施例所提供的晶体管中，栅介质层含有铝原子，且所述铝原子靠近栅介质层远离沟道区的表面，从而能够在栅介质层远离沟道区的表面形成偶极子，利用该偶极子调控功函数，进而控制晶体管的阈值电压。栅介质层和栅金属层之间无需设置用于提供铝原子的N型功函数层。这样，在栅结构的填充空间固定的情况下，栅结构中其他膜层(例如，栅介质层和栅金属层)的允许厚度范围可以较大。其中，在栅金属层的允许厚度范围较大的情况下，栅金属层的厚度可以较厚，从而有利于降低晶体管的栅极电阻，提高晶体管的性能。
在一些实施例中，所述晶体管还包括P型功函数层，P型功函数层位于所述栅介质层和所述栅金属层之间。由于栅介质层和栅金属层之间无需设置N型功函数层，因此在栅结构的填充空间固定的情况下，栅结构中其他膜层的允许厚度范围较大。这样， 在晶体管还包括P型功函数层的情况下，P型功函数层的允许厚度范围也可以较大。由于P型功函数层的厚度与晶体管的阈值电压相关，因此，在P型功函数层的允许厚度范围较大的情况下，晶体管的阈值电压的可调范围也可以较大。这样，在将晶体管应用至半导体器件中后，通过设置晶体管中P型功函数层的厚度不同，半导体器件中可以包括更多具有不同阈值电压的晶体管，从而提高半导体器件的性能。
在一些实施例中，所述晶体管还包括刻蚀阻挡层，刻蚀阻挡层位于所述栅介质层和所述P型功函数层之间。刻蚀阻挡层可以作为刻蚀P型功函数层过程中的停止层，从而避免在刻蚀P型功函数层过程中，栅介质层也被刻蚀的情况出现。
在一些实施例中，所述晶体管还包括保护层。保护层位于所述栅介质层和所述栅金属层之间，且与所述栅介质层接触。本申请实施例在栅结构中设置保护层，在栅介质层的材料包括氧原子的情况下，保护层与栅介质层接触，还可以防止栅介质层中的氧原子向外部扩散，从而有效的改善因栅介质层中氧原子向外扩散，栅结构性能降低，导致晶体管的栅极漏电流增大的问题。
在一些实施例中，所述晶体管还包括粘接层，粘接层位于所述栅介质层和所述栅金属层之间，且与所述栅金属层接触。这样，粘接层位于栅介质层和栅金属层之间，且与栅金属层接触，从而可以用于粘接栅金属层，提高栅金属层与栅介质层之间的附着力，避免栅金属层与栅介质层之间分离的情况出现。
在一些实施例中，所述栅介质层的材料包括二氧化铪。
在一些实施例中，所述栅介质层中的铝元素的含量高于其他膜层的铝元素的含量，所述其他膜层至少包括所述栅金属层。
在一些实施例中，所述晶体管还包括栅绝缘层，栅绝缘层位于所述栅结构和所述沟道区之间。
第二方面，提供了一种半导体器件，该半导体器件包括衬底以及所述衬底上设置的多个晶体管，所述晶体管为如上述任一实施例所述的晶体管。
在一些实施例中，所述多个晶体管包括N型场效应管和P型场效应管，所述P型场效应管包括P型功函数层。
在一些实施例中，多个所述P型场效应管中的P型功函数层的厚度不完全相同。这样设置，使得多个P型场效应管中栅结构的功函数不完全相同，多个P型场效应管的阈值电压也不完全相同，从而有利于实现半导体器件的多阈值电压体系，提高半导体器件的性能。
在一些实施例中，至少一个所述N型场效应管包括P型功函数层。
在一些实施例中，多个所述N型场效应管包括P型功函数层，且多个所述N型场效应管中的P型功函数层的厚度不完全相同。这样，多个N型场效应管中栅结构的功函数不完全相同，多个N型场效应管的阈值电压也不完全相同，从而有利于实现半导体器件的多阈值电压体系，提高半导体器件的性能。
第三方面，提供一种晶体管的制备方法，该制备方法包括：在衬底上形成鳍，所述鳍包括源极区、漏极区，以及位于所述源极区和所述漏极区之间的沟道区。在所述源极区上形成源极，在所述漏极区上形成所述漏极；形成栅介质层，所述栅介质层跨设在所述沟道区上；所述栅介质层含有铝原子，且所述铝原子靠近所述栅介质层远离 所述沟道区的表面；在所述栅介质层上形成栅金属层。
在一些实施例中，所述形成栅介质层，包括：形成初始介质层，所述初始介质层跨设在所述沟道区上；在所述初始介质层上形成N型功函数层，所述N型功函数层中包括铝原子；采用退火工艺，将所述N型功函数层中的铝原子靶向移动至所述初始介质层，形成所述栅介质层；去除所述N型功函数层。
在一些实施例中，所述制备方法还包括：在所述初始介质层上形成N型功函数层之前，在所述初始介质层上形成P型功函数层。
在一些实施例中，所述制备方法还包括：在所述初始介质层上形成P型功函数层之前，在所述初始介质层上形成刻蚀阻挡层。
在一些实施例中，所述制备方法还包括：在所述形成初始介质层之后，在所述初始介质层上形成保护层。
在一些实施例中，所述制备方法还包括：在所述栅介质层上形成粘接层。
在一些实施例中，所述在衬底上形成鳍之后，且在所述形成栅介质层之前，所述制备方法还包括：形成栅绝缘层，所述栅绝缘层跨设在所述沟道区上。
第四方面，提供一种半导体器件的制备方法，该制备方法包括：提供衬底，所述衬底包括N型场效应管区和P型场效应管区。在所述衬底上形成多个鳍，所述鳍包括源极区、漏极区，以及位于所述源极区和所述漏极区之间的沟道区；所述多个鳍包括位于所述N型场效应管区的第一鳍，和位于所述P型场效应管区的第二鳍。在所述源极区上形成源极，在所述漏极区上形成漏极；形成初始介质层，所述初始介质层跨设在所述沟道区上。在所述初始介质层上形成P型功函数层，所述P型功函数层至少位于所述P型场效应管区。在所述P型功函数层上形成N型功函数层，所述N型功函数层位于N型场效应管区和所述P型场效应管区，且所述N型功函数层中包括铝原子。采用退火工艺，将所述N型功函数层中的铝原子靶向移动至所述初始介质层，形成所述栅介质层。所述铝原子靠近所述栅介质层远离所述沟道区的表面。去除所述N型功函数层。在所述P型功函数层上形成所述栅金属层。
在一些实施例中，所述在所述初始介质层上形成P型功函数层，包括：在所述初始介质层上形成第一中间P型功函数层；图案化第一中间P型功函数层；在图案化后的第一中间P型功函数层上形成第二中间P型功函数层；重复至少一次上述步骤，直至多个晶体管的P型功函数层达到目标厚度。
第五方面，提供了一种电子设备，该电子设备包括印刷电路板，和如上述任一实施例所述的半导体器件；所述半导体器件和所述印刷电路板电连接。
其中，第二方面至五方面中任一种实施例所带来的技术效果可参见第一方面中不同实施例所带来的技术效果，在此不再赘述。
附图说明
图1A为本申请实施例提供的一种晶体管的立体图；
图1B为本申请实施例提供的一种晶体管的俯视图；
图2为图1A所示的晶体管在D-D’处的一种截面图；
图3为图1A所示的晶体管在E-E’处的截面图；
图4为图1A所示的晶体管在D-D’处的另一种截面图；
图5为图1A所示的晶体管在D-D’处的再一种截面图；
图6为图1A所示的晶体管在D-D’处的又一种截面图；
图7为利用二次离子质谱仪对一种晶体管中铝元素和铪元素的检测结果图；
图8为利用二次离子质谱仪对另一种晶体管中铝元素和铪元素的检测结果图；
图9为本申请实施例提供的一种半导体器件的立体图；
图10为本申请实施例提供的一种半导体器件的俯视图；
图11为图10所示的半导体器件在F-F’处的一种截面图；
图12为图10所示的半导体器件在F-F’处的另一种截面图；
图13为本申请实施例提供的一种晶体管的制备方法的流程图；
图14为本申请实施例提供的另一种晶体管的立体图；
图15为本申请实施例提供的一种晶体管的俯视图；
图16为本申请实施例提供的一种晶体管的结构图；
图17为本申请实施例提供的另一种晶体管的制备方法的流程图；
图18为本申请实施例提供的另一种晶体管的结构图；
图19为本申请实施例提供的再一种晶体管的结构图；
图20为本申请实施例提供的又一种晶体管的结构图；
图21为本申请实施例提供的再一种晶体管的制备方法的流程图；
图22为本申请实施例提供的又一种晶体管的结构图；
图23为本申请实施例提供的又一种晶体管的制备方法的流程图；
图24为本申请实施例提供的又一种晶体管的结构图；
图25为本申请实施例提供的又一种晶体管的制备方法的流程图；
图26为本申请实施例提供的又一种晶体管的结构图；
图27为本申请实施例提供的又一种晶体管的制备方法的流程图；
图28为本申请实施例提供的又一种晶体管的结构图；
图29为本申请实施例提供的又一种晶体管的制备方法的流程图；
图30为本申请实施例提供的又一种晶体管的结构图；
图31为本申请实施例提供的一种半导体器件的制备方法的流程图；
图32～图39为图31所示的流程图对应的半导体器件的状态图；
图40为本申请实施例提供的另一种半导体器件的制备方法的流程图；
图41为图40所示的流程图所对应的半导体器件的状态图；
图42为本申请一些实施例提供的一种电子设备的结构图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述。其中，在本申请的描述中，除非另有说明，“/”表示前后关联的对象是一种“或”的关系，例如，A/B可以表示A或B；本申请中的“和/或”仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况，其中A,B可以是单数或者复数。
并且，在本申请的描述中，除非另有说明，“多个”是指两个或多于两个。“以下至少一项(个)”或其类似表达，是指的这些项中的任意组合，包括单项(个)或复数项(个) 的任意组合。例如，a，b，或c中的至少一项(个)，可以表示：a，b，c，a-b，a-c，b-c，或a-b-c，其中a，b，c可以是单个，也可以是多个。
另外，为了便于清楚描述本申请实施例的技术方案，在本申请的实施例中，采用了“第一”、“第二”等字样对功能和作用基本相同的相同项或相似项进行区分。本领域技术人员可以理解“第一”、“第二”等字样并不对数量和执行次序进行限定，并且“第一”、“第二”等字样也并不限定一定不同。
同时，在本申请实施例中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请实施例中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其它实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念，便于理解。
如图1A～图3所示，本申请一些实施例提供了一种晶体管100。晶体管100包括鳍10、栅结构20，源极30和漏极40。
其中，鳍10包括源极区AA、漏极区BB，以及位于源极区AA和漏极区BB之间的沟道区CC。
在一些示例中，鳍10的材料可以包括硅、锗、或锗硅等。可以理解，本申请中鳍10的材料并不仅限于此。
栅结构20跨设在沟道区CC上，栅结构20包括栅介质层21和栅金属层22。其中，栅介质层21跨设在沟道区CC上。栅介质层21中含有铝原子(即，Al原子)，且铝原子靠近栅介质层21远离沟道区CC的表面。栅金属层22，位于栅介质层21上。
在一些示例中，栅介质层21可以为高介电常数层。示例性的，高介电常数层的介电常数大于3.9。例如，高介电常数层的材料可以包括二氧化铪(HfO2)。
示例性的，在栅介质层21与鳍10之间还可以具有界面层，界面层的材料例如可以包括氧化硅(SiO2)。界面层可以用于增加栅介质层21(或高介电常数层)和鳍10之间的附着力。
在一些示例中，栅金属层22的材料可以包括低电阻金属。例如，栅金属层22的材料可以包括钨(W)。
源极30和漏极40分别位于栅结构20两侧，且源极30位于源极区AA上，漏极40位于漏极区BB上。
示例性的，鳍10的延伸方向为第一方向X，也即由源极区AA指向漏极区BB的方向(或由漏极区BB指向源极区AA的方向)为第一方向X，栅结构20的延伸方向可以为第二方向Y，栅结构20跨设在鳍10的沟道区CC上，也即第一方向X与第二方向Y相交叉。第三方向Z垂直于第一方向X和第二方向Y。
本申请中对源极30和漏极40的具体形状不做限制，图1A中仅以源极30和漏极40呈长方体为例进行示意。
在一些示例中，如图1A和图1B所示，源极30在第二方向Y上的尺寸可以大于鳍10(或者源极区AA)在第二方向Y上的尺寸。漏极40在第二方向Y上的尺寸可以大于鳍10(或者漏极区BB)在第二方向Y上的尺寸。
本申请的上述实施例所提供的晶体管100中，栅结构20包括栅介质层21和栅金属层22，栅介质层21含有铝原子，且铝原子靠近栅介质层21远离沟道区CC的表面， 从而能够在栅介质层21远离沟道区CC的表面形成偶极子，利用该偶极子调控功函数，进而控制晶体管的阈值电压。栅介质层21和栅金属层22之间无需设置用于提供铝原子的N型功函数层。这样，在栅结构20的填充空间固定的情况下，栅结构20中其它膜层(例如，栅介质层21和栅金属层22)的允许厚度范围可以较大。
在栅金属层22的允许厚度范围较大的情况下，栅金属层22的厚度可以较厚，从而有利于降低晶体管100的栅极电阻，提高晶体管100的性能。
示例性的，在N型功函数层的厚度为4nm的情况下，本申请中不设置N型功函数层，可以使栅金属层22的允许厚度范围相应的扩大4nm。同时，参阅图3，栅金属层22在第一方向X上的宽度范围可以扩大8nm。
在一些实施例中，如图1A和图2所示，晶体管100还包括浅沟槽隔离结构110，沿第二方向Y，浅沟槽隔离结构110位于鳍10的两侧，且浅沟槽隔离结构110在第三方向Z上的尺寸小于沟道区CC在第三方向Z上的尺寸。也即，沟道区CC的部分嵌入浅沟槽隔离结构110内，沟道区CC的其余部分凸出于浅沟槽隔离结构110。
在栅结构20跨设在沟道区CC上的情况下，栅结构20还覆盖浅沟槽隔离结构110的至少部分表面。
示例性的，浅沟槽隔离结构110的材料可以包括硅(Si)、碳(C)、氮(N)、氧(O)等元素组成的二元或多元化合物，例如可以包括碳氧氮化硅(SiCxOyNz)、碳氧化硅(SiCxOy)、氮化硅(SiNx)、氧化硅(SiOx)或氮氧化硅(SiOxNy)中的至少一种。或者，浅沟槽隔离结构110的材料还可以含有氢(H)、氟(F)、氯(Cl)等元素中的一种或多种。
当多个晶体管100同时布置在同一半导体器件中时，浅沟槽隔离结构110可以将相邻的两个晶体管100的鳍10隔离开来。
可以理解，本申请上述实施例所提供的晶体管100可以是N型场效应晶体管，也可以是P型场效应晶体管，本申请对此不做限制。当晶体管100为N型场效应晶体管时，晶体管100例如可以是N型金属-氧化物-半导体(N Metal-Oxide-Semiconductor，NMOS)晶体管。当晶体管100为P型场效应晶体管时，晶体管100例如可以是P型金属-氧化物-半导体(P Metal-Oxide-Semiconductor，PMOS)晶体管。
在一些实施例中，如图4所示，栅结构20还包括P型功函数层23。P型功函数层23位于栅介质层21和栅金属层22之间。
其中，P型功函数层23用于调控栅结构20的功函数，进而调整晶体管100的阈值电压。示例性的，在晶体管100为N型场效应晶体管的情况下，P型功函数层23的厚度越大，栅结构20的功函数越大，晶体管100的阈值电压越大。在晶体管100为P型场效应晶体管的情况下，P型功函数层23的厚度越大，栅结构20的功函数越大，晶体管100的阈值电压越小。
示例性的，P型功函数层23的材料可以包括氮化钛(TiN)。
本申请的上述实施例所提供的栅结构20中，由于栅介质层21和栅金属层22之间无需设置N型功函数层，因此在栅结构20的填充空间固定的情况下，栅结构20中其他膜层的允许厚度范围较大。这样，在栅结构20还包括P型功函数层23的情况下，P型功函数层23的允许厚度范围也可以较大。由于P型功函数层23的厚度与晶体管100 的阈值电压相关，因此，在P型功函数层23的允许厚度范围较大的情况下，晶体管100的阈值电压的可调范围也可以较大。这样，在将本申请所提供的晶体管100应用至半导体器件中后，通过设置晶体管100中P型功函数层23的厚度不同，半导体器件中可以包括更多具有不同阈值电压的晶体管100，从而提高半导体器件的性能。
在一些实施例中，如图5所示，栅结构20还包括刻蚀阻挡层24，刻蚀阻挡层24位于栅介质层21和P型功函数层23之间。其中，刻蚀阻挡层24可以作为刻蚀P型功函数层23过程中的停止层，从而避免在刻蚀P型功函数层23过程中，栅介质层21也被刻蚀的情况出现。
示例性的，刻蚀阻挡层24的材料可以包括氮化钽(TaN)。
在一些实施例中，如图6所示，栅结构20还包括保护层25。保护层25位于栅介质层21和栅金属层22之间，且与栅介质层21接触。
示例性的，保护层25的材料可以包括氮化钛(TiN)。
其中，在栅介质层21的材料包括氧原子的情况下，保护层25与栅介质层21接触，还可以防止栅介质层21中的氧原子向外部扩散，从而有效的改善因栅介质层中氧原子向外扩散，栅结构性能降低，导致晶体管的栅极漏电流增大的问题。
在一些实施例中，如图6所示，栅结构20还包括粘接层26，粘接层26位于栅介质层21和栅金属层22之间，且与栅金属层22接触。
示例性的，粘接层26的材料也可以包括氮化钛(TiN)。
粘接层26位于栅介质层21和栅金属层22之间，且与栅金属层22接触，从而可以用于粘接栅金属层22，提高栅金属层22与栅介质层21之间的附着力，避免栅金属层与栅介质层之间分离的情况出现。
同时，在粘接层26覆盖在栅介质层21上的情况下，粘接层26还可以防止后续工艺过程或晶体管使用过程中，位于栅介质层21内的铝原子向外扩散，从而避免出现因铝原子向外扩散导致阈值电压漂移的问题。
如图6所示，在栅结构20包括栅介质层21、栅金属层22、P型功函数层23、刻蚀阻挡层24、保护层25和粘接层26的情况下，保护层25可以位于刻蚀阻挡层24和栅介质层21之间，P型功函数层23可以位于刻蚀阻挡层24与粘接层26之间，粘接层26可以位于P型功函数层23与栅金属层22之间。
在一些实施例中，如图6所示，晶体管100还包括栅绝缘层50，位于栅介质层21和沟道区CC之间。其中，参阅图6，栅绝缘层50仅覆盖沟道区CC的顶面和靠近顶面的部分侧面。
示例性的，栅绝缘层50的材料可以包括氧化物。
在一些实施例中，栅介质层21中的铝元素的含量高于其他膜层的铝元素的含量，所述其他膜层至少包括栅金属层22。
示例性的，所述其他膜层还可以包括P型功函数层23、刻蚀阻挡层24，保护层25和粘接层26中的至少一个。
示例性的，可以采用二次离子质谱仪对栅结构20中的金属元素(例如铪、铝)进行检测。二次离子质谱仪是使用离子对样品进行轰击，使样品被电离，产生代表样品成分的二次离子，进而使用质谱仪对二次离子进行定性和定量分析。
图7为利用二次离子质谱仪对本申请实施例所提供的栅结构20中铝元素(Al)和铪元素(Hf)的含量分析结果图。其中，纵坐标表征元素强度，单位为任意单位(arbitrary unit，AU)，由下到上，元素强度逐渐加强。横坐标表征高度，单位为纳米(nm)，从左向右，高度逐渐升高。
根据图7中铪元素(Hf)的检测曲线可知，随着高度逐渐升高，检测到的铪元素的元素强度先升高后降低。由于栅介质层21的材料包括二氧化铪，因此，铪元素强度最高点所对应的横坐标即为栅介质层21所对应的高度。根据图7中铝元素(Al)的检测曲线可知，随着高度逐渐升高，检测到的铝元素的元素强度先增高后降低。由于栅介质层21中还包括铝元素，且铝元素靠近栅介质层21远离沟道区CC的表面，因此铝元素的元素强度最高点的横坐标与铪元素的元素强度最高点的横坐标之间的距离较近。
图8为利用二次离子质谱仪对相关技术所提供的栅结构中铝元素(Al)和铪元素(Hf)的含量分析结果图。根据图8中铪元素(Hf)的检测曲线可知，随着高度逐渐升高，检测到的铪元素的元素强度先升高后降低。由于栅介质层的材料包括二氧化铪，因此，铪元素强度最高点所对应的横坐标即为栅介质层所对应的高度。然而，由于相关技术中N型功函数层包括Al原子，而在栅介质层中不设置Al原子，因此随着高度逐渐升高，检测到的铝元素的元素强度一直升高。
如图9所示，本申请的一些实施例提供了一种半导体器件200。半导体器件200中包括多个晶体管。晶体管为上述任一实施所述的晶体管100。
本申请一些实施例中对晶体管100的数目不做限制，只要保证能够实现半导体器件200所要实现的功能即可。
示例性的，参阅图9和图10，半导体器件200还可以包括衬底210。所述多个晶体管100设置在衬底210上。
示例性的，衬底210的材料可以包括硅、锗、或锗硅等。
如图11所示，多个晶体管100包括N型场效应管101和P型场效应管102，P型场效应管102包括P型功函数层23。
本申请一些实施例中，对半导体器件200中的N型场效应管101的数目和P型场效应管102的数目不做限制，对N型场效应管101和P型场效应管102在衬底210上的分布位置也不做限制，可以根据半导体器件200的实际需求设计N型场效应管101和P型场效应管102的数目和排布方式。
半导体器件200中的多个晶体管100可以用于形成多个电路结构，该电路结构可以用于实现不同的功能。示例性的，该电路结构可以为存储器、像素电路结构、放大电路结构、电源管理电路结构、充电保护电路结构、控制(逻辑)电路结构和图像传感器电路结构。本申请实施例对此不做限制。
在一些实施例中，多个P型场效应管102中的P型功函数层23的厚度不完全相同。
这样，多个P型场效应管102中的P型功函数层23的厚度不完全相同，多个P型场效应管102中栅结构20的功函数不完全相同，多个P型场效应管102的阈值电压也不完全相同，从而有利于实现半导体器件200的多阈值电压体系，提高半导体器件200的性能。
在一些实施例中，如图12所示，至少一个N型场效应管101包括P型功函数层23。
其中，至少一个N型场效应管101包括P型功函数层23，可以是仅一个N型场效应管101包括P型功函数层23，也可以是多个N型场效应管101包括P型功函数层23。
通过在至少一个N型场效应管101中设置P型功函数层23，从而可以利用P型功函数层23调控N型场效应管101中的栅结构20的功函数，从而调整N型场效应管101的阈值电压。
在一些实施例中，多个N型场效应管101包括P型功函数层23，且多个N型场效应管101中的P型功函数层23的厚度不完全相同。
这样，多个N型场效应管101中的P型功函数层23的厚度不完全相同，多个N型场效应管101中栅结构20的功函数不完全相同，多个N型场效应管101的阈值电压也不完全相同，从而有利于实现半导体器件200的多阈值电压体系，提高半导体器件200的性能。
如图13所示，本申请一些实施例提供了一种晶体管100的制备方法。该制备方法包括：
S1、如图14和图15所示，在衬底210上形成鳍10，鳍10包括源极区AA、漏极区BB，以及位于源极区AA和漏极区BB之间的沟道区CC。
示例性的，在衬底210上形成鳍10后，还可以在衬底210上形成浅沟槽隔离结构110。例如，可以在衬底上形成隔离层，隔离层覆盖鳍10，然后平坦化隔离层，暴露出鳍10的顶面，最后利用回刻工艺刻蚀隔离层去除鳍10两侧的部分隔离层，形成浅沟槽隔离结构110，其中，如图14所示，鳍10的下端嵌入浅沟槽隔离结构110，鳍10的上端凸出于浅沟槽隔离结构110，后续的结构可以制作于该浅沟槽隔离结构110上。
S2、参阅图1A和图3，在源极区AA上形成源极30，在漏极区BB上形成漏极40。示例性的，可以采用外延生长工艺在源极区AA上形成源极30和在漏极区BB上漏极40。
在一些示例中，在步骤S2、在源极区AA上形成源极30，在漏极区BB上形成漏极40之前，可以先形成牺牲栅结构，牺牲栅结构跨设在沟道区CC上。这样，能够以牺牲栅结构为基准，在牺牲栅结构的两侧形成源极30和漏极40。
S3、如图16所示，形成栅介质层21，栅介质层21跨设在沟道区CC上。栅介质层21含有铝原子(Al原子)，且铝原子靠近栅介质层21远离沟道区CC的表面。
在一些示例性中，在步骤S3、形成栅介质层21之前，可以先去除上述牺牲栅结构。
在一些实施例中，如图17所示，步骤S3、形成栅介质层21，包括：
S31、如图18所示，形成初始介质层211，初始介质层211跨设在沟道区CC上。
示例性的，初始介质层211的材料可以包括氧化铪。
示例性的，可以采用原子层沉积工艺，形成初始介质层211。
S32、如图19所示，在初始介质层211上形成N型功函数层27，N型功函数层 27中包括铝原子(Al原子)。
示例性的，N型功函数层27的材料可以包括碳化铝钛(TiAlC)或铝化钛(TiAl)。
S33、参阅图16和图20，采用退火工艺，将N型功函数层27中的铝原子(Al原子)靶向移动至初始介质层211，形成栅介质层21。
在一些示例中，可以采用高温退火工艺，将N型功函数层27中的铝原子靶向移动至初始介质层211。在另一些示例中，可以采用激光退火工艺，将N型功函数层27中的铝原子靶向移动至初始介质层211。在又一些示例中，可以采用微波退火工艺，将N型功函数层27中的铝原子靶向移动至初始介质层211。
在采用高温退火工艺，将N型功函数层27中的铝原子靶向移动至初始介质层211的情况下，示例性的，可以使用炉管温度为400摄氏度～500摄氏度的高温退火工艺，并将退火时间控制在10分钟～30分钟。
S34、参阅图16和图20，去除N型功函数层27。
在一些示例中，可以采用干法刻蚀工艺去除N型功函数层27。在又一些示例中，可以采用湿法刻蚀工艺去除N型功函数层27。
当采用湿法刻蚀工艺去除N型功函数层27时，刻蚀液可以包括氨水(NH4OH)和双氧水(H2O2)。本申请对刻蚀液中氨水(NH4OH)和过氧化氢(H2O2)的比例不做限制。
S4、参阅图2，在栅介质层21上形成栅金属层22。
示例性的，栅金属层22的材料可以包括钨(W)。
本申请上述所提供的晶体管的制备方法中，先在初始介质层211上形成N型功函数层27，然后采用退火工艺，将N型功函数层27中的铝原子(Al原子)靶向移动至初始介质层211，形成栅介质层21，最后去除N型功函数层27，使得栅结构20内最终不设置N型功函数层27。这样，在栅结构的填充空间固定的情况下，栅结构中其他膜层的允许厚度范围可以较大。其中，在栅金属层22的允许厚度范围较大的情况下，栅金属层22的厚度可以较厚，从而有利于降低晶体管100的栅极电阻，提高晶体管100的性能。
在一些实施例中，如图21所示，制备方法还包括：
S35、如图22所示，在初始介质层211上形成P型功函数层23。
示例性的，可以在步骤S32、在初始介质层211上形成N型功函数层27之前，在初始介质层211上形成P型功函数层23。
示例性的，P型功函数层23的材料可以包括氮化钛(TiN)。
在一些实施例中，如图23所示，制备方法还包括：
S36、如图24所示，在初始介质层211上形成刻蚀阻挡层24。
示例性的，可以在S35、在初始介质层211上形成P型功函数层23之前，在初始介质层211上形成刻蚀阻挡层24。
示例性的，刻蚀阻挡层24的材料可以包括氮化钽(TaN)。
在一些实施例中，如图25所示，制备方法还包括：
S37、如图26所示，在初始介质层211上形成保护层25。
示例性的，可以在步骤S31、形成初始介质层211之后，在初始介质层211上形 成保护层25。
在一些实施例中，如图27所示，制备方法还包括：
S38、如图28所示，在栅介质层21上形成粘接层26。
示例性的，可以在步骤S4、在栅介质层21上形成栅金属层22之前，在栅介质层21上形成粘接层26。
在一些实施例中，如图29所示，在步骤S1、在衬底210上形成鳍10之后，且在步骤S3、形成栅介质层21之前，制备方法还可以包括：
S5、如图30所示，形成栅绝缘层50，栅绝缘层50跨设在沟道区CC上。
在一些示例中，可以在步骤S1、在衬底210上形成鳍10之后，且步骤S2、在源极区AA上形成源极30，在漏极区BB上形成漏极40之前，形成栅绝缘层50。
如图31所示，本申请一些实施例提供了一种半导体器件200的制备方法。该制备方法包括：
S100、如图32所示，提供衬底210，衬底210包括N型场效应管区W1和P型场效应管区W2。
本申请中对衬底210所包括的N型场效应管区W1和P型场效应管区W2的数量不做限制。示例性的，如图32所示，衬底210可以包括一个N型场效应管区W1和一个P型场效应管区W2。基于此，半导体器件200中可以包括一个N型场效应管101和一个P型场效应管102。
或者，示例性的，衬底210中可以包括多个N型场效应管区W1和多个P型场效应管区W2。基于此，半导体器件200中可以包括多个N型场效应管101和多个P型场效应管102。此时，多个N型场效应管101和多个P型场效应管102之间可以通过电连接形成至少一个电路结构，从而用于实现不同的功能。
在衬底210包括多个N型场效应管区W1和多个P型场效应管区W2的情况下，本申请中对多个N型场效应管区W1和多个P型场效应管区W2的分布不做限制，可以根据实际需求进行设置。
S200、如图33A和图33B所示，在衬底210上形成多个鳍10，鳍10包括源极区AA、漏极区BB，以及位于源极区AA和漏极区BB之间的沟道区CC。多个鳍10包括位于N型场效应管区W1的第一鳍11，和位于P型场效应管区W2的第二鳍12。
S300、参阅图9和图10，在源极区AA上形成源极30，在漏极区BB上形成漏极40。
S400、如图34所示，形成初始介质层211，初始介质层211跨设在沟道区CC上。
可以理解，“初始介质层211跨设在沟道区CC上”，可以是如图34所示，初始介质层211跨设在多个鳍10的沟道区CC上。其中，初始介质层211可以同时跨设在多个第一鳍11和多个第二鳍12的沟道区CC上，或者，初始介质层211可以同时跨设在多个第一鳍11的沟道区CC上，又或者，初始介质层211可以同时跨设在多个第二鳍12的沟道区CC上。
S500、如图35所示，在初始介质层211上形成P型功函数层23，P型功函数层23至少位于P型场效应管区W2。
其中，“P型功函数层23至少位于P型场效应管区W2”，可以是如图35所示，P 型功函数层23仅位于P型场效应管区W2，也可以是，P型功函数层23位于P型场效应管区W2和N型场效应管区W1。
S600、如图36所示，在P型功函数层23上形成N型功函数层27，N型功函数层27位于N型场效应管区W1和P型场效应管区W2，且N型功函数层27中包括铝原子(Al原子)。
S700、参阅图37和图38，采用退火工艺，将N型功函数层27中的铝原子靶向移动至初始介质层211，形成栅介质层21。铝原子靠近栅介质层21远离沟道区CC的表面。
S800、如图38所示，去除N型功函数层27。
S900、如图39所示，在P型功函数层23上形成栅金属层22。
在一些实施例中，如图40和图41所示，步骤S500、在初始介质层211上形成P型功函数层23，包括：
S510、在初始介质层211上形成第一中间P型功函数层231。
S520、图案化第一中间P型功函数层231。
示例性的，可以利用光刻工艺图案化第一中间P型功函数层231。
S530、在图案化后的第一中间P型功函数层231上形成第二中间P型功函数层232。
S540、重复至少一次上述步骤，直至多个晶体管的P型功函数层23达到目标厚度。
其中，可以根据不同晶体管100的所需要的阈值电压，设计不同晶体管100中的P型功函数层23的目标厚度。本申请中对目标厚度的取值不做具体限制。
在一些示例中，第一中间P型功函数层231的厚度和第二中间P型功函数层232的厚度可以相同。在另一些示例中，第一中间P型功函数层231的厚度和第二中间P型功函数层232的厚度可以不同。
本申请中对第一中间P型功函数层231的厚度和第二中间P型功函数层232的厚度不做限制。示例性的，第一中间P型功函数层231的厚度可以为10埃±5埃。示例性的，第二中间P型功函数层232的厚度可以为10埃±5埃。
如图42所示，本申请一些实施例提供了一种电子设备1000，该电子设备1000例如为消费性电子产品、家居式电子产品、车载式电子产品、金融终端产品。其中，消费性电子产品如为手机(mobile phone)、平板电脑(pad)、笔记本电脑、电子阅读器、个人计算机(personal computer，PC)、个人数字助理(personal digital assistant，PDA)、桌面显示器、智能穿戴产品(例如，智能手表、智能手环)、虚拟现实(virtual reality，VR)终端设备、增强现实(augmented reality，AR)终端设备、无人机等。家居式电子产品如为智能门锁、电视、遥控器、冰箱、充电家用小型电器(例如豆浆机、扫地机器人)等。车载式电子产品如为车载导航仪、车载DVD等。金融终端产品如为ATM机、自助办理业务的终端等。本申请实施例对上述电子设备1000的具体形式不做特殊限制。
上述电子设备1000可以包括半导体器件200和印刷电路板(printed circuit board，PCB)300等元件，半导体器件200与印刷电路板300电连接，以实现信号互通。
本申请一些实施例所提供的电子设备1000所能够达到的技术效果与上述任一实施例所述的半导体器件所能够达到的技术效果相同，在此不再赘述。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (23)

  1. 一种晶体管，其特征在于，包括：
    鳍；所述鳍包括源极区、漏极区，以及位于所述源极区和所述漏极区之间的沟道区；
    栅介质层，跨设在所述沟道区上；所述栅介质层含有铝原子，且所述铝原子靠近所述栅介质层远离所述沟道区的表面；
    栅金属层，位于所述栅介质层上；
    源极和漏极，所述源极位于所述源极区上，所述漏极位于所述漏极区上。
  2. 根据权利要求1所述的晶体管，其特征在于，还包括：
    P型功函数层，位于所述栅介质层和所述栅金属层之间。
  3. 根据权利要求2所述的晶体管，其特征在于，还包括：
    刻蚀阻挡层，位于所述栅介质层和所述P型功函数层之间。
  4. 根据权利要求1～3中任一项所述的晶体管，其特征在于，还包括：
    保护层，位于所述栅介质层和所述栅金属层之间，且与所述栅介质层接触。
  5. 根据权利要求1～3中任一项所述的晶体管，其特征在于，还包括：
    粘接层，位于所述栅介质层和所述栅金属层之间，且与所述栅金属层接触。
  6. 根据权利要求1～3中任一项所述的晶体管，其特征在于，所述栅介质层的材料包括二氧化铪。
  7. 根据权利要求1～3中任一项所述的晶体管，其特征在于，所述栅介质层中的铝元素的含量高于其他膜层的铝元素的含量，所述其他膜层至少包括所述栅金属层。
  8. 根据权利要求1～3中任一项所述的晶体管，其特征在于，还包括：
    栅绝缘层，位于所述栅介质层和所述沟道区之间。
  9. 一种半导体器件，其特征在于，所述半导体器件包括衬底以及所述衬底上设置的多个晶体管，所述晶体管为如权利要求1～8中任一项所述的晶体管。
  10. 根据权利要求9所述的半导体器件，其特征在于，所述多个晶体管包括N型场效应管和P型场效应管，所述P型场效应管包括P型功函数层。
  11. 根据权利要求10所述的半导体器件，其特征在于，多个所述P型场效应管中的P型功函数层的厚度不完全相同。
  12. 根据权利要求10所述的半导体器件，其特征在于，至少一个所述N型场效应管包括P型功函数层。
  13. 根据权利要求12所述的半导体器件，其特征在于，多个所述N型场效应管包括P型功函数层，且多个所述N型场效应管中的P型功函数层的厚度不完全相同。
  14. 一种晶体管的制备方法，其特征在于，包括：
    在衬底上形成鳍，所述鳍包括源极区、漏极区，以及位于所述源极区和所述漏极区之间的沟道区；
    在所述源极区上形成源极，在所述漏极区上形成漏极；
    形成栅介质层，所述栅介质层跨设在所述沟道区上；所述栅介质层含有铝原子，且所述铝原子靠近所述栅介质层远离所述沟道区的表面；
    在所述栅介质层上形成栅金属层。
  15. 根据权利要求14所述的制备方法，其特征在于，所述形成栅介质层，包括：
    形成初始介质层，所述初始介质层跨设在所述沟道区上；
    在所述初始介质层上形成N型功函数层，所述N型功函数层中包括铝原子；
    采用退火工艺，将所述N型功函数层中的铝原子靶向移动至所述初始介质层，形成所述栅介质层；
    去除所述N型功函数层。
  16. 根据权利要求15所述的制备方法，其特征在于，还包括：
    在所述初始介质层上形成N型功函数层之前，在所述初始介质层上形成P型功函数层。
  17. 根据权利要求16所述的制备方法，其特征在于，还包括：
    在所述初始介质层上形成P型功函数层之前，在所述初始介质层上形成刻蚀阻挡层。
  18. 根据权利要求15所述的制备方法，其特征在于，还包括：
    在所述形成初始介质层之后，在所述初始介质层上形成保护层。
  19. 根据权利要求14所述的制备方法，其特征在于，还包括：
    在所述栅介质层上形成粘接层。
  20. 根据权利要求14所述的制备方法，其特征在于，所述在衬底上形成鳍之后，且在所述形成栅介质层之前，所述制备方法还包括：
    形成栅绝缘层，所述栅绝缘层跨设在所述沟道区上。
  21. 一种半导体器件的制备方法，其特征在于，包括：
    提供衬底，所述衬底包括N型场效应管区和P型场效应管区；
    在所述衬底上形成多个鳍，所述鳍包括源极区、漏极区，以及位于所述源极区和所述漏极区之间的沟道区；所述多个鳍包括位于所述N型场效应管区的第一鳍，和位于所述P型场效应管区的第二鳍；
    在所述源极区上形成源极，在所述漏极区上形成漏极；
    形成初始介质层，所述初始介质层跨设在所述沟道区上；
    在所述初始介质层上形成P型功函数层，所述P型功函数层至少位于所述P型场效应管区；
    在所述P型功函数层上形成N型功函数层，所述N型功函数层位于N型场效应管区和所述P型场效应管区，且所述N型功函数层中包括铝原子；
    采用退火工艺，将所述N型功函数层中的铝原子靶向移动至所述初始介质层，形成所述栅介质层；所述铝原子靠近所述栅介质层远离所述沟道区的表面；
    去除所述N型功函数层；
    在所述P型功函数层上形成所述栅金属层。
  22. 根据权利要求21所述的制备方法，其特征在于，所述在所述初始介质层上形成P型功函数层，包括：
    在所述初始介质层上形成第一中间P型功函数层；
    图案化第一中间P型功函数层；
    在图案化后的第一中间P型功函数层上形成第二中间P型功函数层；
    重复至少一次上述步骤，直至多个晶体管的P型功函数层达到目标厚度。
  23. 一种电子设备，其特征在于，包括印刷电路板，和如权利要求9～13中任一项所述的半导体器件；所述半导体器件和所述印刷电路板电连接。
PCT/CN2023/082328 2022-04-15 2023-03-17 晶体管及其制备方法、半导体器件及其制备方法 WO2023197828A1 (zh)

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