TWI792192B - 半導體裝置及其形成方法 - Google Patents

半導體裝置及其形成方法 Download PDF

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TWI792192B
TWI792192B TW110106060A TW110106060A TWI792192B TW I792192 B TWI792192 B TW I792192B TW 110106060 A TW110106060 A TW 110106060A TW 110106060 A TW110106060 A TW 110106060A TW I792192 B TWI792192 B TW I792192B
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Taiwan
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layer
channel elements
vertically stacked
work function
stacked channel
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TW110106060A
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TW202133326A (zh
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朱龍琨
黃懋霖
徐崇威
余佳霓
江國誠
王志豪
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台灣積體電路製造股份有限公司
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Abstract

提供具有第一全繞式閘極(GAA)電晶體、第二全繞式閘極電晶體和第三全繞式閘極電晶體的半導體裝置。第一全繞式閘極(GAA)電晶體包含第一複數個通道元件、位於第一複數個通道元件上方的閘極介電層、位於閘極介電層上方的第一功函數層及位於第一功函數層上方的黏著層。第二全繞式閘極電晶體包含第二複數個通道元件、位於第二複數個通道元件上方的閘極介電層、位於閘極介電層上方的第二功函數層、位於第二功函數層上方並接觸第二功函數層的第一功函數層及位於第一功函數層上方的黏著層。第三全繞式閘極電晶體包含第三複數個通道元件、位於第三複數個通道元件上方的閘極介電層及位於閘極介電層上方的黏著層。

Description

半導體裝置及其形成方法
本發明實施例係有關於半導體技術，且特別是有關於半導體裝置及其形成方法。
半導體積體電路(integrated circuit，IC)產業已經歷了快速成長。在積體電路材料和設計上的技術進步產生了數代積體電路，每一代都比前一代具有更小且更複雜的電路。在積體電路的發展史中，功能密度(即每一晶片區互連的裝置數目)增加，同時幾何尺寸(即製造過程中所產生的最小的組件(或線路))縮小。此元件尺寸微縮化的製程提供增加生產效率與降低相關費用的益處。元件尺寸微縮化也增加了加工及製造積體電路的複雜性。
舉例來說，隨著積體電路(IC)技術朝更小的技術節點發展，已引進多閘極裝置透過增加閘極通道耦合、降低關態電流及減少短通道效應(short-channel effects，SCEs)來改善閘極控制。多閘極裝置一般代表具有閘極結構或閘極結構的一部分設置於通道區的多於一面上方的裝置。鰭式場效電晶體(Fin-like field effect transistors，FinFETs)和全繞式閘極(gate-all-around，GAA)電晶體(兩者也被稱為非平面電晶體)為高效能且低漏電應用之已流行且有潛力的候選的多閘極裝置的範例。鰭式場效電晶體具有由閘極在多於一面圍繞的升高的通道(舉例來說，閘極圍繞從基底延伸的半導體材料的“鰭”的頂部和側壁)。相較於平面電晶體，此配置提供通道的較佳控制以及大幅地減少短通道效應(特別來說，透過減少次臨界漏電流(即在關態的鰭式場效電晶體的源極與汲極之間的耦合)來達到)。全繞式閘極電晶體具有可部分延伸或完全延伸於通道區周圍的閘極結構，以在兩面或更多面上提供入口至通道區。全繞式閘極電晶體的通道區可由奈米線、奈米片、其他奈米結構及/或其他合適的結構形成。在一些實施例中，此通道區包含垂直堆疊的多個奈米線(其水平延伸，進而提供水平定向的通道)。這種全繞式閘極電晶體可被稱為垂直堆疊水平全繞式閘極(vertically-stacked horizontal GAA，VGAA)電晶體。
當期望具有不同臨界電壓的全繞式閘極電晶體時，可在所有通道區上方毯覆式沉積一層或多層，且選擇性移除通道區的子集。有時，移除沉積於通道區中奈米結構之間的材料可能具有挑戰性。不移除或完全移除此材料可導致裝置失效或降低效能。因此，雖然現有的全繞式閘極電晶體及其形成製程一般來說已滿足其預期目的，但是現有的全繞式閘極電晶體及其形成製程在各個方面並非完全令人滿意。
在一些實施例中，提供半導體裝置，半導體裝置包含第一全繞式閘極電晶體，包含第一複數個通道元件；界面層，位於第一複數個通道元件上方；閘極介電層，位於界面層上方；第一功函數層，位於閘極介電層上方並接觸閘極介電層；及黏著層，位於第一功函數層上方；第二全繞式閘極電晶體，包含第二複數個通道元件；界面層，位於第二複數個通道元件上方；閘極介電層，位於界面層上方；第二功函數層，位於閘極介電層上方並接觸閘極介電層；第一功函數層，位於第二功函數層上方並接觸第二功函數層；及黏著層，位於第一功函數層上方；以及第三全繞式閘極電晶體，包含第三複數個通道元件；界面層，位於第三複數個通道元件上方；閘極介電層，位於界面層上方；及黏著層，位於閘極介電層上方。
在一些其他實施例中，提供半導體裝置的形成方法，此方法包含提供工件，工件包含基底、在基底的第一區中的複數個第一垂直堆疊通道元件、在基底的第二區中的複數個第二垂直堆疊通道元件及在基底的第三區中的複數個第三垂直堆疊通道元件；在複數個第一垂直堆疊通道元件、複數個第二垂直堆疊通道元件和複數個第三垂直堆疊通道元件上方沉積閘極介電層；在閘極介電層上方沉積犧牲層；蝕刻犧牲層，使得犧牲層的一部分保留在複數個第一垂直堆疊通道元件的相鄰兩者之間、複數個第二垂直堆疊通道元件的相鄰兩者之間和複數個第三垂直堆疊通道元件的相鄰兩者之間；選擇性移除第二區中全部的犧牲層；在複數個第一垂直堆疊通道元件、複數個第二垂直堆疊通道元件和複數個第三垂直堆疊通道元件上方沉積第一功函數層；選擇性移除第一區中的第一功函數層和犧牲層；在複數個第一垂直堆疊通道元件、複數個第二垂直堆疊通道元件和複數個第三垂直堆疊通道元件上方沉積第二功函數層，第二功函數層不同於第一功函數層；以及在第二功函數層上方沉積鈍化層。
在另外一些實施例中，提供半導體裝置的形成方法，此方法包含提供工件，工件包含基底、在基底的第一區中的複數個第一垂直堆疊通道元件、在基底的第二區中的複數個第二垂直堆疊通道元件及在基底的第三區中的複數個第三垂直堆疊通道元件；在複數個第一垂直堆疊通道元件、複數個第二垂直堆疊通道元件和複數個第三垂直堆疊通道元件上方沉積閘極介電層；在閘極介電層上方沉積犧牲層；部分及選擇性蝕刻犧牲層，使得犧牲層的一部分設置於複數個第一垂直堆疊通道元件的相鄰兩者之間、複數個第二垂直堆疊通道元件的相鄰兩者之間和複數個第三垂直堆疊通道元件的相鄰兩者之間；選擇性移除第二區中全部的犧牲層；在複數個第一垂直堆疊通道元件、複數個第二垂直堆疊通道元件和複數個第三垂直堆疊通道元件上方沉積第一功函數層；選擇性移除第一區中的第一功函數層和犧牲層；在複數個第一垂直堆疊通道元件、複數個第二垂直堆疊通道元件和複數個第三垂直堆疊通道元件上方沉積第二功函數層，第二功函數層不同於第一功函數層；在第二功函數層上方沉積鈍化層；選擇性移除第三區中的鈍化層、第一功函數層、第二功函數層和犧牲層；在複數個第一垂直堆疊通道元件、複數個第二垂直堆疊通道元件和複數個第三垂直堆疊通道元件上方沉積黏著層；以及在黏著層上方沉積金屬填充層，其中第一功函數層的組成大致相同於黏著層的組成。
要瞭解的是以下的揭露內容提供許多不同的實施例或範例，以實施提供之主體的不同部件。以下敘述各個構件及其排列方式的特定範例，以求簡化揭露內容的說明。當然，這些僅為範例並非用以限定本發明。例如，以下的揭露內容敘述了將一第一部件形成於一第二部件之上或上方，即表示其包含了所形成的上述第一部件與上述第二部件是直接接觸的實施例，亦包含了尚可將附加的部件形成於上述第一部件與上述第二部件之間，而使上述第一部件與上述第二部件可能未直接接觸的實施例。此外，揭露內容中不同範例可能使用重複的參考符號及/或用字。這些重複符號或用字係為了簡化與清晰的目的，並非用以限定各個實施例及/或所述外觀結構之間的關係。
再者，為了方便描述圖式中一元件或部件與另一(複數)元件或(複數)部件的關係，可使用空間相關用語，例如“在...之下”、“下方”、“下部”、“上方”、“上部”及類似的用語。除了圖式所繪示的方位之外，空間相關用語也涵蓋裝置在使用或操作中的不同方位。所述裝置也可被另外定位(例如，旋轉90度或者位於其他方位)，並對應地解讀所使用的空間相關用語的描述。
再者，當用“大約”、“近似”及類似術語描述數字或數字範圍時，此術語目的在涵蓋在包含所描述的數字的合理範圍內的數字，例如在描述的數字的+/- 10％之內或本發明所屬技術領域者理解的其他數值。舉例來說，術語“約5nm”涵蓋4.5nm至5.5nm的尺寸範圍。
本發明實施例為有關於全繞式閘極電晶體，且特別為有關於在半導體裝置中有著不同臨界電壓的全繞式閘極電晶體。依據本發明實施例的半導體裝置包含在第一區中的第一型全繞式閘極電晶體、在第二區中的第二型全繞式閘極電晶體以及在第三區中的第三型全繞式閘極電晶體。第一型全繞式閘極電晶體包含第一垂直堆疊通道元件，第二型全繞式閘極電晶體包含第二垂直堆疊通道元件，且第三型全繞式閘極電晶體包含第三垂直堆疊通道元件。第一型全繞式閘極電晶體包含在第一垂直堆疊通道元件上方的界面層、在界面層上方的閘極介電層、在閘極介電層上方的n型功函數層、在n型功函數層上方的鈍化層、在鈍化層上方的黏著層以及在黏著層上方的金屬填充層。第二型全繞式閘極電晶體包含在第二垂直堆疊通道元件上方的界面層、在界面層上方的閘極介電層、在閘極介電層上方的p型功函數層、在p型功函數層上方的n型功函數層、在n型功函數層上方的鈍化層、在鈍化層上方的黏著層以及在黏著層上方的金屬填充層。第三型全繞式閘極電晶體包含在第三垂直堆疊通道元件上方的界面層、在界面層上方的閘極介電層、在閘極介電層上方的黏著層以及在黏著層上方的金屬填充層。依據本發明實施例，半導體裝置的形成製程包含在通道元件之間形成犧牲層，以防止難以移除的功函數層沉積於通道元件之間。由於很少或沒有設置於通道元件之間的難以移除的功函數層，因此容易移除通道元件之間的材料，且後續沉積層可沉積於通道元件周圍。
第1圖為依據本發明各個方面之半導體裝置的製造方法100的流程圖。以下將結合第2A、2B、2C和3-23圖描述第1圖，第2A、2B、2C和3-23圖為依據第1圖的方法100，將半導體裝置製造於工件上之前，工件在製造的各個階段的概略透視圖和概略剖面示意圖。在本發明實施例中，為了便於參考，因為在製程結束時工件會變為半導體裝置，因此可互換指稱工件和半導體裝置，且可共用相同的參考符號。可在方法100之前、期間和之後提供額外的步驟，且對於方法100的額外實施例，可移動、取代或消除描述的一些步驟。可將額外的部件增加至第2A、2B、2C和3-23圖所示的半導體裝置，且在半導體裝置的其他實施例中，可取代、修改或消除以下描述的一些部件。
請參照第1、2A、2B和2C圖，方法100包含方塊102，其中在工件200的基底202上的第一區1000、第二區2000和第三區3000上方形成複數個交替的半導體層204。工件200的第一區1000顯示於第2A圖，工件200的第二區2000顯示於第2B圖，且工件200的第三區3000顯示於第2C圖。在一些實施例中，基底202包含矽。替代地或附加地，基底202包含其他元素半導體(例如鍺)、化合物半導體(例如碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦)、合金半導體(例如矽鍺(SiGe)、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP)或前述之組合。在一些實施例中，基底202包含一個或多個第III-V族材料、一個或多個第II-IV族材料或前述之組合。在一些實施例中，基底202為絕緣層上覆半導體基底，例如絕緣層上覆矽(silicon-on-insulator，SOI)基底、絕緣層上覆矽鍺(silicon germanium-on-insulator，SGOI)基底或絕緣層上覆鍺(germanium-on-insulator，GOI)基底。絕緣層上覆半導體基底可透過使用植氧分離(separation by implantation of oxygen，SIMOX)、晶圓接合及/或其他合適的方法製造。依據工件200的設計需求，基底202可包含各種摻雜區。p型摻雜區可包含p型摻雜物，例如硼、銦、其他p型摻雜物或前述之組合。n型摻雜區可包含n型摻雜物，例如磷、砷、其他n型摻雜物或前述之組合。在一些實施例中，基底202包含由p型摻雜物和n型摻雜物的組合形成的摻雜區。各種摻雜區可直接形成於基底202上及/或基底202中，這些摻雜區例如提供p型井結構、n型井結構、雙井結構、凸起結構或前述之組合。可進行離子佈植製程、擴散製程及/或其他合適的摻雜製程，以形成各種摻雜區。在一些實施例中，p型全繞式閘極裝置形成於n型井上方，而n型全繞式閘極裝置形成於p型井上方。
第一區1000、第二區2000和第三區3000為具有不同臨界電壓的電晶體的裝置區。在一些實施例中，第一區1000可為具有第一臨界電壓的n型裝置區，第三區3000可為具有第三臨界電壓的p型裝置區，且第二區2000可為具有在第一臨界電壓與第三臨界電壓之間的第二臨界電壓的中級裝置區。第一臨界電壓、第二臨界電壓和第三臨界電壓彼此不同。舉例來說，第一臨界電壓可在約4.3eV與約4.5eV之間，第二臨界電壓可在約4.5eV與約4.7eV之間，第三臨界電壓可在約4.7eV與約4.9eV之間。取決於設計參數，第二區2000中的中級裝置可作為n型裝置或p型裝置，以減少漏電流。
在第2A、2B和2C圖呈現的實施例中，複數個交替的半導體層204包含複數個第一半導體層208和複數個第二半導體層206交錯排列。也就是說，一個第二半導體層206夾設於兩相鄰第一半導體層208之間。複數個第一半導體層208由第一半導體材料形成，而複數個第二半導體層206由不同於第一半導體材料的第二半導體材料形成。在一些實施例中，第一半導體材料為矽(Si)或基本上由矽(Si)組成，而第二半導體材料為矽鍺(SiGe)由基本上由矽鍺(SiGe)組成。在一些其他實施例中，第一半導體材料為矽(Si)或基本上由矽(Si)組成，而第二半導體材料為鍺(Ge)或基本上由鍺(Ge)組成。在一些替代實施例中，第一半導體材料包含具有第一鍺含量的矽鍺(SiGe)，而第二半導體材料包含具有大於第一鍺含量的第二鍺含量的矽鍺(SiGe)。複數個交替的半導體層204包可透過交替地沉積或磊晶成長複數個第一半導體層208和複數個第二半導體層206形成。在一些實施例中，在將複數個交替的半導體層204圖案化為鰭結構(鰭狀主動區)之後，可選擇性地移除在通道區中的複數個第二半導體層206的一部分，以釋放由複數個第一半導體層208形成的通道元件。就這點而言，第二半導體層206用作犧牲半導體層，且可被稱為犧牲半導體層。
請參照第1、2A、2B和2C圖，方法100包含方塊104，其中在第一區1000中形成第一鰭結構210A，在第二區2000中形成第二鰭結構210B，及在第三區3000中形成第三鰭結構210C。如第2A圖所示，可將複數個交替的半導體層204圖案化，以形成第一區1000中的第一鰭結構210A。如第2B圖所示，可將複數個交替的半導體層204圖案化，以形成第二區2000中的第二鰭結構210B。如第2C圖所示，可將複數個交替的半導體層204圖案化，以形成第三區3000中的第三鰭結構210C。在方塊104，第一鰭結構210A、第二鰭結構210B和第三鰭結構210C可透過使用合適的製程(例如光微影和蝕刻製程)圖案化。在一些實施例中，使用乾蝕刻或電漿蝕刻製程蝕刻複數個交替的半導體層204來形成鰭結構。在一些其他實施例中，鰭結構可透過雙重圖案化微影(double-patterning lithography，DPL)製程、四重圖案化微影(quadruple-patterning lithography，QPL)製程或多重圖案化微影(multiple-patterning lithography，MPL)製程形成。一般來說，雙重圖案化微影、四重圖案化微影和多重圖案化微影製程結合了光微影和自對準製程，以創造具有較小間距的圖案，舉例來說，此圖案具有比使用單一直接光微影製程可獲得的間距更小的圖案。在一些實施例中，介電隔離部件212形成於第一鰭結構210A之間、第二鰭結構210B之間及第三鰭結構210C之間。介電隔離部件212也可被稱為淺溝槽隔離(shallow trench isolation，STI)部件。
請參照第1、2A、2B和2C圖，方法100包含方塊106，其中在第一鰭結構210A的第一通道區1100、第二鰭結構210B的第二通道區2100和第三鰭結構210C的第三通道區3100上方形成虛設閘極結構214。如第2A、2B和2C圖所示，虛設閘極結構214可包含虛設閘極介電層216、虛設閘極電極218、閘極頂部硬遮罩220和閘極間隙壁221。在一些實施例中，虛設閘極電極218可由多晶矽形成，且虛設閘極介電層216可由氧化矽或氮氧化矽形成。閘極頂部硬遮罩220可由氧化矽或氮化矽形成。在一些實施例中，閘極頂部硬遮罩220可包含多層。舉例來說，閘極頂部硬遮罩220可包含與虛設閘極電極218相鄰的氧化矽層及在氧化矽層上方的氮化矽層。閘極間隙壁221沿虛設閘極電極218的側壁延伸，並定義第一通道區1100、第二通道區2100和第三通道區3100。在一些實施例中，閘極間隙壁221可由氧化矽、氮氧化矽、氮化矽、氮碳氧化矽、有著介電常數小於二氧化矽的介電常數(即約3.9)的低介電常數介電材料或前述之組合形成。
為了清楚描述和顯示，第3-23圖的每一張圖包含沿第2A圖所示的剖面I-I’的第一鰭結構210A的局部剖面示意圖、沿第2B圖所示的剖面II-II’的第二鰭結構210B的局部剖面示意圖以及沿第2C圖所示的剖面III-III’的第三鰭結構210C的局部剖面示意圖。如第2A圖所示，剖面I-I’沿虛設閘極結構214延伸，並通過第一通道區1100。如第2B圖所示，剖面II-II’沿虛設閘極結構214延伸，並通過第二通道區2100。如第2C圖所示，剖面III-III’沿虛設閘極結構214延伸，並通過第三通道區3100。
請參照第1和3-5圖，方法100包含方塊108，其中釋放第一通道區1100中的第一通道元件2081、第二通道區2100中的第二通道元件2082以及第三通道區3100中的第三通道元件2083。在一些實施例中，在方塊106形成虛設閘極結構214之後，虛設閘極結構214用作蝕刻遮罩以將第一鰭結構210A、第二鰭結構210B和第三鰭結構210C凹陷，以形成源極/汲極溝槽來暴露出第一通道區1100、第二通道區2100和第三通道區3100中的複數個第一半導體層208和複數個第二半導體層206的側壁。在一些實施例中，可選擇性並部分蝕刻第一通道區1100、第二通道區2100和第三通道區3100中的複數個第二半導體層206，以在複數個第一半導體層208的兩者之間形成內部間隙壁凹口。接著，在內部間隙壁凹口中形成內部間隙壁部件。可在源極/汲極溝槽中形成磊晶源極/汲極部件。在形成磊晶源極/汲極部件之後，可在工件200上方沉積層間介電(interlayer dielectric，ILD)層。可進行平坦化製程(例如化學機械研磨(chemical mechanical polishing，CMP)製程)，以將工件200平坦化直到暴露出虛設閘極電極218。接著，可使用合適的乾蝕刻或濕蝕刻製程選擇性地移除暴露的虛設閘極電極218。第3圖顯示在移除虛設閘極電極218之後，在第一通道區1100、第二通道區2100和第三通道區3100中複數個交替的半導體層204。在一些實施例中，可使用合適的蝕刻製程來移除虛設閘極介電層216，此蝕刻製程不同於用以移除虛設閘極電極218的蝕刻製程。第4圖顯示在移除虛設閘極介電層216之後，在第一通道區1100、第二通道區2100和第三通道區3100中複數個交替的半導體層204。在移除虛設閘極介電層216之後，可選擇性地移除複數個第二半導體層206。在一些實施例中，複數個第二半導體層206由矽鍺形成，且選擇性移除製程包含使用合適的氧化劑(例如臭氧)將複數個第二半導體層206氧化。之後，可選擇性地移除氧化的第二半導體層206。在此階段，如第5圖所示，第一通道元件2081形成於第一區1000中，第二通道元件2082形成於第二區2000中，而第三通道元件2083形成於第三區3000中。
請參照第1和6圖，方法100包含方塊110，其中在第一區1000的第一通道元件2081、第二區2000的第二通道元件2082以及第三區3000的第三通道元件2083上方形成界面層222。在一些實施例中，界面層222可包含氧化矽或氮氧化矽或其他合適的材料。在一些實施例中，界面層222可透過使用合適的方法沉積，例如原子層沉積(atomic layer deposition，ALD)、化學氣相沉積(chemical vapor deposition，CVD)、臭氧氧化、熱氧化或其他合適的方法。界面層222具有控制並降低閘極漏電流以及改善閘極介電層228(如第7圖所示)與通道元件(包含第一通道元件2081、第二通道元件2082和第三通道元件2083)之間的界面黏著性的功能。
請參照第1和7圖，方法100包含方塊112，其中在第一區1000、第二區2000和第三區3000中的界面層222上方沉積閘極介電層228。在一些實施例中，閘極介電層228為高介電常數介電層，因為閘極介電層228的介電常數大於二氧化矽的介電常數(~3.9)。在一些實施例中，閘極介電層228可包含摻雜或未摻雜的氧化鉿(HfO2 )、摻雜或未摻雜的氧化鋯(ZrO2 )、摻雜或未摻雜的氧化鈦(TiO2 )或摻雜或未摻雜的氧化鋁(Al2 O3 )。舉例來說，閘極介電層228可包含氧化鉿矽(HfSiO)、氮氧化鉿矽(HfSiON)、氧化鉿鋁(HfAlO)、氧化鉿鉭(HfTaO)、氧化鉿鋯(HfZrO)、氧化鋯矽(ZrSiO2 )、氧化鉿鈦(HfTiO)或前述之組合。在完成方塊112的操作之後，界面層222和閘極介電層228環繞第一通道元件2081、第二通道元件2082和第三通道元件2083的每一者。
請參照第1和8圖，方法100包含方塊114，其中在閘極介電層228上方沉積犧牲層230。依據本發明一些實施例，犧牲層230由可被選擇性移除而大致不損壞閘極介電層228的材料形成。在一些實施例中，犧牲層230由介電材料(例如氧化矽、氮化矽、氧化鋁、氧化鈦、氧化鋯)、半導體材料(例如矽或鍺或SiGe)、低密度金屬氮化物(例如氮化鈦)或其他合適的材料形成。在一些範例中，犧牲層230可由氧化矽或氮化矽形成。犧牲層230可透過使用原子層沉積(ALD)或其他合適的方法沉積。
請參照第1和9圖，方法100包含方塊116，其中移除犧牲層230的一部分。在一些實施例中，在方塊116，當蝕刻犧牲層230時，第一通道元件2081、第二通道元件2082和第三通道元件2083的每一者作為蝕刻遮罩或蝕刻屏蔽。在方塊116的犧牲層230的移除包含選擇基於形成犧牲層230的材料的乾蝕刻製程或濕蝕刻製程。在第9圖所呈現的一些實施例中，在完成方塊116的操作之後，保留犧牲層230設置於相鄰通道元件之間的部分。犧牲層230的剩下部分可被稱為剩餘犧牲層230’。換句話說，方塊116的操作可移除在第一通道元件2081、第二通道元件2082和第三通道元件2083的最頂表面和側面上的犧牲層230，以暴露出設置於第一通道元件2081、第二通道元件2082和第三通道元件2083上方的閘極介電層228。此處，最頂表面代表第一通道元件2081、第二通道元件2082和第三通道元件2083中的最頂部通道元件的頂表面。如第9圖所示，剩餘犧牲層230’垂直設置於相鄰的第一通道元件2081之間、第二通道元件2082之間及第三通道元件2083之間。
請參照第1、10、11和12圖，方法100包含方塊118，其中選擇性移除第二區2000中的剩餘犧牲層230’。在第10圖所呈現的一些實施例中，可形成圖案化硬遮罩232，使得圖案化硬遮罩232覆蓋第一區1000和第三區3000，且暴露出第二區2000。在一範例製程中，先在工件200上方毯覆式沉積硬遮罩層，在沉積的硬遮罩層上方沉積底部抗反射塗佈(bottom antireflective coating，BARC)層，並接著在底部抗反射塗佈層上方沉積光阻層。將光阻層預烘烤、透過暴露於通過遮罩或從遮罩反射的圖案化輻射來圖案化、後烘烤以及使用顯影劑在顯影製程中顯影，以形成圖案化光阻層。圖案化光阻層用作蝕刻遮罩，以將底部抗反射塗佈層圖案化。接著，圖案化的底部抗反射塗佈層用作蝕刻遮罩，以將硬遮罩層圖案化，以形成圖案化硬遮罩232。在一些範例中，硬遮罩層可為單一層或多層。請參照第11圖，移除第二區2000中的剩餘犧牲層230’，而第一區1000和第三區3000中的剩餘犧牲層230’透過圖案化硬遮罩232遮蔽。請參照第12圖，圖案化硬遮罩232透過使用合適的蝕刻製程移除。
請參照第1和13圖，方法100包含方塊120，其中在第一通道元件2081、第二通道元件2082和第三通道元件2083上方沉積第一功函數層234。在一些實施例中，第一功函數層234可為p型功函數層，且可包含氮化鈦(TiN)、氮化鈦矽(TiSiN)、氮化鉭(TaN)、氮碳化鎢(WCN)、鉬(Mo)或其他合適的p型功函數材料。第一功函數層234可透過使用原子層沉積製程形成。由於剩餘犧牲層230’保留在相鄰的第一通道元件2081之間以及第三通道元件2083之間，因此防止了第一功函數層234沉積環繞第一通道元件2081和第三通道元件2083的每一者。相較之下，第二區2000大致沒有剩餘犧牲層230’，且允許第一功函數層234形成環繞第二通道元件2082的每一者。
在傳統技術中，允許早期沉積的功函數層沉積於相鄰通道元件之間。當移除早期沉積的功函數層時，可能需要過蝕刻或增強蝕刻，以移除在通道元件之間的空間中的功函數材料。過蝕刻或增強蝕刻製程可能損壞相鄰電晶體中所需的功函數層。如果早期沉積的功函數層能夠保留在通道元件之間，由於存在早期沉積的功函數層的緣故，因此可防止後續沉積的功函數層進入相鄰通道元件之間。最終的裝置可具有臨界電壓大於必要的臨界電壓，或一個電晶體中的不同通道元件可具有不同臨界電壓。從以下描述和顯示可以看出，剩餘犧牲層230’用以防止難以移除的功函數層沉積於相鄰的第一通道元件2081之間以及相鄰的第三通道元件2083之間。如此一來，用以從一個或多個功函數層釋放第一通道元件2081或第三通道元件2083的後續蝕刻製程不需要過蝕刻來移除相鄰的第一通道元件2081之間以及相鄰的第三通道元件2083之間的功函數層材料。透過允許所期望的功函數層環繞通道元件而不過蝕刻，本發明實施例的製程可產生低臨界電壓的電晶體，改善臨界電壓一致性，並改善產率。
請參照第1、14、15和16圖，方法100包含方塊122，其中選擇性移除在第一通道元件2081上方的第一功函數層234和剩餘犧牲層230’。在第14圖所呈現的一些實施例中，可形成圖案化硬遮罩236，使得圖案化硬遮罩236覆蓋第二區2000和第三區3000，且暴露出第一區1000。在一範例製程中，先在工件200上方毯覆式沉積硬遮罩層，在沉積的硬遮罩層上方沉積底部抗反射塗佈(BARC)層，並接著在底部抗反射塗佈層上方沉積光阻層。將光阻層預烘烤、透過暴露於通過遮罩或從遮罩反射的圖案化輻射來圖案化、後烘烤以及使用顯影劑在顯影製程中顯影，以形成圖案化光阻層。圖案化光阻層用作蝕刻遮罩，以將底部抗反射塗佈層圖案化。接著，圖案化的底部抗反射塗佈層用作蝕刻遮罩，以將硬遮罩層圖案化。在一些範例中，硬遮罩層可為單一層或多層。請參照第15圖，移除第一區1000中的第一功函數層234和剩餘犧牲層230’，而第二區2000和第三區3000透過圖案化硬遮罩236遮蔽。在一些實施例中，第一功函數層234和剩餘犧牲層230’可透過在兩個不同的蝕刻製程中使用不同的蝕刻劑移除，使得每個蝕刻製程針對需移除的材料。請參照第16圖，圖案化硬遮罩236透過使用合適的蝕刻製程移除。在一些範例中，第一功函數層234具有厚度在約0.5nm與約2nm之間。
請參照第1和17圖，方法100包含方塊124，其中在第一通道元件2081、第二通道元件2082和第三通道元件2083上方沉積第二功函數層238。第二功函數層238不同於第一功函數層234。在一些實施例中，第二功函數層238可為n型功函數層，且可包含鋁(Al)、鈦鋁(TiAl)、碳化鈦鋁(TiAlC)、碳化鉭鋁(TaAlC)、矽化鉭鋁(TaSiAl)、碳化鉭矽(TaSiC)、矽化鉭(TaSi)、碳化鉿(HfC)、含鋁層或其他合適的n型功函數層。第二功函數層238可透過使用原子層沉積製程形成。由於移除了第一區1000和第二區2000的剩餘犧牲層230’，因此允許沉積第二功函數層238圍繞每個第一通道元件2081和每個第二通道元件2082。關於第三區3000，第二功函數層238沉積於第一功函數層234上方，且不環繞每個第三通道元件2083。在一些範例中，第二功函數層238包含厚度在約1nm與約3nm之間。如第18圖所示，第二功函數層238不會夾斷(pinch off)相鄰的第一通道元件2081之間以及相鄰的第二通道元件2082之間的空間，使得後續層(例如第18圖所示的鈍化層240)可沉積於相鄰的第一通道元件2081之間以及相鄰的第二通道元件2082之間。
請參照第1和18圖，方法100包含方塊126，其中在第二功函數層238上方沉積鈍化層240。方塊126的操作為選擇性的，且當進行方塊126時，在沉積第二功函數層238之後，方塊126在沒有破真空的相同製程腔體中立刻進行。這是因為當第二功函數層238包含鋁時，鈍化層240作為防止第二功函數層238中的鋁氧化。當第二功函數層238不包含鋁時，省略方塊126的操作。在第二功函數層238包含鋁的實施例中，進行方塊126的操作。鈍化層240可被稱為保護層。選擇鈍化層240的材料，使得鈍化層240可阻檔氧擴散或具有比鋁更低的還原電位。當鈍化層240的材料具有比鋁更低的還原電位時，鈍化層240透過優先氧化作為氧沉降(oxygen sink)。在一些實施例中，鈍化層240可由氮化鈦(TiN)、氮化鈦矽(TiSiN)、矽(Si)、氮化鉭(TaN)、氮碳化鎢(WCN)或其他合適的材料形成。在一些範例中，鈍化層240可形成至厚度在約0.5nm與約2nm之間。在一些其他範例中，可省略鈍化層240。在應用鈍化層240的實施例中，沉積鈍化層240以夾斷相鄰的第一通道元件2081之間以及相鄰的第二通道元件2082之間的空間，使得後續層(例如第22圖所示的黏著層244)不沉積於相鄰的第一通道元件2081之間以及相鄰的第二通道元件2082之間。
請參照第1、19、20和21圖，方法100包含方塊128，其中選擇性移除第三區3000中的第二功函數層238、鈍化層240、第一功函數層234和剩餘犧牲層230’。 在第19圖所呈現的一些實施例中，可形成圖案化硬遮罩242，使得圖案化硬遮罩242覆蓋第一區1000和第二區2000，且暴露出第三區3000。在一範例製程中，先在工件200上方毯覆式沉積硬遮罩層，在沉積的硬遮罩層上方沉積底部抗反射塗佈(BARC)層，並接著在底部抗反射塗佈層上方沉積光阻層。將光阻層預烘烤、透過暴露於通過遮罩或從遮罩反射的圖案化輻射來圖案化、後烘烤以及使用顯影劑在顯影製程中顯影，以形成圖案化光阻層。圖案化光阻層用作蝕刻遮罩，以將底部抗反射塗佈層圖案化。接著，圖案化的底部抗反射塗佈層用作蝕刻遮罩，以將硬遮罩層圖案化。在一些範例中，硬遮罩層可為單一層或多層。請參照第20圖，移除暴露的第三區3000中的鈍化層240、第二功函數層238、第一功函數層234和剩餘犧牲層230’，而第一區1000和第二區2000透過圖案化硬遮罩242遮蔽。請參照第21圖，圖案化硬遮罩242透過使用合適的蝕刻製程移除。
請參照第1和22圖，方法100包含方塊130，其中在第一通道元件2081、第二通道元件2082和第三通道元件2083上方沉積黏著層244。在一些實施例中，黏著層244可為p型功函數層，且可包含氮化鈦(TiN)、氮化鈦矽(TiSiN)、氮化鉭(TaN)、氮碳化鎢(WCN)、鉬(Mo)或其他合適的p型功函數材料。也就是說，黏著層244的組成可相同於第一功函數層234的組成。在一些實施例中，黏著層244可透過原子層沉積形成至厚度在約2nm與約5nm之間。在一些範例中，沉積黏著層244，以夾斷相鄰的第三通道元件2083之間的空間，使得後續層可不沉積於相鄰的第三通道元件2083之間。
請參照第1和23圖，方法100包含方塊132，其中進行進一步的製程。這些進一步的製程可包含在通道區(包含第一通道區1100、第二通道區2100和第三通道區3100)上方沉積金屬填充層246。金屬填充層246可包含鎢(W)或鈷(Co)。在沉積金屬填充層246之後，在第一區1000中形成第一金屬閘極堆疊物250A，在第二區2000中形成第二金屬閘極堆疊物250B，且在第三區3000中形成第三金屬閘極堆疊物250C。第一金屬閘極堆疊物250A包含界面層222、閘極介電層228、第二功函數層238、鈍化層240、黏著層244和金屬填充層246。第二金屬閘極堆疊物250B包含界面層222、閘極介電層228、第一功函數層234、第二功函數層238、鈍化層240、黏著層244和金屬填充層246。第三金屬閘極堆疊物250C包含界面層222、閘極介電層228、黏著層244和金屬填充層246。方塊132的進一步的製程的範例可包含形成層間介電(ILD)層、形成通過層間介電層的源極/汲極接點，以耦接至源極/汲極部件，以及形成閘極接點，以耦接至閘極結構。
在完成方法100的操作之後，第一全繞式閘極電晶體260A形成於第一區1000中，第二全繞式閘極電晶體260B形成於第二區2000中，且第三全繞式閘極電晶體260C形成於第三區3000中。第一全繞式閘極電晶體260A具有第一金屬閘極堆疊物250A。第二全繞式閘極電晶體260B具有第二金屬閘極堆疊物250B。第三全繞式閘極電晶體260C具有第三金屬閘極堆疊物250C。如第23圖所示，由於第二功函數層238為直接形成於閘極介電層228上方的n型功函數層，而沒有p型功函數層(即第一功函數層234)在中間，因此第一全繞式閘極電晶體260A可為有著臨界電壓低於本來的臨界電壓的n型全繞式閘極電晶體。透過使用剩餘犧牲層230’(如第13圖所示)，可能或至少促進在第一區1000中不存在p型功函數層在中間，這防止了第一功函數層234(或太多的第一功函數層234)進入相鄰的第一通道元件2081之間。由於在相鄰的第一通道元件2081之間的第一功函數層234減少或不存在，因此不需要濕式過蝕刻來移除在第一通道元件2081之間難以移除的第一功函數層234。
相似地，由於黏著層244為直接形成於閘極介電層228上方的p型功函數層，而沒有相鄰的n型功函數層(即第二功函數層238)，因此第三全繞式閘極電晶體260C可為有著臨界電壓低於本來的臨界電壓的p型全繞式閘極電晶體。n型功函數層可包含可擴散至相鄰p型功函數層的高擴散率以不利地使功函數偏離價帶的組件。舉例來說，在n型功函數層中的鋁可擴散至p型裝置的p型功函數層中，進而使功函數偏離價帶，且不利地增加臨界電壓。透過移除第三區3000的第二功函數層238(即n型功函數層)，沒有n型功函數層的高擴散率組件可擴散至黏著層244(即p型功函數層)中。透過使用剩餘犧牲層230’(如第13和17圖所示)，可能或至少促進在第三區3000中不存在n型功函數層在中間，這防止了第一功函數層234(或太多的第一功函數層234)及第二功函數層238(或太多的第二功函數層238)進入相鄰的第三通道元件2083之間。由於在相鄰的第三通道元件2083之間的第一功函數層234和第二功函數層238減少或不存在，因此不需要濕式過蝕刻來移除在第三通道元件2083之間難以移除的第一功函數層234和第二功函數層238。
在第23圖所示的實施例中，第二全繞式閘極電晶體260B包含坐落於第一全繞式閘極電晶體260A的n型臨界電壓與第三全繞式閘極電晶體260C的p型臨界電壓之間的中級臨界電壓。不同於第一金屬閘極堆疊物250A和第三金屬閘極堆疊物250C，第二全繞式閘極電晶體260B的第二金屬閘極堆疊物250B包含第一功函數層234和第二功函數層238。
在未在本文明確顯示的一些實施例中，可選擇性地將一個或多個偶極層選擇性地加進第一金屬閘極堆疊物250A、第二金屬閘極堆疊物250B和第三金屬閘極堆疊物250C，以進一步使工件200中的臨界電壓多樣化。舉例來說，取決於電子親和力和氧原子密度，偶極層可為n型偶極層或p型偶極層。加入第一金屬閘極堆疊物250A、第二金屬閘極堆疊物250B和第三金屬閘極堆疊物250C的偶極層可進一步將功函數移動靠近價帶或導電帶，進而使第一全繞式閘極電晶體260A、第二全繞式閘極電晶體260B和第三全繞式閘極電晶體260C的最終臨界電壓偏移。n型偶極層的範例材料包含氧化鑭、氧化鎂或氧化釔。p型偶極層的範例材料包含氧化鋁、氧化鈦或氧化鈮。在一些範例中，可將偶極材料熱引入閘極介電層228，而大致不增加閘極介電層228的厚度。透過選擇性處理一些第一全繞式閘極電晶體260A的閘極介電層228，而不處理一些其他的第一全繞式閘極電晶體260A的閘極介電層228，兩個第一全繞式閘極電晶體260A可進一步轉變為有著不同臨界電壓的第一全繞式閘極電晶體260A的兩個次群組。第二全繞式閘極電晶體260B和第三全繞式閘極電晶體260C也是如此。也就是說，透過選擇性引入一個偶極材料，可將有著三種臨界電壓水平的三種全繞式閘極電晶體製作成有著六種臨界電壓水平的六種全繞式閘極電晶體。因此可以看出，本發明實施例的製程和半導體裝置為形成具有多種臨界電壓的全繞式閘極電晶體打開了大門。
基於以上討論，本發明實施例提供了優於傳統全繞式閘極電晶體及其形成製程的許多優點。然而，可以理解的是，其他實施例可提供額外的優點，且本文並非必須揭露所有優點，且所有實施例不需要特定的優點。本發明實施例提供半導體裝置形成製程，此製程使用犧牲層以防止將被移除的功函數層進入相鄰通道元件之間的空間。此配置允許將被移除的功函數層的選擇性移除，而不需可能對相鄰結構造成損壞的過蝕刻。揭露的製程允許n型功函數層完全環繞n型全繞式閘極電晶體中的通道元件，且從p型全繞式閘極電晶體的通道元件周圍大致完全移除n型功函數層。因此，依據本發明實施例的n型全繞式閘極電晶體和p型全繞式閘極電晶體具有較低的臨界電壓。
本發明實施例提供半導體裝置及其形成方法。在一實施例中，提供半導體裝置。半導體裝置包含第一全繞式閘極(GAA)電晶體、第二全繞式閘極電晶體和第三全繞式閘極電晶體。第一全繞式閘極(GAA)電晶體包含第一複數個通道元件、位於第一複數個通道元件上方的界面層、位於界面層上方的閘極介電層、位於閘極介電層上方並接觸閘極介電層的第一功函數層及位於第一功函數層上方的黏著層。第二全繞式閘極電晶體包含第二複數個通道元件、位於第二複數個通道元件上方的界面層、位於界面層上方的閘極介電層、位於閘極介電層上方並接觸閘極介電層的第二功函數層、位於第二功函數層上方並接觸第二功函數層的第一功函數層及位於第一功函數層上方的黏著層。第三全繞式閘極電晶體包含第三複數個通道元件、位於第三複數個通道元件上方的界面層、位於界面層上方的閘極介電層及位於閘極介電層上方的黏著層。
在一些實施例中，第一功函數層包含鋁(Al)、鈦鋁(TiAl)、碳化鈦鋁(TiAlC)、碳化鉭鋁(TaAlC)、矽化鉭鋁(TaSiAl)、碳化鉭矽(TaSiC)、矽化鉭(TaSi)或碳化鉿(HfC)，且第二功函數層包含氮化鈦(TiN)、氮化鈦矽(TiSiN)、氮化鉭(TaN)、氮碳化鎢(WCN)或鉬(Mo)。在一些實施例中，其中黏著層包含氮化鈦(TiN)、氮化鈦矽(TiSiN)、氮化鉭(TaN)、氮碳化鎢(WCN)或鉬(Mo)。在一些範例中，第一全繞式閘極電晶體更包含設置於第一功函數層與黏著層之間的鈍化層，第二全繞式閘極電晶體更包含設置於第一功函數層與黏著層之間的鈍化層，且第三全繞式閘極電晶體不具有鈍化層。在一些實施例中，第一功函數層包含厚度在約1nm與約3nm之間，第二功函數層包含厚度在約0.5nm與約2nm之間，鈍化層包含厚度在約0.5nm與約2nm之間，且黏著層包含厚度在約2nm與約5nm之間。在一些實施例中，鈍化層包含氮化鈦(TiN)、氮化鈦矽(TiSiN)、矽(Si)、氮化鉭(TaN)或氮碳化鎢(WCN)。在一些實施例中，第一全繞式閘極電晶體、第二全繞式閘極電晶體和第三全繞式閘極電晶體的每一者更包含位於黏著層上方的金屬填充層，且金屬填充層包含鎢(W)或鈷(Co)。在一些實施例中，第一功函數層完全地圍繞第一複數個通道元件的每一者設置。
在另一實施例中，提供一方法，此方法包含提供工件，工件包含基底、在基底的第一區中的複數個第一垂直堆疊通道元件、在基底的第二區中的複數個第二垂直堆疊通道元件及在基底的第三區中的複數個第三垂直堆疊通道元件；在複數個第一垂直堆疊通道元件、複數個第二垂直堆疊通道元件和複數個第三垂直堆疊通道元件上方沉積閘極介電層；在閘極介電層上方沉積犧牲層；蝕刻犧牲層，使得犧牲層的一部分保留在複數個第一垂直堆疊通道元件的相鄰兩者之間、複數個第二垂直堆疊通道元件的相鄰兩者之間和複數個第三垂直堆疊通道元件的相鄰兩者之間；選擇性移除第二區中全部的犧牲層；在複數個第一垂直堆疊通道元件、複數個第二垂直堆疊通道元件和複數個第三垂直堆疊通道元件上方沉積第一功函數層；選擇性移除第一區中的第一功函數層和犧牲層；在複數個第一垂直堆疊通道元件、複數個第二垂直堆疊通道元件和複數個第三垂直堆疊通道元件上方沉積第二功函數層，第二功函數層不同於第一功函數層；以及在第二功函數層上方沉積鈍化層。
在一些實施例中，提供工件的步驟包含在基底的第一區、第二區和第三區上方形成複數個交替的半導體層，將複數個交替的半導體層圖案化，以在第一區中形成第一主動區，在第二區中形成第二主動區，及在第三區中形成第三主動區；以及選擇性移除複數個第二半導體層，以在第一主動區中形成複數個第一垂直堆疊通道元件，在第二主動區中形成複數個第二垂直堆疊通道元件，且在第三主動區中形成複數個第三垂直堆疊通道元件。複數個交替的半導體層包含複數個第一半導體層和夾設於複數個第一半導體層之間的複數個第二半導體層。在一些實施例中，蝕刻犧牲層暴露出設置於複數個第一垂直堆疊通道元件、複數個第二垂直堆疊通道元件和複數個第三垂直堆疊通道元件的側面上的閘極介電層。在一些範例中，犧牲層包含氧化矽或氮化矽。在一些實施例中，第一功函數層包含鋁(Al)、鈦鋁(TiAl)、碳化鈦鋁(TiAlC)、碳化鉭鋁(TaAlC)、矽化鉭鋁(TaSiAl)、碳化鉭矽(TaSiC)、矽化鉭(TaSi)或碳化鉿(HfC)，且第二功函數層包含氮化鈦(TiN)、氮化鈦矽(TiSiN)、氮化鉭(TaN)、氮碳化鎢(WCN)或鉬(Mo)。在一些實施例中，鈍化層包含氮化鈦(TiN)、氮化鈦矽(TiSiN)、矽(Si)、氮化鉭(TaN)或氮碳化鎢(WCN)。在一些實施例中，此方法更包含選擇性移除第三區中的鈍化層、第一功函數層、第二功函數層和犧牲層；在複數個第一垂直堆疊通道元件、複數個第二垂直堆疊通道元件和複數個第三垂直堆疊通道元件上方沉積黏著層；以及在黏著層上方沉積金屬填充層。在一些實施例中，其中黏著層包含氮化鈦(TiN)、氮化鈦矽(TiSiN)、氮化鉭(TaN)、氮碳化鎢(WCN)或鉬(Mo)，且金屬填充層包含鎢(W)或鈷(Co)。
在另一實施例中，提供一方法，此方法包含提供工件，工件包含基底、在基底的第一區中的複數個第一垂直堆疊通道元件、在基底的第二區中的複數個第二垂直堆疊通道元件及在基底的第三區中的複數個第三垂直堆疊通道元件；在複數個第一垂直堆疊通道元件、複數個第二垂直堆疊通道元件和複數個第三垂直堆疊通道元件上方沉積閘極介電層；在閘極介電層上方沉積犧牲層；部分及選擇性蝕刻犧牲層，使得犧牲層的一部分設置於複數個第一垂直堆疊通道元件的相鄰兩者之間、複數個第二垂直堆疊通道元件的相鄰兩者之間和複數個第三垂直堆疊通道元件的相鄰兩者之間；選擇性移除第二區中全部的犧牲層；在複數個第一垂直堆疊通道元件、複數個第二垂直堆疊通道元件和複數個第三垂直堆疊通道元件上方沉積第一功函數層；選擇性移除第一區中的第一功函數層和犧牲層；在複數個第一垂直堆疊通道元件、複數個第二垂直堆疊通道元件和複數個第三垂直堆疊通道元件上方沉積第二功函數層，第二功函數層不同於第一功函數層；在第二功函數層上方沉積鈍化層；選擇性移除第三區中的鈍化層、第一功函數層、第二功函數層和犧牲層；在複數個第一垂直堆疊通道元件、複數個第二垂直堆疊通道元件和複數個第三垂直堆疊通道元件上方沉積黏著層；以及在黏著層上方沉積金屬填充層，其中第一功函數層的組成大致相同於黏著層的組成。
在一些實施例中，第二功函數層包含鋁(Al)。在一些實施例中，犧牲層設置於複數個第三垂直堆疊通道元件的相鄰兩者之間的部分防止第一功函數層和第二功函數層沉積於複數個第三垂直堆疊通道元件的相鄰兩者之間。在一些範例中，其中在選擇性移除第二區中全部的犧牲層包含使用對犧牲層具有蝕刻選擇性的蝕刻劑。
前述內文概述了許多實施例的特徵，使本技術領域中具有通常知識者可以從各個方面更加了解本發明實施例。本技術領域中具有通常知識者應可理解，且可輕易地以本發明實施例為基礎來設計或修飾其他製程及結構，並以此達到相同的目的及/或達到與在此介紹的實施例等相同之優點。本技術領域中具有通常知識者也應了解這些相等的結構並未背離本發明的發明精神與範圍。在不背離本發明的發明精神與範圍之前提下，可對本發明實施例進行各種改變、置換或修改。舉例來說，透過設置不同厚度的位元線導體和字元線導體，可實現導體的不同電阻。然而，也可使用其他技術來改變金屬導體的電阻。
100:方法 102,104,106,108,110,112,114,116,118,120,122,124,126,128,130,132:方塊 200:工件 202:基底 204:半導體層 206:第二半導體層 208:第一半導體層 210A:第一鰭結構 210B:第二鰭結構 210C:第三鰭結構 212:介電隔離部件 214:虛設閘極結構 216:虛設閘極介電層 218:虛設閘極電極 220:閘極頂部硬遮罩 221:閘極間隙壁 222:界面層 228:閘極介電層 230:犧牲層 230’:剩餘犧牲層 232,236,242:圖案化硬遮罩 234:第一功函數層 238:第二功函數層 240:鈍化層 244:黏著層 246:金屬填充層 250A:第一金屬閘極堆疊物 250B:第二金屬閘極堆疊物 250C:第三金屬閘極堆疊物 260A:第一全繞式閘極電晶體 260B:第二全繞式閘極電晶體 260C:第三全繞式閘極電晶體 1000:第一區 1100:第一通道區 2081:第一通道元件 2000:第二區 2100:第二通道區 2082:第二通道元件 3000:第三區 3100:第三通道區 2083:第三通道元件
根據以下的詳細說明並配合所附圖式可以更加理解本發明實施例。應注意的是，根據本產業的標準慣例，圖示中的各種部件(feature)並未必按照比例繪製。事實上，可能任意的放大或縮小各種部件的尺寸，以做清楚的說明。也應強調的是，附圖僅顯示出本發明的典型實施例，因此不應視為對範圍的限制，本發明可同等地應用於其他實施例中。 第1圖為依據本發明一實施例之半導體裝置的形成方法的流程圖。 第2A圖為依據本發明各個方面之工件的第一區域的概略透視圖。 第2B圖為依據本發明各個方面之工件的第二區域的概略透視圖。 第2C圖為依據本發明各個方面之工件的第三區域的概略透視圖。 第3-23圖顯示依據第1圖的方法，在製造的各個階段之工件的第一區域和第二區域的局部剖面示意圖。
200:工件
222:界面層
228:閘極介電層
234:第一功函數層
238:第二功函數層
240:鈍化層
244:黏著層
246:金屬填充層
250A:第一金屬閘極堆疊物
250B:第二金屬閘極堆疊物
250C:第三金屬閘極堆疊物
260A:第一全繞式閘極電晶體
260B:第二全繞式閘極電晶體
260C:第三全繞式閘極電晶體
1000:第一區
2081:第一通道元件
2000:第二區
2082:第二通道元件
3000:第三區
2083:第三通道元件

Claims (15)

  1. 一種半導體裝置，包括：一第一全繞式閘極電晶體，包括：一第一複數個通道元件；一界面層，位於該第一複數個通道元件上方；一閘極介電層，位於該界面層上方；一第一功函數層，位於該閘極介電層上方並接觸該閘極介電層；及一黏著層，位於該第一功函數層上方；一第二全繞式閘極電晶體，包括：一第二複數個通道元件；該界面層，位於該第二複數個通道元件上方；該閘極介電層，位於該界面層上方；一第二功函數層，位於該閘極介電層上方並接觸該閘極介電層；該第一功函數層，位於該第二功函數層上方並接觸該第二功函數層；及該黏著層，位於該第一功函數層上方；以及一第三全繞式閘極電晶體，包括：一第三複數個通道元件；該界面層，位於該第三複數個通道元件上方；該閘極介電層，位於該界面層上方；及該黏著層，位於該閘極介電層上方。
  2. 如請求項1之半導體裝置，其中該第一功函數層包括鋁(Al)、鈦鋁(TiAl)、碳化鈦鋁(TiAlC)、碳化鉭鋁(TaAlC)、矽化鉭鋁(TaSiAl)、碳化鉭矽 (TaSiC)、矽化鉭(TaSi)或碳化鉿(HfC)，其中該第二功函數層包括氮化鈦(TiN)、氮化鈦矽(TiSiN)、氮化鉭(TaN)、氮碳化鎢(WCN)或鉬(Mo)。
  3. 如請求項2之半導體裝置，其中該黏著層包括氮化鈦(TiN)、氮化鈦矽(TiSiN)、氮化鉭(TaN)、氮碳化鎢(WCN)或鉬(Mo)。
  4. 如請求項1至3中任一項之半導體裝置，其中該第一全繞式閘極電晶體更包括一鈍化層設置於該第一功函數層與該黏著層之間，其中該第二全繞式閘極電晶體更包括該鈍化層設置於該第一功函數層與該黏著層之間，其中該第三全繞式閘極電晶體不具有該鈍化層。
  5. 如請求項1至3中任一項之半導體裝置，其中該第一全繞式閘極電晶體、該第二全繞式閘極電晶體和該第三全繞式閘極電晶體的每一者更包括一金屬填充層位於該黏著層上方，其中該金屬填充層包括鎢(W)或鈷(Co)。
  6. 如請求項1至3中任一項之半導體裝置，其中該第一功函數層完全地圍繞該第一複數個通道元件的每一者設置。
  7. 一種半導體裝置的形成方法，包括：提供一工件，該工件包括一基底、在該基底的一第一區中的複數個第一垂直堆疊通道元件、在該基底的一第二區中的複數個第二垂直堆疊通道元件及在該基底的一第三區中的複數個第三垂直堆疊通道元件；在該複數個第一垂直堆疊通道元件、該複數個第二垂直堆疊通道元件和該複數個第三垂直堆疊通道元件上方沉積一閘極介電層；在該閘極介電層上方沉積一犧牲層；蝕刻該犧牲層，使得該犧牲層的一部分保留在該複數個第一垂直堆疊通道元件的相鄰兩者之間、該複數個第二垂直堆疊通道元件的相鄰兩者之間和該複數 個第三垂直堆疊通道元件的相鄰兩者之間；選擇性移除該第二區中全部的該犧牲層；在該複數個第一垂直堆疊通道元件、該複數個第二垂直堆疊通道元件和該複數個第三垂直堆疊通道元件上方沉積一第一功函數層；選擇性移除該第一區中的該第一功函數層和該犧牲層；在該複數個第一垂直堆疊通道元件、該複數個第二垂直堆疊通道元件和該複數個第三垂直堆疊通道元件上方沉積一第二功函數層，該第二功函數層不同於該第一功函數層；以及在該第二功函數層上方沉積一鈍化層。
  8. 如請求項7之半導體裝置的形成方法，其中提供該工件的步驟包括：在該基底的該第一區、該第二區和該第三區上方形成複數個交替的半導體層，該複數個交替的半導體層包括複數個第一半導體層和夾設於該複數個第一半導體層之間的複數個第二半導體層；將該複數個交替的半導體層圖案化，以在該第一區中形成一第一主動區，在該第二區中形成一第二主動區，及在該第三區中形成一第三主動區；以及選擇性移除該複數個第二半導體層，以在該第一主動區中形成該複數個第一垂直堆疊通道元件，在該第二主動區中形成該複數個第二垂直堆疊通道元件，且在該第三主動區中形成該複數個第三垂直堆疊通道元件。
  9. 如請求項7或8之半導體裝置的形成方法，其中蝕刻該犧牲層暴露出設置於該複數個第一垂直堆疊通道元件、該複數個第二垂直堆疊通道元件和該複數個第三垂直堆疊通道元件的側面上的該閘極介電層。
  10. 如請求項7或8之半導體裝置的形成方法，其中該犧牲層包括氧化矽或氮化矽。
  11. 如請求項7或8之半導體裝置的形成方法，更包括：選擇性移除該第三區中的該鈍化層、該第一功函數層、該第二功函數層和該犧牲層；在該複數個第一垂直堆疊通道元件、該複數個第二垂直堆疊通道元件和該複數個第三垂直堆疊通道元件上方沉積一黏著層；以及在該黏著層上方沉積一金屬填充層。
  12. 一種半導體裝置的形成方法，包括：提供一工件，該工件包括一基底、在該基底的一第一區中的複數個第一垂直堆疊通道元件、在該基底的一第二區中的複數個第二垂直堆疊通道元件及在該基底的一第三區中的複數個第三垂直堆疊通道元件；在該複數個第一垂直堆疊通道元件、該複數個第二垂直堆疊通道元件和該複數個第三垂直堆疊通道元件上方沉積一閘極介電層；在該閘極介電層上方沉積一犧牲層；部分及選擇性蝕刻該犧牲層，使得該犧牲層的一部分設置於該複數個第一垂直堆疊通道元件的相鄰兩者之間、該複數個第二垂直堆疊通道元件的相鄰兩者之間和該複數個第三垂直堆疊通道元件的相鄰兩者之間；選擇性移除該第二區中全部的該犧牲層；在該複數個第一垂直堆疊通道元件、該複數個第二垂直堆疊通道元件和該複數個第三垂直堆疊通道元件上方沉積一第一功函數層；選擇性移除該第一區中的該第一功函數層和該犧牲層； 在該複數個第一垂直堆疊通道元件、該複數個第二垂直堆疊通道元件和該複數個第三垂直堆疊通道元件上方沉積一第二功函數層，該第二功函數層不同於該第一功函數層；在該第二功函數層上方沉積一鈍化層；選擇性移除該第三區中的該鈍化層、該第一功函數層、該第二功函數層和該犧牲層；在該複數個第一垂直堆疊通道元件、該複數個第二垂直堆疊通道元件和該複數個第三垂直堆疊通道元件上方沉積一黏著層；以及在該黏著層上方沉積一金屬填充層，其中該第一功函數層的組成大致相同於該黏著層的組成。
  13. 如請求項12之半導體裝置的形成方法，其中該第二功函數層包括鋁(Al)。
  14. 如請求項13之半導體裝置的形成方法，其中該犧牲層設置於該複數個第三垂直堆疊通道元件的相鄰兩者之間的部分防止該第一功函數層和該第二功函數層沉積於該複數個第三垂直堆疊通道元件的相鄰兩者之間。
  15. 如請求項12至14中任一項之半導體裝置的形成方法，其中在選擇性移除該第二區中全部的該犧牲層包括使用對該犧牲層具有一蝕刻選擇性的一蝕刻劑。
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