CN113270367A - 半导体装置的制作方法 - Google Patents

半导体装置的制作方法 Download PDF

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Publication number
CN113270367A
CN113270367A CN202110156303.2A CN202110156303A CN113270367A CN 113270367 A CN113270367 A CN 113270367A CN 202110156303 A CN202110156303 A CN 202110156303A CN 113270367 A CN113270367 A CN 113270367A
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layer
dielectric layer
drain
source
fin
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王培勋
江国诚
王志豪
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供一种半导体装置的制作方法。半导体装置的制作方法包括形成自基板凸起的鳍状物，且鳍状物具有相对的第一侧壁与第二侧壁；形成牺牲介电层于鳍状物的上表面、第一侧壁与第二侧壁上；蚀刻牺牲介电层，以自鳍状物的第二侧壁移除牺牲介电层；形成凹陷于鳍状物中；自凹陷成长外延的源极/漏极结构，外延的源极/漏极结构具有相对的第一侧壁与第二侧壁，其中牺牲介电层覆盖外延的源极/漏极结构的第一侧壁；使牺牲介电层凹陷，以露出外延的源极/漏极结构的第一侧壁；以及形成源极/漏极接点于外延的源极/漏极结构的第一侧壁上。

Description

半导体装置的制作方法
技术领域
本发明实施例涉及半导体装置与其制作方法，尤其涉及制作场效晶体管如鳍状场效晶体管、全绕式栅极场效晶体管及/或其他场效晶体管的方法。
背景技术
半导体集成电路产业已经历指数成长。集成电路材料与设计的技术进展，使每一代的集成电路比前一代具有更小且更复杂的电路。在集成电路演进中，功能密度(比如单位芯片面积的内连线装置数目)通常随着几何尺寸(比如制作工艺所能产生的最小构件或线路)缩小而增加。尺寸缩小的工艺通常有利于增加产能并降低相关成本。尺寸缩小亦会增加处理与制造集成电路的复杂度。
举例来说，随着装置尺寸持续缩小，减少源极/漏极结构与源极/漏极金属接点之间的接点电阻的挑战更高。具体而言，在形成源极/漏极金属接点时，相邻的源极/漏极区之间的有限空间会减少金属接点着陆面积并加大金属接点电阻，此亦降低装置集成程度。虽然解决这些挑战的方法一般适用，但仍无法完全符合所有方面的需求。本发明实施例的主题之一为进一步改善源极/漏极金属接点的形成方法。
发明内容
本发明实施例的目的在于提供一种半导体装置的制作方法，以解决上述至少一个问题。
在本发明一例中，提供半导体装置的制作方法。方法包括形成自基板凸起的鳍状物，且鳍状物具有相对的第一侧壁与第二侧壁；形成牺牲介电层于鳍状物的上表面、第一侧壁与第二侧壁上；蚀刻牺牲介电层，以自鳍状物的第二侧壁移除牺牲介电层；形成凹陷于鳍状物中；自凹陷成长外延的源极/漏极结构，外延的源极/漏极结构具有相对的第一侧壁与第二侧壁，其中牺牲介电层覆盖外延的源极/漏极结构的第一侧壁；使牺牲介电层凹陷，以露出外延的源极/漏极结构的第一侧壁；以及形成源极/漏极接点于外延的源极/漏极结构的第一侧壁上。
在本发明另一例中，提供半导体装置的制作方法。方法包括形成自基板凸起的第一半导体鳍状物与第二半导体鳍状物；形成第一介电层，以顺应性地覆盖第一半导体鳍状物、第二半导体鳍状物与基板；自第一半导体鳍状物与第二半导体鳍状物之间的区域移除第一介电层的第一部分；沉积第二介电层于第一半导体鳍状物与第二半导体鳍状物之间的区域中；成长外延的源极/漏极结构于第一半导体鳍状物与第二半导体鳍状物上，其中第一介电层覆盖每一外延的源极/漏极结构的第一侧壁，而第二介电层覆盖每一外延的源极/漏极结构的第二侧壁；自第一侧壁移除第一介电层的第二部分，以露出第一侧壁；以及形成金属接点于第一侧壁上。
在本发明又一例中，提供半导体装置。半导体装置包括半导体鳍状物，位于基板上；第一介电层与第二介电层，位于基板上，且半导体鳍状物夹设于第一介电层与第二介电层之间，其中第一介电层与第二介电层的材料组成不同；外延的源极/漏极区结构，位于半导体鳍状物上，其中外延的源极/漏极结构的延伸部分延伸于第一介电层与第二介电层上；以及源极/漏极接点，位于外延的源极/漏极结构上，其中源极/漏极接点部分地覆盖外延的源极/漏极结构的上表面，并连续延伸以包覆外延的源极/漏极结构其面对第一介电层的侧壁。
本发明实施例的有益效果在于，本发明实施例提供源极/漏极接点的形成方法，其可部分包覆外延的源极/漏极结构。本发明实施例包括在栅极置换工艺之后形成源极/漏极接点，其与外延的源极/漏极结构的上表面的一部分与一侧壁具有接触界面。综上所述，半包覆的设置可减少下方的外延的源极/漏极结构与上方的源极/漏极接点之间的接点电阻。
附图说明
图1A及图1B为本发明一些实施例中，制造半导体装置的方法的流程图。
图2、图3、图4、图5、图6、图7、图8及图9为本发明一些实施例中，半导体装置在图1A及图1B的方法的中间阶段沿着X方向切面的剖视图。
图10A为本发明一些实施例中，半导体装置的三维透视图。
图10B为本发明一些实施例中，半导体装置的平面俯视图。
图11A、图11A'、图12A、图13A、图14A、图15A、图16A及图17A为本发明一些实施例中，半导体装置在图1A及图1B的方法的中间阶段沿着Y方向切面的剖视图。
图11B、图11B'、图12B、图13B、图14B、图15B、图16B、图17B及图17B'为本发明一些实施例中，半导体装置在图1A及图1B的方法的中间阶段沿着X方向切面的剖视图。
附图标记如下：
A,B:着陆点
A-A’,B-B’:剖面
H1,H2:高度
W1,W2:宽度
S204:侧壁
100:方法
102,104,106,108,110,112,114,116,118,120,122,124,126,128,130,132:步骤
200:半导体装置
202:基板
204:半导体鳍状物
204a,204b:半导体材料
206,236,238:硬掩模层
208:衬垫层
210:绝缘材料层
212:蚀刻停止层
214:牺牲介电层
216:光刻胶层
218:沟槽
220:介电鳍状物
222:盖层
224,234:界面层
230:虚置栅极堆叠
232:虚置栅极
240:介电层
242:栅极间隔物层
242a:第一栅极间隔物层
242b:第二栅极间隔物层
250:凹陷
252:源极/漏极结构
254,256,258:层状物
260:气隙
262:接点蚀刻停止层
264:层间介电层
270:金属栅极结构
276:接点沟槽
282:源极/漏极接点
具体实施方式
下述详细描述可搭配附图说明，以利理解本发明的各方面。值得注意的是，各种结构仅用于说明目的而未按比例绘制，如本业常态。实际上为了清楚说明，可任意增加或减少各种结构的尺寸。
下述内容提供的不同实施例或例子可实施本发明实施例的不同结构。特定构件与排列的实施例用以简化本公开而非局限本发明。举例来说，形成第一构件于第二构件上的叙述包含两者直接接触，或两者之间隔有其他额外构件而非直接接触。此外，本发明的多种实例可重复采用相同标号以求简洁，但多种实施例及/或设置中具有相同标号的元件并不必然具有相同的对应关系。
此外，本发明实施例的结构形成于另一结构上、连接至另一结构及/或耦接至另一结构中，结构可直接接触另一结构，或可形成额外结构于结构及另一结构之间。此外，空间性的相对用语如“下方”、“其下”、“下侧”、“上方”、“上侧”或类似用语可用于简化说明某一元件与另一元件在图示中的相对关系。空间性的相对用语可延伸至以其他方向使用的元件，而非局限于图示方向。举例来说，若将附图中的装置翻转，则下方或之下的元件将转为上方或之上的元件。方向性用语仅用以说明图示中的方向。此外，当数值或数值范围的描述有“约”、“近似”或类似用语时，除非特别说明否则其包含所述数值的+/-10％。举例来说，用语“约5nm”包含的尺寸范围为4.5nm至5.5nm。
本发明实施例一般关于半导体装置与其制作方法，更特别关于制作场效晶体管如鳍状场效晶体管、全绕式栅极场效晶体管及/或其他场效晶体管的方法。
在半导体制作中，在形成接点沟槽(亦视作接点孔)于外延的源极/漏极结构上之后，形成源极/漏极金属接点(之后视作源极/漏极接点)于外延的源极/漏极结构的上表面上。如此一来，源极/漏极接点与外延的源极/漏极结构之间的接点面积受限于外延的源极/漏极结构的顶部，可能造成较高的接点电阻。改善源极/漏极接点的形成方法可为加大接点沟槽，以露出外延的源极/漏极结构的侧壁。如此一来，形成于接点沟槽中的源极/漏极接点与外延的源极/漏极结构的侧壁具有额外的接点面积(除了上表面以外)。比如源极/漏极接点包覆外延的源极/漏极结构的三侧。然而随着技术节点发展，减少相邻的外延的源极/漏极结构之间的空间，会限制形成源极/漏极接点的工艺容许范围。举例来说，由于导电材料填入狭窄沟槽的能力不良，在形成源极/漏极接点于接点沟槽中时，可能形成空洞于外延的源极/漏极结构的侧壁上。此外，源极/漏极接点的包覆部分减少相邻的源极/漏极接点之间的有效空间，在施加不同电压至相邻的源极/漏极接点时，可能增加电性击穿的风险。
本发明实施例提供的源极/漏极接点沉积于外延的源极/漏极结构的一侧壁与上表面上，但不沉积于另一侧的侧壁上。外延的源极/漏极结构的一侧壁上的额外接点面积，可降低接点电阻。与此同时，外延的源极/漏极结构的另一侧壁实质上不接触源极/漏极接点，如同源极/漏极接点半包覆外延的源极/漏极结构，其可加大相邻的源极/漏极接点之间的距离并改善装置的击穿效能。在一些实施例中，在形成接点沟槽之前沉积牺牲介电层。在形成接点沟槽时，可部分地移除牺牲介电层，且之后可置换为源极/漏极接点。综上所述，牺牲介电层保留源极/漏极接点所用的区域，且形成源极/漏极接点的步骤为自对准步骤。此外，控制牺牲介电层的厚度亦可确认接点沟槽的宽度，且可最佳化牺牲介电层的厚度以利导电材料填入接点沟槽，并避免形成空洞于外延的源极/漏极结构的侧壁上。
图1A及图1B显示本发明一些实施例中，形成半导体装置200(之后可视作装置)的方法100的流程图。方法100仅为举例而非局限本发明实施例至权利要求未实际记载处。在方法100之前、之中与之后可进行额外步骤，且方法的额外实施例可置换、省略或调换一些步骤。下述方法100将搭配其他附图说明如下，且其他附图显示半导体装置200在方法100的中间步骤时的多种三维图与剖视图。具体而言，图2、图3、图4、图5、图6、图7、图8、图9、图11B、图11B'、图12B、图13B、图14B、图15B、图16B、图17B、图17B'为半导体装置200沿着源极/漏极区中的X方向切面(即垂直于鳍状物的长度方向)的剖视图。图11B、图11B'、图12B、图13B、图14B、图15B、图16B、图17B、即图17B'为半导体装置200沿着Y方向切面(即沿着鳍状物的长度方向)的剖视图。图10A为半导体装置200的三维图。图10B为半导体装置200的平面俯视图。
半导体装置200可为制作集成电路或其部分时的中间装置，其可包含静态随机存取存储器及/或其他逻辑电路、无源构件(如电阻、电容器或电感)或有源构件(如p型场效晶体管、n型场效晶体管、鳍状场效晶体管、金属氧化物半导体场效晶体管、互补式金属氧化物半导体晶体管、双极晶体管、高电压晶体管、高频晶体管及/或其他存储器单元)。本发明实施例不限于任何特定数目的装置或装置区或任何特定的装置设置。举例来说，虽然附图中的半导体装置200为三维场效晶体管装置(如鳍状场效晶体管或全绕式栅极场效晶体管)，本发明实施例亦可用于制作平面场效晶体管装置。
如图1A及图2所示，方法100的步骤102提供半导体装置200，其包括自基板202凸起的一或多个半导体鳍状物204。基板202可包含半导体元素(单一元素)如硅、锗及/或其他合适材料；半导体化合物如碳化硅、砷化镓、磷化镓、磷化铟、砷化铟、锑化铟及/或其他合适材料；或半导体合金如硅锗、磷砷化镓、砷化铝铟、砷化铝镓、砷化镓铟、磷化镓铟、磷砷化镓铟及/或其他合适材料。基板202可为组成一致的单层材料。在其他实施例中，基板202可包含类似或不同组成的多个材料层，其适于制造集成电路装置。在一例中，基板202可为绝缘层上硅基板，其具有硅层形成于氧化硅层上。在另一例中，基板202可包含导电层、半导体层、介电层、其他层或上述的组合。
在一些实施例中，基板202包括场效晶体管或多种掺杂区如源极/漏极区位于基板202之中或之上。掺杂区可掺杂p型掺质如磷或砷，及/或n型掺质如硼或二氟化硼，端视设计需求而定。掺杂区可直接形成于基板202上、p型井结构中、n型井结构中或双井结构中，或采用隆起结构。掺杂区的形成方法可为注入掺质原子、原位掺杂外延成长及/或其他合适技术。
每一半导体鳍状物204适于提供n型场效晶体管或p型场效晶体管。在一些实施例中，此处所示的半导体鳍状物204适于提供类似型态(如n型或p型)的鳍状场效晶体管。在其他实施例中，其适于提供相反型态(如n型与p型)的鳍状场效晶体管。此设置仅用于说明目的而非局限本发明实施例。半导体鳍状物204的制作方法可采用合适工艺，包括光刻与蚀刻工艺。光刻工艺可包含形成硬掩模层206于基板202上，并形成光刻胶层于硬掩模层206上。显影光刻胶至一图案，进行曝光后烘烤工艺，与显影光刻胶以形成图案化的光刻胶层。接着采用图案化的光刻胶层与蚀刻工艺转移图案至硬掩模层206。硬掩模层206可包含介电层如氧化硅、氮化硅、氮氧化硅及/或碳化硅。在例示性的实施例中，硬掩模层206可包含氮化硅。接着经由硬掩模层206的图案中的开口蚀刻基板202，以保留半导体鳍状物204于基板202上。蚀刻工艺可包含干蚀刻、湿蚀刻、反应性离子蚀刻及/或其他合适工艺。
形成半导体鳍状物204所用的多种方法的实施例亦适用。举例来说，可采用双重图案化或多重图案化工艺图案化半导体鳍状物204。一般而言，双重图案化或多重图案化工艺结合光刻与自对准工艺，其产生的图案间距可小于采用单一的直接光刻工艺所得的图案间距。举例来说，一实施例形成牺牲层于基板上，并采用光刻工艺图案化牺牲层。采用自对准工艺，以沿着图案化的牺牲层侧部形成间隔物。接着移除牺牲层，而保留的间隔物或芯可用于图案化鳍状物。在一些实施例中，在形成半导体鳍状物204之后，半导体鳍状物204沿着Z方向的高度H1介于约40nm至约70nm之间，而半导体鳍状物204的上侧部分沿着X方向的宽度W1介于约10nm至约40nm之间。
如图1A及图3所示，方法100的步骤104形成一系列的介电层于半导体装置200上。在一些实施例中，可顺应性地形成含一或多层的绝缘材料的绝缘材料层210，且形成方法可采用化学气相沉积、原子层沉积或其他合适方法。以顺应性的方式沉积绝缘材料层210，使其在半导体鳍状物204的上表面与垂直表面(如侧壁)以及基板202的水平表面上具有实质上相同的厚度。在一些实施例中，绝缘材料层210的沉积厚度为约10nm至约40nm。绝缘材料层210所用的绝缘材料可包含氧化硅、氮化硅、氮氧化硅、碳氮氧化硅、碳氮化硅、掺杂氟的硅酸盐玻璃或低介电常数的介电材料。
在一些实施例中，在形成绝缘材料层210之前可视情况形成衬垫层208于半导体装置200上。衬垫层208的组成可为氧化硅或氮化硅为主的材料(如氮化硅、碳氮化硅或碳氮氧化硅)。可先顺应性地沉积衬垫层208于半导体鳍状物204与基板202上，且沉积方法可为化学气相沉积、原子层沉积或其他合适方法。接着沉积绝缘材料层210所用的绝缘材料于衬垫层208上。
方法100的步骤104在形成绝缘材料层210之后，亦形成蚀刻停止层212。蚀刻停止层212包括的介电材料与绝缘材料层210不同。在一些实施例中，蚀刻停止层212的组成为高介电常数(比如大于氧化硅的介电常数(约3.9))的介电材料，比如金属氧化物如氧化铪、氧化锆、氧化铝或上述的组合。顺应性形成蚀刻停止层212的方法可采用化学气相沉积、原子层沉积或其他合适方法。在一些实施例中，蚀刻停止层212的沉积厚度为约2nm至约5nm。
方法100的步骤104在形成蚀刻停止层之后，更形成牺牲介电层214。牺牲介电层214包含的介电材料与蚀刻停止层212不同。在一些实施例中，牺牲介电层214的组成为碳氧化硅、碳氮氧化硅或上述的组合。顺应性形成牺牲介电层214的方法可采用化学气相沉积、原子层沉积或其他合适方法。牺牲介电层214可保留形成接点沟槽所用的空间，且接点沟槽露出成长于半导体鳍状物204上的外延的源极/漏极结构的侧壁，如下所述。在多种实施例中，牺牲介电层214沿着X方向的宽度W2为半导体鳍状物204的宽度W1的约15％至约100％，比如约25％。在多种实施例中，当宽度W2大于约15％的宽度W1，就算导电材料在高深宽比沟槽中的填隙能力有限，填入接点沟槽的导电材料实质上无空洞。另一方面，当宽度W2小于约15％的宽度W1，则可能形成空洞于沟槽中，其将增加源极/漏极接点与外延的源极/漏极结构之间的接点电阻。若宽度W2大于约100％的宽度W1，则需增加半导体鳍状物204之间的空间以容纳较大宽度的牺牲介电层214，其会影响芯片尺寸并增加制造成本。在具体例子中，牺牲介电层214的宽度W2为约5nm至约10nm。
如图1A、图4及图5所示，方法100的步骤106部分地移除半导体鳍状物204之间的牺牲介电层214与蚀刻停止层212，以形成沟槽218。步骤106可包含多种工艺，比如光刻与蚀刻。光刻工艺可包含形成光刻胶层216于半导体装置200上。例示性的光刻胶包括对射线如紫外光、深紫外射线及/或极紫外射线敏感的光敏材料。在半导体装置200上进行光刻曝光，使光刻胶层216的选定区域曝光至射线。曝光造成光刻胶层216的曝光区中的化学反应。在曝光之后，对光刻胶层216施加显影剂。显影剂可溶解或移除正型光刻胶显影工艺中的曝光区，或负型光刻胶显影工艺中的非曝光区。合适的正型显影剂包括氢氧化四甲基铵、氢氧化钾或氢氧化钠，而合适的负型显影剂包括溶剂如乙酸正丁酯、乙醇、己烷、苯或甲苯。在显影光刻胶层216之后，可由蚀刻工艺如湿蚀刻、干蚀刻、反应性离子蚀刻、灰化及/或其他蚀刻方法移除牺牲介电层214与蚀刻停止层212的露出部分。在一些实施例中，蚀刻工艺包括不同蚀刻化学剂的多重蚀刻步骤，一蚀刻步骤的目标为牺牲介电层214的具体材料而不蚀刻蚀刻停止层212(如图4所示)，而另一蚀刻步骤的目标为蚀刻停止层212的具体材料而不蚀刻绝缘材料层210(如图5所示)。在形成沟槽218之后，以湿式剥除或等离子体灰化移除图案化的光刻胶层216。其他实施例在蚀刻牺牲介电层214之后与蚀刻蚀刻停止层212之前，可移除图案化的光刻胶层216。蚀刻停止层212的蚀刻方法可采用图案化的牺牲介电层214作为蚀刻掩模。
如图1A、图6及图7所示，方法100的步骤108形成介电鳍状物220(在一些例子中可视作虚置鳍状物或混合鳍状物)于沟槽218中。每一介电鳍状物220可位于半导体鳍状物204之间，其方向可实质上平行于半导体鳍状物204。然而与设置以提供有源装置的半导体鳍状物204不同，介电鳍状物220非有源且非设置以形成场效晶体管。在一些实施例中，提供介电鳍状物220以调整鳍状物至鳍状物的空间(如鳍状物间距)。介电鳍状物220亦有助于减少鳍状物图案化负载效应，并避免源极/漏极外延结构桥接。介电鳍状物220的形成方法可为任何合适方法。在图6所示的一例中，可先沉积介电鳍状物220的介电材料以填入沟槽218并覆盖半导体装置200。介电鳍状物220可包含任何合适的介电材料如碳氮化硅、碳氮氧化硅或金属氧化物(如氧化铪、氧化锆或氧化铝)及/或其他合适的介电材料，且其沉积方法可为任何合适的沉积工艺如化学气相沉积、物理气相沉积、原子层沉积及/或其他合适工艺。在一实施例中，介电鳍状物220包括化学气相沉积所沉积的氧化铝。在多种实施例中，介电鳍状物220的材料组成与牺牲介电层214或蚀刻停止层212的材料组成不同。在沉积之后，可进行化学机械研磨工艺以移除多余的介电材料。在一些实施例中，硬掩模层206可作为化学机械研磨停止层。之后可使介电鳍状物220的介电材料凹陷(比如以化学蚀刻工艺)，使其上表面低于半导体鳍状物204的上表面。步骤108亦可使蚀刻停止层212与牺牲介电层214凹陷，如图7所示。在所述实施例中，步骤108之后的蚀刻停止层212与牺牲介电层214只保留于半导体鳍状物204的一侧壁(背对相邻的半导体鳍状物204)上。此外，由于蚀刻停止层212与牺牲介电层214的厚度，多种介电鳍状物220的下表面不齐平，使直接形成于绝缘材料层210上的介电鳍状物220的下表面，低于形成于牺牲介电层214上的其他介电鳍状物220的下表面。
如图1A及图8所示，方法100的步骤110形成盖层222以覆盖介电鳍状物220、蚀刻停止层212与牺牲介电层214。盖层222与牺牲介电层214的介电材料不同。在一些实施例中，盖层222与蚀刻停止层212的介电材料不同。在一些其他实施例中，盖层222与蚀刻停止层212的介电材料相同。在具体例子中，盖层222的组成为高介电常数的介电材料如金属氧化物(如氧化铪、氧化锆、氧化铝或上述的组合)。盖层222的沉积方法可为任何合适的沉积工艺如化学气相沉积、物理气相沉积、原子层沉积及/或其他合适工艺。在沉积之后可进行化学机械研磨工艺以移除多余的介电材料。在所述实施例中，化学机械研磨工艺亦可移除硬掩模层206并露出半导体鳍状物204的上表面。盖层222的厚度可为约5nm至约20nm。
如图1A及图9所示，方法100的步骤112使绝缘材料层210凹陷，以露出半导体鳍状物204的上侧部分。在一些实施例中，绝缘材料层210的凹陷范围为约40nm至约80nm。步骤112亦使衬垫层208凹陷。此步骤形成的凹陷的绝缘材料层210可使半导体鳍状物204彼此之间电性隔离，因此可视作浅沟槽隔离区。在许多实施例中，方法100形成浅沟槽隔离区如凹陷的绝缘材料层210的方法可为合适的蚀刻工艺如干蚀刻工艺、湿蚀刻工艺或反应性离子蚀刻工艺。
如图1A、图10A、图10B及图11A至图11B'所示，方法100的步骤114形成多个虚置栅极堆叠230以接合半导体鳍状物204。具体而言，图10A显示半导体装置200在步骤114的三维图。图10B显示半导体装置200的平面俯视图。图11A显示半导体装置200沿着图10A及图10B所示的剖面A-A'(如半导体鳍状物204上的Y切面)的剖视图。图11A'显示图11A中的剖视图的其他实施例。图11B显示半导体装置200沿着图10A及图10B所示的剖面B-B'(源极/漏极区中的X切面)的剖视图。图11B'显示图11B中的剖视图的其他实施例。
每一虚置栅极堆叠230作为后续形成的高介电常数的栅极介电层与金属栅极结构的占位物。虚置栅极堆叠230可包含虚置栅极232与多种其他材料层。在一些实施例中，虚置栅极232包括多晶硅。在图11A所示的实施例中，虚置栅极堆叠可包含界面层234位于半导体鳍状物204与虚置栅极232之间、硬掩模层236位于虚置栅极232上及/或硬掩模层238位于硬掩模层236上。虚置栅极堆叠230的形成方法可为先毯覆性沉积虚置栅极堆叠的多种材料层。虚置栅极堆叠230的多种材料层的形成方法可为任何合适工艺，比如化学气相沉积、物理气相沉积、原子层沉积、化学氧化、其他合适工艺或上述的组合。之后可在虚置栅极堆叠230的多种材料层上进行图案化步骤，以形成虚置栅极堆叠于半导体鳍状物204上。如下详述，在制作半导体装置200的其他构件(如外延的源极/漏极结构)之后，可进行栅极置换工艺以将虚置栅极堆叠230的部分置换为高介电常数的栅极介电层与金属栅极。硬掩模层236及238可各自包含任何合适的介电材料，比如半导体氧化物及/或半导体氮化物。在一例中，硬掩模层236包含碳氮化硅，且硬掩模层238包含氧化硅。界面层224可包含任何合适材料如氧化硅。
如图11A及图11B所示，方法100的步骤114亦形成介电层240于半导体装置200上。在许多实施例中，介电层240可顺应性地形成于半导体装置200上，包括形成于半导体鳍状物204、介电鳍状物220上的盖层222与虚置栅极堆叠230上。介电层240可包含任何合适的介电材料如含氮的介电材料，且其形成方法可为任何合适方法如原子层沉积、化学气相沉积、物理气相沉积、其他合适方法或上述的组合。在所述实施例中，介电层240的形成方法可为热原子层沉积工艺。在一些例子中，介电层240可包含氮化硅、碳氮化硅、碳氮氧化硅、其他合适的介电材料或上述的组合。
方法100的步骤114亦形成栅极间隔物层242于介电层240上。与介电层240类似，栅极间隔物层242可顺应性地形成于虚置栅极堆叠230上。栅极间隔物层242可包含任何合适的介电材料如含氧介电材料或高介电常数的介电材料，且其形成方法可为任何合适方法如原子层沉积、化学气相沉积、物理气相沉积、其他合适方法或上述的组合。在一些实施例中，栅极间隔物242包括两个或更多材料层，比如第一栅极间隔物层242a与沉积于第一栅极间隔物层242a上的第二栅极间隔物层242b。在具体例子中，第一栅极间隔物层242a包括碳氮氧化硅、碳氧化硅、氮化硅或上述的组合，且其厚度为约2nm至约4nm。第二栅极间隔物层242b与第一栅极间隔物层242a的材料不同，且可为碳氮化硅、氮化硅或上述的组合，且其厚度可为约2nm至约4nm。
图11A'为一些其他实施例中，步骤114中的半导体装置200。图11A'中的半导体装置200在许多方面与图11A类似。差别之一为图11A'中的半导体鳍状物204可包含交错的不同半导体材料如半导体材料204a与半导体材料204b。在一些实施例中，半导体鳍状物204可包含总共三至十层的交错半导体材料层，而本发明实施例当然不限于此设置。在本发明实施例中，半导体材料204a包括硅，而半导体材料204b包括硅锗。半导体材料204a及204b的一者(或两者)可掺杂合适掺质如p型掺质或n型掺质，以形成所需的场效晶体管。半导体材料204a及204b的形成方法可各自为外延工艺如分子束外延工艺、化学气相沉积工艺(如有机金属化学气相沉积工艺)及/或其他合适的外延成长工艺。
如图11A'所示，许多实施例中交错的半导体材料204a及204b的层状物设置以提供多栅极装置如全绕式栅极场效晶体管，如下详述。多栅极装置可增加栅极-通道耦接、减少关闭状态电流与减少短通道效应，以改善栅极控制。多栅极装置如全绕式栅极场效晶体管通常包含栅极结构，其延伸于水平通道区周围，以自所有侧接触通道区。全绕式栅极场效晶体管通常与互补式金属氧化物半导体工艺相容，以大幅缩小尺寸并维持栅极控制与缓解短通道效应。本发明实施例当然不限于只形成全绕式栅极场效晶体管，且可提供许多其他三维场效晶体管如鳍状场效晶体管。如此一来，半导体鳍状物204可包含半导体材料的单层，或不同半导体材料的多层(非交错堆叠，可提供不一致的鳍状物以形成鳍状场效晶体管)，如图11A所示的相关说明。
图11B'所示的另一实施例为步骤114中的半导体装置200。图11B'中的半导体装置200的许多部分与图11B实质上类似，差异在于图11B'中的两个半导体鳍状物204可包含不同的半导体材料。举例来说，一半导体鳍状物204可包含硅以用于形成n型场效晶体管，而其他半导体鳍状物204可包含硅锗以用于形成p型场效晶体管。含硅锗的半导体鳍状物的形成方法可包含使硅鳍状物凹陷，并以外延工艺沉积硅锗，且外延工艺可为分子束外延工艺、化学气相沉积工艺(如有机金属化学气相沉积工艺)及/或其他合适的外延成长工艺。
如图1A、图12A及图12B所示，方法100的步骤116移除半导体鳍状物204的一部分以形成凹陷250于其中。在许多实施例中，方法100以合适的蚀刻工艺形成凹陷250，比如干蚀刻工艺、湿蚀刻工艺或反应性离子蚀刻工艺。在一些实施例中，方法100选择性移除半导体鳍状物204而不蚀刻或实质上不蚀刻蚀刻停止层212与介电鳍状物220的部分。如此处所述，步骤116可移除界面层234、介电层240及栅极间隔物层242的上侧部分以及形成于介电鳍状物220上的盖层222的上侧部分，以形成凹陷250。步骤116的蚀刻工艺可实施干蚀刻工艺，其可采用蚀刻剂如含溴气体(如溴化氢及/或溴仿)、含氟气体(如四氟化碳、六氟化硫、二氟甲烷、氟仿及/或六氟乙烷)、其他合适气体或上述的组合。调整蚀刻工艺时间，可控制半导体鳍状物204的移除量。在一些实施例中，步骤116的蚀刻工艺露出的介电鳍状物220的上侧部分的高度H2小于或等于约40nm。在一些实施例中，盖层222的保留厚度为约3nm至约10nm。
如图1B、图13A及图13B所示，方法100的步骤118自凹陷250开始成长外延的源极/漏极结构252。外延的源极/漏极结构252可包含多个外延半导体层，比如层状物254、256及258。在一些实施例中，层状物254、256及258中包含的掺质量不同。在一些例子中，由于掺杂工艺的特性，层状物254中包含的掺质量小于层状物258中包含的掺质量。在一些例子中，层状物258中包含的掺质量亦小于层状物256中包含的掺质量，以最小化漏电流的可能性。在一些例子中，层状物256中包含的掺质量约大于或等于层状物254中包含的掺质量。如图13B所示，外延的源极/漏极结构252一开始成长于凹陷250中，接着延伸高于介电鳍状物220。换言之，外延的源极/漏极结构252的横向成长不受凹陷的宽度限制，可更弹性地设计外延的源极/漏极结构尺寸。在所述实施例中，步骤118之后可保留气隙260于外延的源极/漏极结构252的底部两侧上(比如外延的源极/漏极结构252以其与其相邻的介电鳍状物220之间)。
外延的源极/漏极结构252(如包含其中的层状物254、256及258)的形成方法可为任何合适方法，比如分子束外延、有机金属化学气相沉积、其他合适的外延成长工艺或上述的组合。外延的源极/漏极结构252可为p型外延材料以适用于p型鳍状场效晶体管装置，或n型外延材料以适用于n型鳍状场效晶体管装置。p型外延材料可包含硅锗(外延硅锗)的一或多个外延层，而硅锗可掺杂p型掺质如硼、锗、铟及/或其他p型掺质。n型外延材料可包含硅(外延硅)或碳化硅(外延碳化硅)的一或多个外延层，而硅或碳化硅可掺杂n型掺质如砷、磷及/或其他n型掺质。在所述实施例中，以p型外延的源极/漏极结构252与相邻的n型外延的源极/漏极结构252做说明。
如图1B、图14A及图14B所示，方法100的步骤120形成层间介电层264于接点蚀刻停止层262上。接点蚀刻停止层262可包含氮化硅、氮氧化硅、碳氮氧化硅、其他合适材料或上述的组合，且其形成方法可为化学气相沉积、物理气相沉积、原子层沉积、其他合适方法或上述的组合。在一些实施例中，接点蚀刻停止层262可具有顺应性的轮廓于虚置栅极堆叠230与外延的源极/漏极结构252上。层间介电层264包括介电材料如四乙氧基硅烷的氧化物、未掺杂的硅酸盐玻璃或掺杂氧化硅(如硼磷硅酸盐玻璃、氟硅酸盐玻璃、磷硅酸盐玻璃或硼硅酸盐玻璃)、其他合适的介电材料或上述的组合。层间介电层264可包含多种介电材料的多层结构，且其形成方法可为沉积工艺如化学气相沉积、可流动的化学气相沉积、旋转涂布玻璃、其他合适方法或上述的组合。在一些实施例中，形成层间介电层264的方法还包括进行化学机械研磨工艺，以平坦化半导体装置200的上表面，使虚置栅极堆叠230的上表面露出。
如图1B、图14A及图14B所示，方法100的步骤122进行栅极置换工艺以将虚置栅极堆叠230置换成个别的金属栅极结构270。在一些实施例中，每一金属栅极结构270为高介电常数的栅极介电层与金属栅极结构，其中高介电常数的栅极介电层的介电常数大于氧化硅的介电常数(约3.9)。步骤122的栅极置换工艺所实施的一系列制作步骤如下详述。
方法100的步骤122以任何合适方法移除虚置栅极堆叠230，以形成栅极沟槽(未图示)于半导体鳍状物204上。形成栅极沟槽的方法可包含一或多道蚀刻工艺，其对虚置栅极堆叠230中包含的材料(如虚置栅极中包含的多晶硅)具有选择性。蚀刻工艺可包含干蚀刻、湿蚀刻、反应性离子蚀刻、其他合适的蚀刻方法或上述的组合。对需要多栅极装置如全绕式栅极场效晶体管的实施例而言，以图11A'为例，蚀刻工艺可自半导体鳍状物204选择性地移除半导体材料204b(含硅锗)，使空洞或间隙(未图示)形成于半导体材料204a(包含硅)的堆叠之间。在一些实施例中，蚀刻工艺可为选择性干蚀刻工艺或湿蚀刻工艺。
方法100接着形成金属栅极结构270于栅极沟槽中。对半导体鳍状物204包括半导体材料204a及204b的交错堆叠的实施例而言，自半导体装置200移除半导体材料204b后，可沉积金属栅极结构270的多种材料层于半导体材料204a的层状物之间的间隙中。虽然未图示，金属栅极结构270可包含多个材料层如高介电常数的栅极介电层形成于界面层上、功函数金属层形成于高介电常数的栅极介电层上、基体导电层形成于功函数金属层上、其他合适层或上述的组合。高介电常数的介电层可包含一或多种高介电常数的介电材料(或一或多层的高介电常数的介电材料)，比如氧化铪硅、氧化铪、氧化铝、氧化锆、氧化镧、氧化钛、氧化钇、钛酸锶或上述的组合。功函数金属层可包含任何合适材料如氮化钛、氮化钽、钌、钼、钨、铂、钛、铝、碳化钽、碳氮化钽、氮化钽硅、氮化钛硅、其他合适材料或上述的组合。在一些实施例中，功函数金属层包括多种相同型态或不同型态的多个材料层(比如均为n型功函数金属或均为p型功函数金属)，以达所需的临界电压。基体导电层可包含铝、铜、钨、钴、钌、其他合适的导电材料或上述的组合。金属栅极结构270可包含其他材料层，比如阻挡层、粘着层及/或盖层。金属栅极结构270的多种层状物的形成方法可为任何合适方法，比如化学气相沉积、原子层沉积、物理气相沉积、电镀、化学氧化、热氧化、其他合适方法或上述的组合。方法100之后可进行一或多道研磨工艺(如化学机械研磨)，以移除多余的导电材料，并平坦化半导体装置200的上表面。
如图1B与图15A至图15B所示，方法100的步骤124进行图案化工艺，以形成接点沟槽276(亦视作接点孔)于层间介电层264中。接点沟槽276偏离外延的源极/漏极结构252的中心，使接点沟槽276中露出外延的源极/漏极结构252的部分上表面。在所述实施例中，接点蚀刻停止层262与层间介电层264可维持覆盖外延的源极/漏极结构252的上表面较靠近相邻的源极/漏极结构252的一部分。形成接点沟槽276的方法包括以光刻工艺形成图案化的光刻胶层，其具有开口以定义接点沟槽276所用的区域；经由图案化的光刻胶层的开口蚀刻层间介电层264与接点蚀刻停止层262；以及以湿式剥除或等离子体灰化移除图案化的光刻胶层。可另外采用硬掩模以图案化接点沟槽276。接点沟槽276中亦露出盖层222与蚀刻停止层212。
如图1B、图15A及图15B所示，方法100的步骤126进行一或多道选择性蚀刻工艺，以移除接点沟槽276中露出的盖层222的一部分，并经由盖层222中的开口使之前形成的牺牲介电层214凹陷。在一些例子中，蚀刻工艺可为一或多道等向蚀刻工艺(如等向干蚀刻或等向湿蚀刻工艺)，其实施的蚀刻剂可包含氢氟酸、氨、三氟化氮、其他合适蚀刻剂或上述的组合。调整蚀刻工艺的时间，可控制牺牲介电层214的凹陷量。在一些实施例中，步骤126的蚀刻工艺使牺牲介电层214凹陷的深度可为约10nm至约60nm。蚀刻工艺使牺牲介电层214凹陷，而不蚀刻或实质上不蚀刻蚀刻停止层212。蚀刻停止层212在蚀刻工艺时，可保护外延的源极/漏极结构252的侧避免于额外蚀刻。
如图1B、图16A及图16B所示，方法100的步骤128进行选择性蚀刻以使蚀刻停止层212凹陷，进而露出外延的源极/漏极结构252的一侧壁表面。蚀刻工艺可包含任何合适的蚀刻技术如湿蚀刻、干蚀刻、反应性离子蚀刻、灰化及/或其他蚀刻方法。选择蚀刻剂以蚀刻蚀刻停止层212而不蚀刻或实质上不蚀刻牺牲介电层214与外延的源极/漏极结构252。可调整蚀刻工艺的时间以控制蚀刻停止层212的凹陷量。因此一些实施例的蚀刻停止层212的上表面与牺牲介电层214的上表面可实质上齐平，端视蚀刻工艺的时间而定。在一些其他实施例中，蚀刻停止层212的上表面可高于牺牲介电层214的上表面。在一些其他实施例中，蚀刻停止层212的上表面可低于牺牲介电层214的上表面。牺牲介电层214与蚀刻停止层212可一起设置为保留良好定义的接点沟槽宽度(由牺牲介电层214与蚀刻停止层212的总厚度所定义)。接点沟槽276的位置可由自对准确认。值得注意的是，接点沟槽276中亦露出外延的源极/漏极结构252的露出的侧壁表面上的气隙260。与此相较，另一侧壁上的气隙260仍保留于外延的源极/漏极结构252与介电鳍状物220之间。
如图1B与图17A至图17B'所示，方法100的步骤130形成源极/漏极接点282于接点沟槽276中，以电性接触对应的外延的源极/漏极结构252。方法100的步骤130在沉积源极/漏极接点282的导电材料之前，可形成硅化物结构(未图示)于外延的源极/漏极结构252的露出表面上。在一些实施例中，硅化物结构的形成方法可为硅化如自对准的硅化，其形成金属材料于外延的源极/漏极结构252上，接着升温退火并造成下方的硅与金属之间的反应以形成硅化物，并蚀刻移除未反应的金属。硅化物结构有助于降低源极/漏极接点电阻。每一源极/漏极接点282可包含一或多个导电层，且其形成方法可采用任何合适方法如原子层沉积、化学气相沉积、物理气相沉积、电镀及/或其他合适工艺。在一些实施例中，每一源极/漏极接点282包括籽晶金属层与填充金属层。在多种实施例中，籽晶金属层包含钴、钨、钌、镍、其他合适金属或上述的组合。填充金属层可包含铜、钨、铝、钴、其他合适材料或上述的组合。
值得注意的是在图17B中，源极/漏极接点282的导电材料填入接点沟槽276所露出的气隙260，使源极/漏极接点282实质上包覆外延的源极/漏极结构252的一侧壁。源极/漏极接点282不包覆外延的源极/漏极结构252的其他侧壁(面对相邻的外延的源极/漏极结构252的其他侧壁)，有助于改善相邻的源极/漏极接点之间的电性击穿效能。由于接点沟槽276中露出的外延的源极/漏极结构252的大表面积(特别是外延的源极/漏极结构252的一侧壁表面)，源极/漏极接点282与外延的源极/漏极结构252仍具有够大的界面以降低源极/漏极接点电阻。
在图17B所示的实施例中，源极/漏极接点282的两个侧壁分别与外延的源极/漏极结构252相交于着陆点A，并与介电鳍状物220的上表面相交于着陆点B。着陆点A可在朝相邻的半导体鳍状物204的方向中偏离半导体鳍状物204的侧壁S204，使半导体鳍状物204完全直接位于源极/漏极接点282之下，即使源极/漏极接点282只部分地覆盖外延的源极/漏极结构252的上表面。在图17B'所示的其他实施例中，着陆点A在远离相邻的半导体鳍状物204的方向中可偏离半导体鳍状物204的侧壁S204，使半导体鳍状物204只有一部分直接位于源极/漏极接点282之下。在此方式中，可进一步增加相邻的源极/漏极接点之间的距离(比如增加约10nm)，其有助于改善电性击穿效能。在一具体例子中，着陆点A的横向位置约在外延的源极/漏极结构252的中心线中。在另一例中，着陆点A可偏离，使半导体鳍状物204无任何部分直接位于源极/漏极接点282之下，且源极/漏极接点282主要接触外延的源极/漏极结构252的侧壁。图17B'所示的另一差异为气隙260保留在外延的源极/漏极结构252的两侧侧壁上。特别是接点沟槽具有高深宽比时，源极/漏极接点282的导电材料难以填入气隙260。然而精细定义接点沟槽的宽度可避免源极/漏极接点282与外延的源极/漏极结构252的侧壁之间的界面上的空洞，有助于降低接点电阻。
如图1B所示，方法100的步骤132可进行额外工艺步骤。举例来说，可形成额外的垂直内连线结构如通孔、水平内连线结构如线路及/或多层内连线结构如金属层与层间介电层于半导体装置200上。多种内连线结构可实施多种导电材料如铜、钨、钴、铝、钛、钽、铂、钼、银、金、锰、锆、钌、上述的合金、金属硅化物、其他合适材料或上述的组合。金属硅化物可包含镍硅化物、钴硅化物、钨硅化物、钽硅化物、钛硅化物、铂硅化物、铒硅化物、钯硅化物、其他合适的金属硅化物或上述的组成。
本发明一或多个实施例可提供许多优点至半导体装置与其形成方法，但不局限于此。本发明实施例提供源极/漏极接点的形成方法，其可部分包覆外延的源极/漏极结构。本发明实施例包括在栅极置换工艺之后形成源极/漏极接点，其与外延的源极/漏极结构的上表面的一部分与一侧壁具有接触界面。综上所述，半包覆的设置可减少下方的外延的源极/漏极结构与上方的源极/漏极接点之间的接点电阻。
在本发明一例中，提供半导体装置的制作方法。方法包括形成自基板凸起的鳍状物，且鳍状物具有相对的第一侧壁与第二侧壁；形成牺牲介电层于鳍状物的上表面、第一侧壁与第二侧壁上；蚀刻牺牲介电层，以自鳍状物的第二侧壁移除牺牲介电层；形成凹陷于鳍状物中；自凹陷成长外延的源极/漏极结构，外延的源极/漏极结构具有相对的第一侧壁与第二侧壁，其中牺牲介电层覆盖外延的源极/漏极结构的第一侧壁；使牺牲介电层凹陷，以露出外延的源极/漏极结构的第一侧壁；以及形成源极/漏极接点于外延的源极/漏极结构的第一侧壁上。在一些实施例中，方法还包括形成蚀刻停止层于牺牲介电层与鳍状物的第一侧壁之间，其中使牺牲介电层凹陷的步骤包括使蚀刻停止层凹陷。在一些实施例中，蚀刻停止层物理接触外延的源极/漏极结构的第一侧壁。在一些实施例中，源极/漏极接点不物理接触外延的源极/漏极结构的第二侧壁。在一些实施例中，源极/漏极接点部分地覆盖外延的源极/漏极结构的上表面。在一些实施例中，方法还包括：形成层间介电层以覆盖牺牲介电层与外延的源极/漏极结构；以及图案化层间介电层以形成接点孔，且接点孔露出牺牲介电层。在一些实施例中，接点孔部分地露出外延的源极/漏极结构的上表面。在一些实施例中，方法还包括在蚀刻牺牲介电层之后，形成介电鳍状物于鳍状物的第二侧壁上。在一些实施例中，介电鳍状物物理接触外延的源极/漏极结构的第二侧壁。在一些实施例中，介电鳍状物不物理接触源极/漏极接点。
在本发明另一例中，提供半导体装置的制作方法。方法包括形成自基板凸起的第一半导体鳍状物与第二半导体鳍状物；形成第一介电层，以顺应性地覆盖第一半导体鳍状物、第二半导体鳍状物与基板；自第一半导体鳍状物与第二半导体鳍状物之间的区域移除第一介电层的第一部分；沉积第二介电层于第一半导体鳍状物与第二半导体鳍状物之间的区域中；成长外延的源极/漏极结构于第一半导体鳍状物与第二半导体鳍状物上，其中第一介电层覆盖每一外延的源极/漏极结构的第一侧壁，而第二介电层覆盖每一外延的源极/漏极结构的第二侧壁；自第一侧壁移除第一介电层的第二部分，以露出第一侧壁；以及形成金属接点于第一侧壁上。在一些实施例中，方法还包括在形成第一介电层之前，形成第三介电层以顺应性地覆盖第一半导体鳍状物、第二半导体鳍状物与基板，其中第一介电层覆盖第三介电层。在一些实施例中，移除第一介电层的第一部分的步骤包括自第一半导体鳍状物与第二半导体鳍状物之间的区域移除第三介电层的第一部分，且移除第一介电层的第二部分的步骤包括自第一侧壁移除第三介电层的第二部分。在一些实施例中，第一介电层与第三介电层包括不同的材料组成。在一些实施例中，方法还包括使第一介电层与第二介电层凹陷；形成盖层以覆盖第一介电层与第二介电层；以及在移除第一介电层的第二部分之前，部分地移除盖层以露出第一介电层。
在本发明又一例中，提供半导体装置。半导体装置包括半导体鳍状物，位于基板上；第一介电层与第二介电层，位于基板上，且半导体鳍状物夹设于第一介电层与第二介电层之间，其中第一介电层与第二介电层的材料组成不同；外延的源极/漏极区结构，位于半导体鳍状物上，其中外延的源极/漏极结构的延伸部分延伸于第一介电层与第二介电层上；以及源极/漏极接点，位于外延的源极/漏极结构上，其中源极/漏极接点部分地覆盖外延的源极/漏极结构的上表面，并连续延伸以包覆外延的源极/漏极结构其面对第一介电层的侧壁。在一些实施例中，第一介电层的上表面低于第二介电层的上表面。在一些实施例中，半导体装置还包括第三介电层，夹设于第一介电层与第二介电层之间，其中第一介电层与第三介电层的材料组成不同。在一些实施例中，第一介电层的上表面低于第三介电层的上表面。在一些实施例中，半导体装置还包括气隙，堆叠于外延的源极/漏极结构与第二介电层之间。
上述实施例的特征有利于本技术领域中技术人员理解本发明。本技术领域中技术人员应理解可采用本发明作基础，设计并变化其他工艺与结构以完成上述实施例的相同目的及/或相同优点。本技术领域中技术人员亦应理解，这些等效置换并未脱离本发明精神与范畴，并可在未脱离本发明的精神与范畴的前提下进行改变、替换或更动。

Claims (1)

1.一种半导体装置的制作方法，包括：
形成自一基板凸起的一鳍状物，且该鳍状物具有相对的一第一侧壁与一第二侧壁；
形成一牺牲介电层于该鳍状物的一上表面、该第一侧壁与该第二侧壁上；
蚀刻该牺牲介电层，以自该鳍状物的该第二侧壁移除该牺牲介电层；
形成一凹陷于该鳍状物中；
自该凹陷成长一外延的源极/漏极结构，该外延的源极/漏极结构具有相对的一第一侧壁与一第二侧壁，其中该牺牲介电层覆盖该外延的源极/漏极结构的该第一侧壁；
使该牺牲介电层凹陷，以露出该外延的源极/漏极结构的该第一侧壁；以及
形成一源极/漏极接点于该外延的源极/漏极结构的该第一侧壁上。
CN202110156303.2A 2020-04-01 2021-02-04 半导体装置的制作方法 Pending CN113270367A (zh)

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