TW202205524A - 半導體裝置的製作方法 - Google Patents

半導體裝置的製作方法 Download PDF

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TW202205524A
TW202205524A TW110111297A TW110111297A TW202205524A TW 202205524 A TW202205524 A TW 202205524A TW 110111297 A TW110111297 A TW 110111297A TW 110111297 A TW110111297 A TW 110111297A TW 202205524 A TW202205524 A TW 202205524A
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Taiwan
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layer
dielectric layer
source
drain
sidewall
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TW110111297A
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English (en)
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王培勳
江國誠
王志豪
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台灣積體電路製造股份有限公司
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Abstract

本發明提供半導體裝置的製作方法。方法包括形成自基板凸起的鰭狀物，且鰭狀物具有相對的第一側壁與第二側壁；形成犧牲介電層於鰭狀物的上表面、第一側壁、與第二側壁上；蝕刻犧牲介電層，以自鰭狀物的第二側壁移除犧牲介電層；形成凹陷於鰭狀物中；自凹陷成長磊晶的源極/汲極結構，磊晶的源極/汲極結構具有相對的第一側壁與第二側壁，其中犧牲介電層覆蓋磊晶的源極/汲極結構的第一側壁；使犧牲介電層凹陷，以露出磊晶的源極/汲極結構的第一側壁；以及形成源極/汲極接點於磊晶的源極/汲極結構的第一側壁上。

Description

半導體裝置的製作方法
本發明實施例一般關於半導體裝置與其製作方法，更特別關於製作場效電晶體如鰭狀場效電晶體、全繞式閘極場效電晶體、及/或其他場效電晶體的方法。
半導體積體電路產業已經歷指數成長。積體電路材料與設計的技術進展，使每一代的積體電路比前一代具有更小且更複雜的電路。在積體電路演進中，功能密度(比如單位晶片面積的內連線裝置數目)通常隨著幾何尺寸(比如製作製程所能產生的最小構件或線路)縮小而增加。尺寸縮小的製程通常有利於增加產能並降低相關成本。尺寸縮小亦會增加處理與製造積體電路的複雜度。
舉例來說，隨著裝置尺寸持續縮小，減少源極/汲極結構與源極/汲極金屬接點之間的接點電阻的挑戰更高。具體而言，在形成源極/汲極金屬接點時，相鄰的源極/汲極區之間的有限空間會減少金屬接點著陸面積並加大金屬接點電阻，此亦降低裝置積體程度。雖然解決這些挑戰的方法一般適用，但仍無法完全符合所有方面的需求。本發明實施例的主題之一為進一步改善源極/汲極金屬接點的形成方法。
在本發明一例中，提供半導體裝置的製作方法。方法包括形成自基板凸起的鰭狀物，且鰭狀物具有相對的第一側壁與第二側壁；形成犧牲介電層於鰭狀物的上表面、第一側壁、與第二側壁上；蝕刻犧牲介電層，以自鰭狀物的第二側壁移除犧牲介電層；形成凹陷於鰭狀物中；自凹陷成長磊晶的源極/汲極結構，磊晶的源極/汲極結構具有相對的第一側壁與第二側壁，其中犧牲介電層覆蓋磊晶的源極/汲極結構的第一側壁；使犧牲介電層凹陷，以露出磊晶的源極/汲極結構的第一側壁；以及形成源極/汲極接點於磊晶的源極/汲極結構的第一側壁上。
在本發明另一例中，提供半導體裝置的製作方法。方法包括形成自基板凸起的第一半導體鰭狀物與第二半導體鰭狀物；形成第一介電層，以順應性地覆蓋第一半導體鰭狀物、第二半導體鰭狀物、與基板；自第一半導體鰭狀物與第二半導體鰭狀物之間的區域移除第一介電層的第一部分；沉積第二介電層於第一半導體鰭狀物與第二半導體鰭狀物之間的區域中；成長磊晶的源極/汲極結構於第一半導體鰭狀物與第二半導體鰭狀物上，其中第一介電層覆蓋每一磊晶的源極/汲極結構的第一側壁，而第二介電層覆蓋每一磊晶的源極/汲極結構的第二側壁；自第一側壁移除第一介電層的第二部分，以露出第一側壁；以及形成金屬接點於第一側壁上。
在本發明又一例中，提供半導體裝置。半導體裝置包括半導體鰭狀物，位於基板上；第一介電層與第二介電層，位於基板上，且半導體鰭狀物夾設於第一介電層與第二介電層之間，其中第一介電層與第二介電層的材料組成不同；磊晶的源極/汲極區結構，位於半導體鰭狀物上，其中磊晶的源極/汲極結構之延伸部分延伸於第一介電層與第二介電層上；以及源極/汲極接點，位於磊晶的源極/汲極結構上，其中源極/汲極接點部分地覆蓋磊晶的源極/汲極結構的上表面，並連續延伸以包覆磊晶的源極/汲極結構其面對第一介電層的側壁。
下述詳細描述可搭配圖式說明，以利理解本發明的各方面。值得注意的是，各種結構僅用於說明目的而未按比例繪製，如本業常態。實際上為了清楚說明，可任意增加或減少各種結構的尺寸。
下述內容提供的不同實施例或例子可實施本發明實施例的不同結構。特定構件與排列的實施例係用以簡化本揭露而非侷限本發明。舉例來說，形成第一構件於第二構件上的敘述包含兩者直接接觸，或兩者之間隔有其他額外構件而非直接接觸。此外，本發明之多種實例可重複採用相同標號以求簡潔，但多種實施例及/或設置中具有相同標號的元件並不必然具有相同的對應關係。
此外，本發明實施例之結構形成於另一結構上、連接至另一結構、及/或耦接至另一結構中，結構可直接接觸另一結構，或可形成額外結構於結構及另一結構之間。此外，空間性的相對用語如「下方」、「其下」、「下側」、「上方」、「上側」、或類似用語可用於簡化說明某一元件與另一元件在圖示中的相對關係。空間性的相對用語可延伸至以其他方向使用之元件，而非侷限於圖示方向。舉例來說，若將圖式中的裝置翻轉，則下方或之下的元件將轉為上方或之上的元件。方向性用語僅用以說明圖示中的方向。此外，當數值或數值範圍的描述有「約」、「近似」、或類似用語時，除非特別說明否則其包含所述數值的+/-10%。舉例來說，用語「約5 nm」包含的尺寸範圍為4.5 nm至5.5 nm。
本發明實施例一般關於半導體裝置與其製作方法，更特別關於製作場效電晶體如鰭狀場效電晶體、全繞式閘極場效電晶體、及/或其他場效電晶體的方法。
在半導體製作中，在形成接點溝槽(亦視作接點孔)於磊晶的源極/汲極結構上之後，形成源極/汲極金屬接點(之後視作源極/汲極接點)於磊晶的源極/汲極結構之上表面上。如此一來，源極/汲極接點與磊晶的源極/汲極結構之間的接點面積受限於磊晶的源極/汲極結構的頂部，可能造成較高的接點電阻。改善源極/汲極接點的形成方法可為加大接點溝槽，以露出磊晶的源極/汲極結構之側壁。如此一來，形成於接點溝槽中的源極/汲極接點與磊晶的源極/汲極結構的側壁具有額外的接點面積(除了上表面以外)。比如源極/汲極接點包覆磊晶的源極/汲極結構之三側。然而隨著技術節點發展，減少相鄰的磊晶的源極/汲極結構之間的空間，會限制形成源極/汲極接點的製程容許範圍。舉例來說，由於導電材料填入狹窄溝槽的能力不良，在形成源極/汲極接點於接點溝槽中時，可能形成空洞於磊晶的源極/汲極結構之側壁上。此外，源極/汲極接點的包覆部分減少相鄰的源極/汲極接點之間的有效空間，在施加不同電壓至相鄰的源極/汲極接點時，可能增加電性崩潰的風險。
本發明實施例提供的源極/汲極接點沉積於磊晶的源極/汲極結構之一側壁與上表面上，但不沉積於另一側的側壁上。磊晶的源極/汲極結構之一側壁上的額外接點面積，可降低接點電阻。與此同時，磊晶的源極/汲極結構的另一側壁實質上不接觸源極/汲極接點，如同源極/汲極接點半包覆磊晶的源極/汲極結構，其可加大相鄰的源極/汲極接點之間的距離並改善裝置的崩潰效能。在一些實施例中，在形成接點溝槽之前沉積犧牲介電層。在形成接點溝槽時，可部分地移除犧牲介電層，且之後可置換為源極/汲極接點。綜上所述，犧牲介電層保留源極/汲極接點所用的區域，且形成源極/汲極接點的步驟為自對準步驟。此外，控制犧牲介電層的厚度亦可確認接點溝槽的寬度，且可最佳化犧牲介電層的厚度以利導電材料填入接點溝槽，並避免形成空洞於磊晶的源極/汲極結構之側壁上。
圖1A及1B顯示本發明一些實施例中，形成半導體裝置200 (之後可視作裝置)的方法100之流程圖。方法100僅為舉例而非侷限本發明實施例至請求項未實際記載處。在方法100之前、之中、與之後可進行額外步驟，且方法的額外實施例可置換、省略、或調換一些步驟。下述方法100將搭配其他圖式說明如下，且其他圖式顯示半導體裝置200在方法100之中間步驟時的多種三維圖與剖視圖。具體而言，圖2、3、4、5、6、7、8、9、11B、11B'、12B、13B、14B、15B、16B、17B、17B'係半導體裝置200沿著源極/汲極區中的X方向切面(即垂直於鰭狀物的長度方向)的剖視圖。圖11B、11B'、12B、13B、14B、15B、16B、17B、即17B'係半導體裝置200沿著Y方向切面(即沿著鰭狀物的長度方向)的剖視圖。圖10A係半導體裝置200的三維圖。圖10B係半導體裝置200的平面上視圖。
半導體裝置200可為製作積體電路或其部分時的中間裝置，其可包含靜態隨機存取記憶體及/或其他邏輯電路、被動構件(如電阻、電容器、或電感)、或主動構件(如p型場效電晶體、n型場效電晶體、鰭狀場效電晶體、金氧半場效電晶體、互補式金氧半電晶體、雙極電晶體、高電壓電晶體、高頻電晶體、及/或其他記憶體單元)。本發明實施例不限於任何特定數目的裝置或裝置區或任何特定的裝置設置。舉例來說，雖然圖式中的半導體裝置200為三維場效電晶體裝置(如鰭狀場效電晶體或全繞式閘極場效電晶體)，本發明實施例亦可用於製作平面場效電晶體裝置。
如圖1A及2所示，方法100的步驟102提供半導體裝置200，其包括自基板202凸起的一或多個半導體鰭狀物204。基板202可包含半導體元素(單一元素)如矽、鍺、及/或其他合適材料；半導體化合物如碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、銻化銦、及/或其他合適材料；或半導體合金如矽鍺、磷砷化鎵、砷化鋁銦、砷化鋁鎵、砷化鎵銦、磷化鎵銦、磷砷化鎵銦、及/或其他合適材料。基板202可為組成一致的單層材料。在其他實施例中，基板202可包含類似或不同組成的多個材料層，其適於製造積體電路裝置。在一例中，基板202可為絕緣層上矽基板，其具有矽層形成於氧化矽層上。在另一例中，基板202可包含導電層、半導體層、介電層、其他層、或上述之組合。
在一些實施例中，基板202包括場效電晶體或多種摻雜區如源極/汲極區位於基板202之中或之上。摻雜區可摻雜p型摻質如磷或砷，及/或n型摻質如硼或二氟化硼，端視設計需求而定。摻雜區可直接形成於基板202上、p型井結構中、n型井結構中、或雙井結構中，或採用隆起結構。摻雜區的形成方法可為佈植摻質原子、原位摻雜磊晶成長、及/或其他合適技術。
每一半導體鰭狀物204適於提供n型場效電晶體或p型場效電晶體。在一些實施例中，此處所示的半導體鰭狀物204適於提供類似型態(如n型或p型)的鰭狀場效電晶體。在其他實施例中，其適於提供相反型態(如n型與p型)的鰭狀場效電晶體。此設置僅用於說明目的而非侷限本發明實施例。半導體鰭狀物204的製作方法可採用合適製程，包括光微影與蝕刻製程。光微影製程可包含形成硬遮罩層206於基板202上，並形成光阻層於硬遮罩層206上。顯影光阻至一圖案，進行曝光後烘烤製程，與顯影光阻以形成圖案化的光阻層。接著採用圖案化的光阻層與蝕刻製程轉移圖案至硬遮罩層206。硬遮罩層206可包含介電層如氧化矽、氮化矽、氮氧化矽、及/或碳化矽。在例示性的實施例中，硬遮罩層206可包含氮化矽。接著經由硬遮罩層206的圖案中的開口蝕刻基板202，以保留半導體鰭狀物204於基板202上。蝕刻製程可包含乾蝕刻、濕蝕刻、反應性離子蝕刻、及/或其他合適製程。
形成半導體鰭狀物204所用的多種方法的實施例亦適用。舉例來說，可採用雙重圖案化或多重圖案化製程圖案化半導體鰭狀物204。一般而言，雙重圖案化或多重圖案化製程結合光微影與自對準製程，其產生的圖案間距可小於採用單一的直接光微影製程所得的圖案間距。舉例來說，一實施例形成犧牲層於基板上，並採用光微影製程圖案化犧牲層。採用自對準製程，以沿著圖案化的犧牲層側部形成間隔物。接著移除犧牲層，而保留的間隔物或芯可用於圖案化鰭狀物。在一些實施例中，在形成半導體鰭狀物204之後，半導體鰭狀物204沿著Z方向的高度H1 介於約40 nm至約70 nm之間，而半導體鰭狀物204的上側部分沿著X方向的寬度W1 介於約10 nm至約40 nm之間。
如圖1A及3所示，方法100的步驟104形成一系列的介電層於半導體裝置200上。在一些實施例中，可順應性地形成含一或多層的絕緣材料之絕緣材料層210，且形成方法可採用化學氣相沉積、原子層沉積、或其他合適方法。以順應性的方式沉積絕緣材料層210，使其在半導體鰭狀物204的上表面與垂直表面(如側壁)以及基板202的水平表面上具有實質上相同的厚度。在一些實施例中，絕緣材料層210的沉積厚度為約10 nm至約40 nm。絕緣材料層210所用的絕緣材料可包含氧化矽、氮化矽、氮氧化矽、碳氮氧化矽、碳氮化矽、摻雜氟的矽酸鹽玻璃、或低介電常數的介電材料。
在一些實施例中，在形成絕緣材料層210之前可視情況形成襯墊層208於半導體裝置200上。襯墊層208的組成可為氧化矽或氮化矽為主的材料(如氮化矽、碳氮化矽、或碳氮氧化矽)。可先順應性地沉積襯墊層208於半導體鰭狀物204與基板202上，且沉積方法可為化學氣相沉積、原子層沉積、或其他合適方法。接著沉積絕緣材料層210所用的絕緣材料於襯墊層208上。
方法100的步驟104在形成絕緣材料層210之後，亦形成蝕刻停止層212。蝕刻停止層212包括的介電材料與絕緣材料層210不同。在一些實施例中，蝕刻停止層212的組成為高介電常數(比如大於氧化矽的介電常數(約3.9))的介電材料，比如金屬氧化物如氧化鉿、氧化鋯、氧化鋁、或上述之組合。順應性形成蝕刻停止層212的方法可採用化學氣相沉積、原子層沉積、或其他合適方法。在一些實施例中，蝕刻停止層212的沉積厚度為約2 nm至約5 nm。
方法100的步驟104在形成蝕刻停止層之後，更形成犧牲介電層214。犧牲介電層214包含的介電材料與蝕刻停止層212不同。在一些實施例中，犧牲介電層214的組成為碳氧化矽、碳氮氧化矽、或上述之組合。順應性形成犧牲介電層214的方法可採用化學氣相沉積、原子層沉積、或其他合適方法。犧牲介電層214可保留形成接點溝槽所用的空間，且接點溝槽露出成長於半導體鰭狀物204上的磊晶的源極/汲極結構之側壁，如下所述。在多種實施例中，犧牲介電層214沿著X方向的寬度W2 為半導體鰭狀物204的寬度W1 之約15%至約100%，比如約25%。在多種實施例中，當寬度W2 大於約15%的寬度W1 ，就算導電材料在高深寬比溝槽中的填隙能力有限，填入接點溝槽的導電材料實質上無空洞。另一方面，當寬度W2 小於約15%的寬度W1 ，則可能形成空洞於溝槽中，其將增加源極/汲極接點與磊晶的源極/汲極結構之間的接點電阻。若寬度W2 大於約100%的寬度W1 ，則需增加半導體鰭狀物204之間的空間以容納較大寬度的犧牲介電層214，其會影響晶片尺寸並增加製造成本。在具體例子中，犧牲介電層214的寬度W2 為約5 nm至約10 nm。
如圖1A、4、及5所示，方法100的步驟106部分地移除半導體鰭狀物204之間的犧牲介電層214與蝕刻停止層212，以形成溝槽218。步驟106可包含多種製程，比如光微影與蝕刻。光微影製程可包含形成光阻層216於半導體裝置200上。例示性的光阻包括對射線如紫外光、深紫外射線、及/或極紫外射線敏感的光敏材料。在半導體裝置200上進行微影曝光，使光阻層216的選定區域曝光至射線。曝光造成光阻層216的曝光區中的化學反應。在曝光之後，對光阻層216施加顯影劑。顯影劑可溶解或移除正型光阻顯影製程中的曝光區，或負型光阻顯影製程中的非曝光區。合適的正型顯影劑包括氫氧化四甲基銨、氫氧化鉀、或氫氧化鈉，而合適的負型顯影劑包括溶劑如乙酸正丁酯、乙醇、己烷、苯、或甲苯。在顯影光阻層216之後，可由蝕刻製程如濕蝕刻、乾蝕刻、反應性離子蝕刻、灰化、及/或其他蝕刻方法移除犧牲介電層214與蝕刻停止層212的露出部分。在一些實施例中，蝕刻製程包括不同蝕刻化學劑的多重蝕刻步驟，一蝕刻步驟的目標為犧牲介電層214的具體材料而不蝕刻蝕刻停止層212 (如圖4所示)，而另一蝕刻步驟的目標為蝕刻停止層212的具體材料而不蝕刻絕緣材料層210 (如圖5所示)。在形成溝槽218之後，以濕式剝除或電漿灰化移除圖案化的光阻層216。其他實施例在蝕刻犧牲介電層214之後與蝕刻蝕刻停止層212之前，可移除圖案化的光阻層216。蝕刻停止層212的蝕刻方法可採用圖案化的犧牲介電層214作為蝕刻遮罩。
如圖1A、6、及7所示，方法100的步驟108形成介電鰭狀物220 (在一些例子中可視作虛置鰭狀物或混合鰭狀物)於溝槽218中。每一介電鰭狀物220可位於半導體鰭狀物204之間，其方向可實質上平行於半導體鰭狀物204。然而與設置以提供主動裝置的半導體鰭狀物204不同，介電鰭狀物220非主動且非設置以形成場效電晶體。在一些實施例中，提供介電鰭狀物220以調整鰭狀物至鰭狀物的空間(如鰭狀物間距)。介電鰭狀物220亦有助於減少鰭狀物圖案化負載效應，並避免源極/汲極磊晶結構橋接。介電鰭狀物220的形成方法可為任何合適方法。在圖6所示的一例中，可先沉積介電鰭狀物220的介電材料以填入溝槽218並覆蓋半導體裝置200。介電鰭狀物220可包含任何合適的介電材料如碳氮化矽、碳氮氧化矽、或金屬氧化物(如氧化鉿、氧化鋯、或氧化鋁)、及/或其他合適的介電材料，且其沉積方法可為任何合適的沉積製程如化學氣相沉積、物理氣相沉積、原子層沉積、及/或其他合適製程。在一實施例中，介電鰭狀物220包括化學氣相沉積所沉積的氧化鋁。在多種實施例中，介電鰭狀物220的材料組成與犧牲介電層214或蝕刻停止層212的材料組成不同。在沉積之後，可進行化學機械研磨製程以移除多餘的介電材料。在一些實施例中，硬遮罩層206可作為化學機械研磨停止層。之後可使介電鰭狀物220的介電材料凹陷(比如以化學蝕刻製程)，使其上表面低於半導體鰭狀物204的上表面。步驟108亦可使蝕刻停止層212與犧牲介電層214凹陷，如圖7所示。在所述實施例中，步驟108之後的蝕刻停止層212與犧牲介電層214只保留於半導體鰭狀物204的一側壁(背對相鄰的半導體鰭狀物204)上。此外，由於蝕刻停止層212與犧牲介電層214的厚度，多種介電鰭狀物220的下表面不齊平，使直接形成於絕緣材料層210上的介電鰭狀物220之下表面，低於形成於犧牲介電層214上的其他介電鰭狀物220之下表面。
如圖1A及8所示，方法100的步驟110形成蓋層222以覆蓋介電鰭狀物220、蝕刻停止層212、與犧牲介電層214。蓋層222與犧牲介電層214的介電材料不同。在一些實施例中，蓋層222與蝕刻停止層212的介電材料不同。在一些其他實施例中，蓋層222與蝕刻停止層212的介電材料相同。在具體例子中，蓋層222的組成為高介電常數的介電材料如金屬氧化物(如氧化鉿、氧化鋯、氧化鋁、或上述之組合)。蓋層222的沉積方法可為任何合適的沉積製程如化學氣相沉積、物理氣相沉積、原子層沉積、及/或其他合適製程。在沉積之後可進行化學機械研磨製程以移除多餘的介電材料。在所述實施例中，化學機械研磨製程亦可移除硬遮罩層206並露出半導體鰭狀物204的上表面。蓋層222的厚度可為約5 nm至約20 nm。
如圖1A及9所示，方法100的步驟112使絕緣材料層210凹陷，以露出半導體鰭狀物204的上側部分。在一些實施例中，絕緣材料層210的凹陷範圍為約40 nm至約80 nm。步驟112亦使襯墊層208凹陷。此步驟形成的凹陷的絕緣材料層210可使半導體鰭狀物204彼此之間電性隔離，因此可視作淺溝槽隔離區。在許多實施例中，方法100形成淺溝槽隔離區如凹陷的絕緣材料層210的方法可為合適的蝕刻製程如乾蝕刻製程、濕蝕刻製程、或反應性離子蝕刻製程。
如圖1A、10A、10B、及11A至11B'所示，方法100的步驟114形成多個虛置閘極堆疊230以接合半導體鰭狀物204。具體而言，圖10A顯示半導體裝置200在步驟114的三維圖。圖10B顯示半導體裝置200的平面上視圖。圖11A顯示半導體裝置200沿著圖10A及10B所示的剖面A-A' (如半導體鰭狀物204上的Y切面)的剖視圖。圖11A'顯示圖11A中的剖視圖的其他實施例。圖11B顯示半導體裝置200沿著圖10A及10B所示的剖面B-B' (源極/汲極區中的X切面)的剖視圖。圖11B'顯示圖11B中的剖視圖的其他實施例。
每一虛置閘極堆疊230作為後續形成的高介電常數的閘極介電層與金屬閘極結構的占位物。虛置閘極堆疊230可包含虛置閘極232與多種其他材料層。在一些實施例中，虛置閘極232包括多晶矽。在圖11A所示的實施例中，虛置閘極堆疊可包含界面層234位於半導體鰭狀物204與虛置閘極232之間、硬遮罩層236位於虛置閘極232上、及/或硬遮罩層238位於硬遮罩層236上。虛置閘極堆疊230的形成方法可為先毯覆性沉積虛置閘極堆疊的多種材料層。虛置閘極堆疊230的多種材料層之形成方法可為任何合適製程，比如化學氣相沉積、物理氣相沉積、原子層沉積、化學氧化、其他合適製程、或上述之組合。之後可在虛置閘極堆疊230的多種材料層上進行圖案化步驟，以形成虛置閘極堆疊於半導體鰭狀物204上。如下詳述，在製作半導體裝置200的其他構件(如磊晶的源極/汲極結構)之後，可進行閘極置換製程以將虛置閘極堆疊230的部分置換為高介電常數的閘極介電層與金屬閘極。硬遮罩層236及238可各自包含任何合適的介電材料，比如半導體氧化物及/或半導體氮化物。在一例中，硬遮罩層236包含碳氮化矽，且硬遮罩層238包含氧化矽。界面層224可包含任何合適材料如氧化矽。
如圖11A及11B所示，方法100的步驟114亦形成介電層240於半導體裝置200上。在許多實施例中，介電層240可順應性地形成於半導體裝置200上，包括形成於半導體鰭狀物204、介電鰭狀物220上的蓋層222、與虛置閘極堆疊230上。介電層240可包含任何合適的介電材料如含氮的介電材料，且其形成方法可為任何合適方法如原子層沉積、化學氣相沉積、物理氣相沉積、其他合適方法、或上述之組合。在所述實施例中，介電層240的形成方法可為熱原子層沉積製程。在一些例子中，介電層240可包含氮化矽、碳氮化矽、碳氮氧化矽、其他合適的介電材料、或上述之組合。
方法100的步驟114亦形成閘極間隔物層242於介電層240上。與介電層240類似，閘極間隔物層242可順應性地形成於虛置閘極堆疊230上。閘極間隔物層242可包含任何合適的介電材料如含氧介電材料或高介電常數的介電材料，且其形成方法可為任何合適方法如原子層沉積、化學氣相沉積、物理氣相沉積、其他合適方法、或上述之組合。在一些實施例中，閘極間隔物242包括兩個或更多材料層，比如第一閘極間隔物層242a與沉積於第一閘極間隔物層242a上的第二閘極間隔物層242b。在具體例子中，第一閘極間隔物層242a包括碳氮氧化矽、碳氧化矽、氮化矽、或上述之組合，且其厚度為約2 nm至約4 nm。第二閘極間隔物層242b與第一閘極間隔物層242a的材料不同，且可為碳氮化矽、氮化矽、或上述之組合，且其厚度可為約2 nm至約4 nm。
圖11A'係一些其他實施例中，步驟114中的半導體裝置200。圖11A'中的半導體裝置200在許多方面與圖11A類似。差別之一為圖11A'中的半導體鰭狀物204可包含交錯的不同半導體材料如半導體材料204a與半導體材料204b。在一些實施例中，半導體鰭狀物204可包含總共三至十層的交錯半導體材料層，而本發明實施例當然不限於此設置。在本發明實施例中，半導體材料204a包括矽，而半導體材料204b包括矽鍺。半導體材料204a及204b之一者(或兩者)可摻雜合適摻質如p型摻質或n型摻質，以形成所需的場效電晶體。半導體材料204a及204b的形成方法可各自為磊晶製程如分子束磊晶製程、化學氣相沉積製程(如有機金屬化學氣相沉積製程)、及/或其他合適的磊晶成長製程。
如圖11A'所示，許多實施例中交錯的半導體材料204a及204b的層狀物設置以提供多閘極裝置如全繞式閘極場效電晶體，如下詳述。多閘極裝置可增加閘極-通道耦接、減少關閉狀態電流、與減少短通道效應，以改善閘極控制。多閘極裝置如全繞式閘極場效電晶體通常包含閘極結構，其延伸於水平通道區周圍，以自所有側接觸通道區。全繞式閘極場效電晶體通常與互補式金氧半製程相容，以大幅縮小尺寸並維持閘極控制與緩解短通道效應。本發明實施例當然不限於只形成全繞式閘極場效電晶體，且可提供許多其他三維場效電晶體如鰭狀場效電晶體。如此一來，半導體鰭狀物204可包含半導體材料的單層，或不同半導體材料的多層(非交錯堆疊，可提供不一致的鰭狀物以形成鰭狀場效電晶體)，如圖11A所示的相關說明。
圖11B'所示的另一實施例係步驟114中的半導體裝置200。圖11B'中的半導體裝置200的許多部分與圖11B實質上類似，差異在於圖11B'中的兩個半導體鰭狀物204可包含不同的半導體材料。舉例來說，一半導體鰭狀物204可包含矽以用於形成n型場效電晶體，而其他半導體鰭狀物204可包含矽鍺以用於形成p型場效電晶體。含矽鍺的半導體鰭狀物之形成方法可包含使矽鰭狀物凹陷，並以磊晶製程沉積矽鍺，且磊晶製程可為分子束磊晶製程、化學氣相沉積製程(如有機金屬化學氣相沉積製程)、及/或其他合適的磊晶成長製程。
如圖1A、12、及12B所示，方法100的步驟116移除半導體鰭狀物204的一部分以形成凹陷250於其中。在許多實施例中，方法100以合適的蝕刻製程形成凹陷250，比如乾蝕刻製程、濕蝕刻製程、或反應性離子蝕刻製程。在一些實施例中，方法100選擇性移除半導體鰭狀物204而不蝕刻或實質上不蝕刻蝕刻停止層212與介電鰭狀物220的部分。如此處所述，步驟116可移除界面層234、介電層240、及閘極間隔物層242的上側部分以及形成於介電鰭狀物220上的蓋層222的上側部分，以形成凹陷250。步驟116的蝕刻製程可實施乾蝕刻製程，其可採用蝕刻劑如含溴氣體(如溴化氫及/或溴仿)、含氟氣體(如四氟化碳、六氟化硫、二氟甲烷、氟仿、及/或六氟乙烷)、其他合適氣體、或上述之組合。調整蝕刻製程時間，可控制半導體鰭狀物204的移除量。在一些實施例中，步驟116的蝕刻製程露出的介電鰭狀物220之上側部分的高度H2 小於或等於約40 nm。在一些實施例中，蓋層222的保留厚度為約3 nm至約10 nm。
如圖1B、13A、及13B所示，方法100的步驟118自凹陷250開始成長磊晶的源極/汲極結構252。磊晶的源極/汲極結構252可包含多個磊晶半導體層，比如層狀物254、256、及258。在一些實施例中，層狀物254、256、及258中包含的摻質量不同。在一些例子中，由於摻雜製程的特性，層狀物254中包含的摻質量小於層狀物258中包含的摻質量。在一些例子中，層狀物258中包含的摻質量亦小於層狀物256中包含的摻質量，以最小化漏電流的可能性。在一些例子中，層狀物256中包含的摻質量約大於或等於層狀物254中包含的摻質量。如圖13B所示，磊晶的源極/汲極結構252一開始成長於凹陷250中，接著延伸高於介電鰭狀物220。換言之，磊晶的源極/汲極結構252的橫向成長不受凹陷的寬度限制，可更彈性地設計磊晶的源極/汲極結構尺寸。在所述實施例中，步驟118之後可保留氣隙260於磊晶的源極/汲極結構252之底部兩側上(比如磊晶的源極/汲極結構252以其與其相鄰的介電鰭狀物220之間)。
磊晶的源極/汲極結構252 (如包含其中的層狀物254、256、及258)之形成方法可為任何合適方法，比如分子束磊晶、有機金屬化學氣相沉積、其他合適的磊晶成長製程、或上述之組合。磊晶的源極/汲極結構252可為p型磊晶材料以適用於p型鰭狀場效電晶體裝置，或n型磊晶材料以適用於n型鰭狀場效電晶體裝置。p型磊晶材料可包含矽鍺(磊晶矽鍺)的一或多個磊晶層，而矽鍺可摻雜p型摻質如硼、鍺、銦、及/或其他p型摻質。n型磊晶材料可包含矽(磊晶矽)或碳化矽(磊晶碳化矽)的一或多個磊晶層，而矽或碳化矽可摻雜n型摻質如砷、磷、及/或其他n型摻質。在所述實施例中，以p型磊晶的源極/汲極結構252與相鄰的n型磊晶的源極/汲極結構252做說明。
如圖1B、14A、及14B所示，方法100的步驟120形成層間介電層264於接點蝕刻停止層262上。接點蝕刻停止層262可包含氮化矽、氮氧化矽、碳氮氧化矽、其他合適材料、或上述之組合，且其形成方法可為化學氣相沉積、物理氣相沉積、原子層沉積、其他合適方法、或上述之組合。在一些實施例中，接點蝕刻停止層262可具有順應性的輪廓於虛置閘極堆疊230與磊晶的源極/汲極結構252上。層間介電層264包括介電材料如四乙氧基矽烷的氧化物、未摻雜的矽酸鹽玻璃、或摻雜氧化矽(如硼磷矽酸鹽玻璃、氟矽酸鹽玻璃、磷矽酸鹽玻璃、或硼矽酸鹽玻璃)、其他合適的介電材料、或上述之組合。層間介電層264可包含多種介電材料的多層結構，且其形成方法可為沉積製程如化學氣相沉積、可流動的化學氣相沉積、旋轉塗佈玻璃、其他合適方法、或上述之組合。在一些實施例中，形成層間介電層264的方法更包括進行化學機械研磨製程，以平坦化半導體裝置200的上表面，使虛置閘極堆疊230的上表面露出。
如圖1B、14A、及14B所示，方法100的步驟122進行閘極置換製程以將虛置閘極堆疊230置換成個別的金屬閘極結構270。在一些實施例中，每一金屬閘極結構270為高介電常數的閘極介電層與金屬閘極結構，其中高介電常數的閘極介電層之介電常數大於氧化矽的介電常數(約3.9)。步驟122的閘極置換製程所實施的一系列製作步驟如下詳述。
方法100的步驟122以任何合適方法移除虛置閘極堆疊230，以形成閘極溝槽(未圖示)於半導體鰭狀物204上。形成閘極溝槽的方法可包含一或多道蝕刻製程，其對虛置閘極堆疊230中包含的材料(如虛置閘極中包含的多晶矽)具有選擇性。蝕刻製程可包含乾蝕刻、濕蝕刻、反應性離子蝕刻、其他合適的蝕刻方法、或上述之組合。對需要多閘極裝置如全繞式閘極場效電晶體的實施例而言，以圖11A'為例，蝕刻製程可自半導體鰭狀物204選擇性地移除半導體材料204b (含矽鍺)，使空洞或間隙(未圖示)形成於半導體材料204a (包含矽)的堆疊之間。在一些實施例中，蝕刻製程可為選擇性乾蝕刻製程或濕蝕刻製程。
方法100接著形成金屬閘極結構270於閘極溝槽中。對半導體鰭狀物204包括半導體材料204a及204b的交錯堆疊之實施例而言，自半導體裝置200移除半導體材料204b後，可沉積金屬閘極結構270的多種材料層於半導體材料204a的層狀物之間的間隙中。雖然未圖示，金屬閘極結構270可包含多個材料層如高介電常數的閘極介電層形成於界面層上、功函數金屬層形成於高介電常數的閘極介電層上、基體導電層形成於功函數金屬層上、其他合適層、或上述之組合。高介電常數的介電層可包含一或多種高介電常數的介電材料(或一或多層的高介電常數的介電材料)，比如氧化鉿矽、氧化鉿、氧化鋁、氧化鋯、氧化鑭、氧化鈦、氧化釔、鈦酸鍶、或上述之組合。功函數金屬層可包含任何合適材料如氮化鈦、氮化鉭、釕、鉬、鎢、鉑、鈦、鋁、碳化鉭、碳氮化鉭、氮化鉭矽、氮化鈦矽、其他合適材料、或上述之組合。在一些實施例中，功函數金屬層包括多種相同型態或不同型態的多個材料層(比如均為n型功函數金屬或均為p型功函數金屬)，以達所需的臨界電壓。基體導電層可包含鋁、銅、鎢、鈷、釕、其他合適的導電材料、或上述之組合。金屬閘極結構270可包含其他材料層，比如阻障層、黏著層、及/或蓋層。金屬閘極結構270的多種層狀物之形成方法可為任何合適方法，比如化學氣相沉積、原子層沉積、物理氣相沉積、電鍍、化學氧化、熱氧化、其他合適方法、或上述之組合。方法100之後可進行一或多道研磨製程(如化學機械研磨)，以移除多餘的導電材料，並平坦化半導體裝置200的上表面。
如圖1B與15A至15C所示，方法100的步驟124進行圖案化製程，以形成接點溝槽276 (亦視作接點孔)於層間介電層264中。接點溝槽276偏離磊晶的源極/汲極結構252之中心，使接點溝槽276中露出磊晶的源極/汲極結構252的部分上表面。在所述實施例中，接點蝕刻停止層262與層間介電層264可維持覆蓋磊晶的源極/汲極結構252之上表面較靠近相鄰的源極/汲極結構252的一部分。形成接點溝槽276的方法包括以微影製程形成圖案化的光阻層，其具有開口以定義接點溝槽276所用的區域；經由圖案化的光阻層之開口蝕刻層間介電層264與接點蝕刻停止層262；以及以濕式剝除或電漿灰化移除圖案化的光阻層。可另外採用硬遮罩以圖案化接點溝槽276。接點溝槽276中亦露出蓋層222與蝕刻停止層212。
如圖1B、15A、及15B所示，方法100的步驟126進行一或多道選擇性蝕刻製程，以移除接點溝槽276中露出的蓋層222的一部分，並經由蓋層222中的開口使之前形成的犧牲介電層214凹陷。在一些例子中，蝕刻製程可為一或多道等向蝕刻製程(如等向乾蝕刻或等向濕蝕刻製程)，其實施的蝕刻劑可包含氫氟酸、氨、三氟化氮、其他合適蝕刻劑、或上述之組合。調整蝕刻製程的時間，可控制犧牲介電層214的凹陷量。在一些實施例中，步驟126的蝕刻製程使犧牲介電層214凹陷的深度可為約10 nm至約60 nm。蝕刻製程使犧牲介電層214凹陷，而不蝕刻或實質上不蝕刻蝕刻停止層212。蝕刻停止層212在蝕刻製程時，可保護磊晶的源極/汲極結構252的側避免於額外蝕刻。
如圖1B、16A、及16B所示，方法100的步驟128進行選擇性蝕刻以使蝕刻停止層212凹陷，進而露出磊晶的源極/汲極結構252之一側壁表面。蝕刻製程可包含任何合適的蝕刻技術如濕蝕刻、乾蝕刻、反應性離子蝕刻、灰化、及/或其他蝕刻方法。選擇蝕刻劑以蝕刻蝕刻停止層212而不蝕刻或實質上不蝕刻犧牲介電層214與磊晶的源極/汲極結構252。可調整蝕刻製程的時間以控制蝕刻停止層212的凹陷量。因此一些實施例的蝕刻停止層212的上表面與犧牲介電層214的上表面可實質上齊平，端視蝕刻製程的時間而定。在一些其他實施例中，蝕刻停止層212的上表面可高於犧牲介電層214的上表面。在一些其他實施例中，蝕刻停止層212的上表面可低於犧牲介電層214的上表面。犧牲介電層214與蝕刻停止層212可一起設置為保留良好定義的接點溝槽寬度(由犧牲介電層214與蝕刻停止層212的總厚度所定義)。接點溝槽276的位置可由自對準確認。值得注意的是，接點溝槽276中亦露出磊晶的源極/汲極結構252之露出的側壁表面上的氣隙260。與此相較，另一側壁上的氣隙260仍保留於磊晶的源極/汲極結構252與介電鰭狀物220之間。
如圖1B與17A至17B'所示，方法100的步驟130形成源極/汲極接點282於接點溝槽276中，以電性接觸對應的磊晶的源極/汲極結構252。方法100的步驟130在沉積源極/汲極接點282的導電材料之前，可形成矽化物結構(未圖示)於磊晶的源極/汲極結構252之露出表面上。在一些實施例中，矽化物結構的形成方法可為矽化如自對準的矽化，其形成金屬材料於磊晶的源極/汲極結構252上，接著升溫退火並造成下方的矽與金屬之間的反應以形成矽化物，並蝕刻移除未反應的金屬。矽化物結構有助於降低源極/汲極接點電阻。每一源極/汲極接點282可包含一或多個導電層，且其形成方法可採用任何合適方法如原子層沉積、化學氣相沉積、物理氣相沉積、電鍍、及/或其他合適製程。在一些實施例中，每一源極/汲極接點282包括晶種金屬層與填充金屬層。在多種實施例中，晶種金屬層包含鈷、鎢、釕、鎳、其他合適金屬、或上述之組合。填充金屬層可包含銅、鎢、鋁、鈷、其他合適材料、或上述之組合。
值得注意的是在圖17B中，源極/汲極接點282的導電材料填入接點溝槽276所露出的氣隙260，使源極/汲極接點282實質上包覆磊晶的源極/汲極結構252之一側壁。源極/汲極接點282不包覆磊晶的源極/汲極結構252之其他側壁(面對相鄰的磊晶的源極/汲極結構252之其他側壁)，有助於改善相鄰的源極/汲極接點之間的電性崩潰效能。由於接點溝槽276中露出的磊晶的源極/汲極結構252之大表面積(特別是磊晶的源極/汲極結構252的一側壁表面)，源極/汲極接點282與磊晶的源極/汲極結構252仍具有夠大的界面以降低源極/汲極接點電阻。
在圖17B所示的實施例中，源極/汲極接點282的兩個側壁分別與磊晶的源極/汲極結構252相交於著陸點A，並與介電鰭狀物220的上表面相交於著陸點B。著陸點A可在朝相鄰的半導體鰭狀物204之方向中偏離半導體鰭狀物204的側壁S204 ，使半導體鰭狀物204完全直接位於源極/汲極接點282之下，即使源極/汲極接點282只部分地覆蓋磊晶的源極/汲極結構252的上表面。在圖17B'所示的其他實施例中，著陸點A在遠離相鄰的半導體鰭狀物204之方向中可偏離半導體鰭狀物204的側壁S204 ，使半導體鰭狀物204只有一部分直接位於源極/汲極接點282之下。在此方式中，可進一步增加相鄰的源極/汲極接點之間的距離(比如增加約10 nm)，其有助於改善電性崩潰效能。在一具體例子中，著陸點A的橫向位置約在磊晶的源極/汲極結構252之中心線中。在另一例中，著陸點A可偏離，使半導體鰭狀物204無任何部分直接位於源極/汲極接點282之下，且源極/汲極接點282主要接觸磊晶的源極/汲極結構252之側壁。圖17B'所示的另一差異為氣隙260保留在磊晶的源極/汲極結構252之兩側側壁上。特別是接點溝槽具有高深寬比時，源極/汲極接點282的導電材料難以填入氣隙260。然而精細定義接點溝槽的寬度可避免源極/汲極接點282與磊晶的源極/汲極結構252的側壁之間的界面上的空洞，有助於降低接點電阻。
如圖1B所示，方法100的步驟132可進行額外製程步驟。舉例來說，可形成額外的垂直內連線結構如通孔、水平內連線結構如線路、及/或多層內連線結構如金屬層與層間介電層於半導體裝置200上。多種內連線結構可實施多種導電材料如銅、鎢、鈷、鋁、鈦、鉭、鉑、鉬、銀、金、錳、鋯、釕、上述之合金、金屬矽化物、其他合適材料、或上述之組合。金屬矽化物可包含鎳矽化物、鈷矽化物、鎢矽化物、鉭矽化物、鈦矽化物、鉑矽化物、鉺矽化物、鈀矽化物、其他合適的金屬矽化物、或上述之組成。
本發明一或多個實施例可提供許多優點至半導體裝置與其形成方法，但不侷限於此。本發明實施例提供源極/汲極接點的形成方法，其可部分包覆磊晶的源極/汲極結構。本發明實施例包括在閘極置換製程之後形成源極/汲極接點，其與磊晶的源極/汲極結構之上表面的一部分與一側壁具有接觸界面。綜上所述，半包覆的設置可減少下方的磊晶的源極/汲極結構與上方的源極/汲極接點之間的接點電阻。
在本發明一例中，提供半導體裝置的製作方法。方法包括形成自基板凸起的鰭狀物，且鰭狀物具有相對的第一側壁與第二側壁；形成犧牲介電層於鰭狀物的上表面、第一側壁、與第二側壁上；蝕刻犧牲介電層，以自鰭狀物的第二側壁移除犧牲介電層；形成凹陷於鰭狀物中；自凹陷成長磊晶的源極/汲極結構，磊晶的源極/汲極結構具有相對的第一側壁與第二側壁，其中犧牲介電層覆蓋磊晶的源極/汲極結構的第一側壁；使犧牲介電層凹陷，以露出磊晶的源極/汲極結構的第一側壁；以及形成源極/汲極接點於磊晶的源極/汲極結構的第一側壁上。在一些實施例中，方法更包括形成蝕刻停止層於犧牲介電層與鰭狀物的第一側壁之間，其中使犧牲介電層凹陷的步驟包括使蝕刻停止層凹陷。在一些實施例中，蝕刻停止層物理接觸磊晶的源極/汲極結構之第一側壁。在一些實施例中，源極/汲極接點不物理接觸磊晶的源極/汲極結構的第二側壁。在一些實施例中，源極/汲極接點部分地覆蓋磊晶的源極/汲極結構的上表面。在一些實施例中，方法更包括：形成層間介電層以覆蓋犧牲介電層與磊晶的源極/汲極結構；以及圖案化層間介電層以形成接點孔，且接點孔露出犧牲介電層。在一些實施例中，接點孔部分地露出磊晶的源極/汲極結構的上表面。在一些實施例中，方法更包括在蝕刻犧牲介電層之後，形成介電鰭狀物於鰭狀物的第二側壁上。在一些實施例中，介電鰭狀物物理接觸磊晶的源極/汲極結構的第二側壁。在一些實施例中，介電鰭狀物不物理接觸源極/汲極接點。
在本發明另一例中，提供半導體裝置的製作方法。方法包括形成自基板凸起的第一半導體鰭狀物與第二半導體鰭狀物；形成第一介電層，以順應性地覆蓋第一半導體鰭狀物、第二半導體鰭狀物、與基板；自第一半導體鰭狀物與第二半導體鰭狀物之間的區域移除第一介電層的第一部分；沉積第二介電層於第一半導體鰭狀物與第二半導體鰭狀物之間的區域中；成長磊晶的源極/汲極結構於第一半導體鰭狀物與第二半導體鰭狀物上，其中第一介電層覆蓋每一磊晶的源極/汲極結構的第一側壁，而第二介電層覆蓋每一磊晶的源極/汲極結構的第二側壁；自第一側壁移除第一介電層的第二部分，以露出第一側壁；以及形成金屬接點於第一側壁上。在一些實施例中，方法更包括在形成第一介電層之前，形成第三介電層以順應性地覆蓋第一半導體鰭狀物、第二半導體鰭狀物、與基板，其中第一介電層覆蓋第三介電層。在一些實施例中，移除第一介電層的第一部分之步驟包括自第一半導體鰭狀物與第二半導體鰭狀物之間的區域移除第三介電層的第一部分，且移除第一介電層的第二部分之步驟包括自第一側壁移除第三介電層的第二部分。在一些實施例中，第一介電層與第三介電層包括不同的材料組成。在一些實施例中，方法更包括使第一介電層與第二介電層凹陷；形成蓋層以覆蓋第一介電層與第二介電層；以及在移除第一介電層的第二部分之前，部分地移除蓋層以露出第一介電層。
在本發明又一例中，提供半導體裝置。半導體裝置包括半導體鰭狀物，位於基板上；第一介電層與第二介電層，位於基板上，且半導體鰭狀物夾設於第一介電層與第二介電層之間，其中第一介電層與第二介電層的材料組成不同；磊晶的源極/汲極區結構，位於半導體鰭狀物上，其中磊晶的源極/汲極結構之延伸部分延伸於第一介電層與第二介電層上；以及源極/汲極接點，位於磊晶的源極/汲極結構上，其中源極/汲極接點部分地覆蓋磊晶的源極/汲極結構的上表面，並連續延伸以包覆磊晶的源極/汲極結構其面對第一介電層的側壁。在一些實施例中，第一介電層的上表面低於第二介電層的上表面。在一些實施例中，半導體裝置更包括第三介電層，夾設於第一介電層與第二介電層之間，其中第一介電層與第三介電層的材料組成不同。在一些實施例中，第一介電層的上表面低於第三介電層的上表面。在一些實施例中，半導體裝置更包括氣隙，堆疊於磊晶的源極/汲極結構與第二介電層之間。
上述實施例之特徵有利於本技術領域中具有通常知識者理解本發明。本技術領域中具有通常知識者應理解可採用本發明作基礎，設計並變化其他製程與結構以完成上述實施例之相同目的及/或相同優點。本技術領域中具有通常知識者亦應理解，這些等效置換並未脫離本發明精神與範疇，並可在未脫離本發明之精神與範疇的前提下進行改變、替換、或更動。
A,B:著陸點 A-A’,B-B’:剖面 H1 ,H2 :高度 W1 ,W2 :寬度 S204 :側壁 100:方法 102,104,106,108,110,112,114,116,118,120,122,124,126,128,130,132:步驟 200:半導體裝置 202:基板 204:半導體鰭狀物 204a,204b:半導體材料 206,236,238:硬遮罩層 208:襯墊層 210:絕緣材料層 212:蝕刻停止層 214:犧牲介電層 216:光阻層 218:溝槽 220:介電鰭狀物 222:蓋層 224,234:界面層 230:虛置閘極堆疊 232:虛置閘極 240:介電層 242:閘極間隔物層 242a:第一閘極間隔物層 242b:第二閘極間隔物層 250:凹陷 252:源極/汲極結構 254,256,258:層狀物 260:氣隙 262:接點蝕刻停止層 264:層間介電層 270:金屬閘極結構 276:接點溝槽 282:源極/汲極接點
圖1A及1B係本發明一些實施例中，製造半導體裝置的方法之流程圖。 圖2、3、4、5、6、7、8、及9係本發明一些實施例中，半導體裝置在圖1A及1B的方法之中間階段沿著X方向切面的剖視圖。 圖10A係本發明一些實施例中，半導體裝置的三維透視圖。 圖10B係本發明一些實施例中，半導體裝置的平面上視圖。 圖11A、11A'、12A、13A、14A、15A、16A、及17A係本發明一些實施例中，半導體裝置在圖1A及1B的方法之中間階段沿著Y方向切面的剖視圖。 圖11B、11B'、12B、13B、14B、15B、16B、17B、及17B'係本發明一些實施例中，半導體裝置在圖1A及1B的方法之中間階段沿著X方向切面的剖視圖。
100:方法
118,120,122,124,126,128,130,132:步驟

Claims (1)

  1. 一種半導體裝置的製作方法，包括： 形成自一基板凸起的一鰭狀物，且該鰭狀物具有相對的一第一側壁與一第二側壁； 形成一犧牲介電層於該鰭狀物的一上表面、該第一側壁、與該第二側壁上； 蝕刻該犧牲介電層，以自該鰭狀物的該第二側壁移除該犧牲介電層； 形成一凹陷於該鰭狀物中； 自該凹陷成長一磊晶的源極/汲極結構，該磊晶的源極/汲極結構具有相對的一第一側壁與一第二側壁，其中該犧牲介電層覆蓋該磊晶的源極/汲極結構的該第一側壁； 使該犧牲介電層凹陷，以露出該磊晶的源極/汲極結構的該第一側壁；以及 形成一源極/汲極接點於該磊晶的源極/汲極結構的該第一側壁上。
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