TWI646685B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TWI646685B
TWI646685B TW106128643A TW106128643A TWI646685B TW I646685 B TWI646685 B TW I646685B TW 106128643 A TW106128643 A TW 106128643A TW 106128643 A TW106128643 A TW 106128643A TW I646685 B TWI646685 B TW I646685B
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Taiwan
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fin
gate
region
forming
isolation region
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TW106128643A
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TW201839989A (zh
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范家聲
楊寶如
謝東衡
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台灣積體電路製造股份有限公司
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Abstract

一種半導體裝置及方法包括：形成第一鰭片及第二鰭片於基板上；形成虛設閘極材料於第一鰭片及第二鰭片上方；形成凹口於第一鰭片與第二鰭片之間的虛設閘極材料中；形成犧牲氧化物於凹口中的虛設閘極材料的側壁上；充填絕緣材料於虛設閘極材料的側壁上的犧牲氧化物之間的凹口中；移除虛設閘極材料及犧牲氧化物；以及形成第一替換閘極於第一鰭片上方，並形成第二替換閘極於第二鰭片上方。

Description

半導體裝置及其製造方法
本揭示的實施方式係關於一種半導體裝置及其製造方法。
半導體裝置用於各種電子應用中，例如個人電腦、手機、數位相機、及其他電子設備。半導體裝置的製造通常藉由依序地在半導體基板上方沉積絕緣層或介電層、導電層及半導體層，並使用微影製程及蝕刻製程對各材料層進行圖案化，以在其上形成電路部件及元件。
半導體工業藉由持續減小最小特徵尺寸來持續改進各電子部件(例如，電晶體、二極體、電阻器、電容器等)之整合密度，此允許更多部件整合在給定區域中。然而，隨著最小特徵尺寸減小，在所使用之每個製程內出現額外問題，且應解決彼等額外問題。
本揭示提供一種用於製造半導體裝置的方法，此方法包括形成第一鰭片及第二鰭片於基板上；形成虛 設閘極材料於第一鰭片及第二鰭片上方；形成凹口於第一鰭片與第二鰭片之間的虛設閘極材料中；形成犧牲氧化物於凹口中的虛設閘極材料的側壁上；充填絕緣材料於凹口中的虛設閘極材料的側壁上的犧牲氧化物之間；移除虛設閘極材料及犧牲氧化物；以及形成第一替換閘極於第一鰭片上方，並形成第二替換閘極於第二鰭片上方。
在其他實施方式中，本揭示提供一種半導體裝置，此半導體裝置包括第一鰭片在基板上；第二鰭片在基板上，第二鰭片及第一鰭片具有平行縱軸；第一隔離區，圍繞第一鰭片及第二鰭片；第一閘極堆疊，在第一鰭片上方；第二閘極堆疊，在第二鰭片上方；以及第二隔離區，設置在第一隔離區上方及在第一閘極堆疊與第二閘極堆疊之間，第二隔離區具有平行於第一鰭片及第二鰭片之縱軸的縱軸。
在其他實施方式中，本揭示提供一種用於製造半導體裝置的方法，此方法包括形成第一鰭片於基板之第一區域中，並形成第二鰭片在基板之第二區域中；形成第一隔離區於基板上，第一隔離區圍繞第一鰭片及第二鰭片；形成虛設閘極材料於第一鰭片及第二鰭片上方；形成凹口於虛設閘極材料中；形成犧牲氧化物於虛設閘極材料的側壁上的凹口中；充填絕緣材料於虛設閘極材料的側壁上的犧牲氧化物之間的凹口中；移除虛設閘極材料及犧牲氧化物的剩餘部分；以及形成替換閘極於第一鰭片及第二鰭片上方。
50‧‧‧基板
50B‧‧‧第一區域
50C‧‧‧第二區域
52‧‧‧鰭片
54‧‧‧絕緣材料/隔離區
56‧‧‧鰭片
58‧‧‧虛設介電層
60‧‧‧虛設閘極層
62‧‧‧遮罩層
70‧‧‧虛設閘極
70S‧‧‧側壁
72‧‧‧遮罩
80‧‧‧閘極密封間隔層
82‧‧‧磊晶源極區/汲極區
86‧‧‧閘極間隔層
88‧‧‧層間介電層
90‧‧‧遮罩層
92‧‧‧光阻
94‧‧‧開口
96‧‧‧犧牲氧化物
98‧‧‧隔離區
98S1‧‧‧中間部分
98S2‧‧‧邊緣部分
100‧‧‧凹口
102‧‧‧閘極介電層
104‧‧‧閘電極
106‧‧‧層間介電層
108‧‧‧接觸點
110‧‧‧接觸點
θ1‧‧‧角度
W1‧‧‧第一寬度
W2‧‧‧第二寬度
Dg‧‧‧間隙填充距離
A-A‧‧‧橫截面
B-B‧‧‧橫截面
C-C‧‧‧線
當結合附圖閱讀時，自以下詳細描述可以最佳地理解本揭示的態樣。應當注意，根據工業中標準實務，各特徵未按比例繪製。事實上，為論述的清楚性，各特徵之尺寸可任意地增加或縮小。
第1圖係繪示根據一些實施方式之三維視圖中的鰭式場效電晶體(FinFET)的實施例。
第2圖至第19C圖係根據一些實施方式之FinFET製造中間階段的橫截面及平面圖。
以下揭示提供許多不同實施方式或實施例，以實現本揭示之不同的特徵。下文描述部件及排列之特定之實施例以簡化本揭示。當然，此等僅為實施例而非用以作為限制。舉例而言，在隨後描述中在第二特徵上方或在第二特徵上第一特徵之形成可包括第一特徵及第二特徵形成為直接接觸之實施方式，亦可包括有另一特徵可形成在第一及第二特徵之間，使得第一及第二特徵可不直接接觸之實施方式。另外，本揭示可在各實施例中重複元件符號及/或字母。此重複為出於簡化及清楚之目的，且本身不指示所論述的各實施方式及/或結構之間之關係。
另外，於此使用的空間相對術語，例如「之下」、「下方」、「下部」、「上方」、「上部」及類似用語，係為了便於描述圖示中的一個元件或特徵與另一元件(或多個元件)或特徵(或多個特徵)之關係。這些空間性相對用詞本 意上涵蓋除了圖中所繪示的位向之外，也涵蓋使用或操作中之裝置的不同位向。裝置也可被轉換成其他位向(旋轉90度或其他位向)，因此本文中使用的空間性相對描述應做類似的解釋。
根據各實施方式提供了半導體裝置及其形成方法。詳言之，隔離區形成於FinFET裝置之鄰近閘極之間。在一後閘極製程中，形成FinFET裝置，且在中間製造階段中，由多晶矽形成虛設閘極。凹部形成於相鄰鰭片之間的虛設閘極中，且虛設閘極的暴露側壁經氧化以形成犧牲氧化物。以絕緣材料充填凹口，形成隔離區。移除虛設閘極及犧牲氧化物，並以金屬閘極替換。在形成隔離區後且形成金屬閘極前，犧牲氧化物的形成增加了隔離區與金屬閘極之間的間隙填充距離。因此，當形成金屬閘極時，可減少隔離區與金屬閘極之間的孔洞及凹坑之形成。
第1圖繪示在三維視圖中之FinFET的實施例。FinFET包括鰭片56，鰭片56位於基板50上。基板50包括隔離區54，且鰭片56從相鄰的隔離區54之間突出於上方。閘極介電質102係位於鰭片56之頂表面上，且沿著鰭片56的側壁，而閘電極104位於閘極介電質102之上。源極區/汲極區82設置於鰭片56的側邊中，對向於閘極介電質102及閘電極104。第1圖進一步繪示在後續圖中所使用的參考橫截面及參考線。橫截面A-A橫跨FinFET的通道、閘極介電質102及閘電極104。橫截面B-B垂直於橫截面A-A，沿著鰭片56的縱軸，舉例而言，並位於源極區/汲極區82之間 的電流流動方向上。為清晰起見，後續圖參考遵循這些參考橫截面。
第2圖至第5圖係根據一些實施方式之FinFET製造中間階段的橫截面圖。第2圖至第5圖係沿著第1圖之橫截面A-A進行繪示，除了多個FinFET外。
第2圖中提供基板50。基板50可以是半導體基板，例如塊狀半導體(bulk semiconductor)、絕緣體上半導體(semiconductor-on-insulator,SOI)基板或其類似基板，其可以是有經過摻雜(例如，摻雜p型雜質或n型雜質)或無摻雜的。基板50可以是晶圓，例如矽晶圓。一般而言，SOI基板係形成在絕緣層上的半導體材料層。舉例而言，絕緣層可以是內埋式氧化物(buried oxide,BOX)層、氧化矽層或其類似層。絕緣層設置在基板上，通常為矽基板或玻璃基板。亦可使用其他基板，例如多層基板或梯度基板(gradient substrate)。在一些實施方式中，基板50的半導體材料可包括矽、鍺、化合物半導體、合金半導體或其組合，化合物半導體包括碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦，合金半導體包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP。
基板50具有第一區域50B及第二區域50C。第一區域50B可用於形成n型裝置，例如n型金屬-氧化物-半導體(n-type metal-oxide-semiconductor,NMOS)場效電晶體，n型FinFET即為一例。第二區域50C可用於形成p型裝置，例如p型金屬-氧化物-半導體(p-type metal-oxide-semiconductor,PMOS)場效電晶體，p型FinFET即為一例。在一些實施方式中，第一區域50B與第二區域50C皆用於形成相同類型的裝置，舉例而言，這兩個區域均用於n型裝置或均用於p型裝置。
在第3圖中，鰭片52形成於基板50中。鰭片52是條狀半導體。在一些實施方式中，可藉由在基板50中蝕刻溝槽，從而在基板50中形成鰭片52。蝕刻可以是任何合適的蝕刻製程，例如活性離子蝕刻(reactive ion etch,RIE)、中性束蝕刻(neutral beam etch,NBE)、其類似製程或其一組合。蝕刻可以是各向異性的。鰭片52可以具有各自平行的縱軸。
在第4圖中，絕緣材料54形成於相鄰的鰭片52之間，以形成隔離區54。絕緣材料54可為氧化物，例如氧化矽、氮化物、其類似物或其一組合，並可藉由高密度電漿化學氣相沉積(high density plasma chemical vapor deposition,HDP-CVD)、流動化學氣相沉積(flowable CVD,FCVD)(例如，在遠端電漿系統中基於化學氣相沉積的材料沉積及後續固化，以使其轉換為另一材料，例如氧化物)、其類似製程等或其一組合來形成。可使用由任何合適之製程所形成的其他絕緣材料。在所繪示之實施方式中，絕緣材料54係藉由流動化學氣相沉積(FCVD)製程所形成的氧化矽。一旦形成絕緣材料後，可施予退火製程。絕緣材料54可稱作隔離區54。另外在第4圖中，平坦化製程，例如化學機械研磨(chemical mechanical polish,CMP)，可移 除任何多餘的絕緣材料54，並形成隔離區54之頂表面及鰭片52之頂表面，隔離區54之頂表面及鰭片52之頂表面是對齊的。
在第5圖中，隔離區54內凹以形成淺溝槽隔離區(Shallow Trench Isolation,STI)54。隔離區54內凹而使得第一區域50B及第二區域50C中的鰭片56從相鄰的隔離區54之間突出。此外，隔離區54的頂表面可具有如圖所示之平坦表面、也可具有凸表面、凹表面(例如凹陷)或其一組合。可藉由合適的蝕刻來形成平面、凸面及/或凹面之隔離區54頂表面。可使用合適的蝕刻製程使隔離區54內凹，例如對隔離區54的材料具有選擇性的蝕刻製程。例如使用CERTAS®蝕刻、應用材料SICONI(Applied Material SICONI)工具或稀釋的氫氟酸(dilute hydrofluoric acid,dHF)的化學氧化物移除。
所屬技術領域中具有普通技能者將易於理解的是，第2圖至第5圖所描述的製程僅是如何可形成鰭片56的一個實施例。在一些實施方式中，介電層可形成於基板50的頂表面上方；可穿過介電層蝕刻溝槽；同質磊晶結構可在溝槽中磊晶生長；且可內凹介電層，使得同質磊晶結構從介電層突出，以形成鰭片。在一些實施方式中，同質磊晶結構可用於鰭片52。舉例而言，可內凹第4圖中之鰭片52，其位置中可磊晶生長不同於鰭片52的材料。在又一實施方式中，介電層可形成於基板50的頂表面上方；可穿過介電層蝕刻溝槽；可使用與基板50不同的材料，在溝槽中磊晶生 長同質磊晶結構；且可內凹介電層，使得同質磊晶結構從介電層突出，以形成鰭片56。在磊晶生長同質磊晶或異質磊晶結構的一些實施方式中，在生長期間，可原位摻雜生長材料，這可避免預先植入和後續植入，儘管可同時使用原位摻雜及植入摻雜。更進一步而言，這有利於在NMOS區域中磊晶生長不同於PMOS區域中的材料。在各實施方式中，鰭片56可由矽鍺(SixGe1-x，其中x可介於約0與1之間)、碳化矽、純或基本上純的鍺、III價-V價化合物半導體、II價-VI價化合物半導體或其類似物所形成。舉例而言，可用於形成III價-V價化合物半導體的材料包括但不限於InAs、AlAs、GaAs、InP、GaN、InGaAs、InAlAs、GaSb、AlSb、AlP、GaP及其類似材料。
另外在第5圖中，可在鰭片56、鰭片52及/或基板50中形成合適的井(未圖示)。在一些實施方式中，可在第一區域50B中形成P井，並可在第二區域50C中形成N井。在一些實施方式中，第一區域50B及第二區域50C中皆形成P井或N井。
在具有不同井類型之實施方式中，使用光阻或其他遮罩(未圖示)可達成在第一區域50B及第二區域50C的不同植入步驟。舉例而言，在第一區域50B中，光阻可形成於鰭片56及隔離區54上方。對光阻作圖案化，以暴露基板50的第二區域50C，例如PMOS區域。可藉由使用旋塗技術來形成光阻，並可使用合適的光刻方法而圖案化。一旦將光阻圖案化後，在第二區域50C中施予n型雜質的植入，且 光阻可充當遮罩，以便基本上防止n型雜質被植入到第一區域50B中，例如NMOS區域。n型雜質可以是磷、砷、或植入在第二區域中的類似物，其濃度等於或小於1018cm-3，例如介於約1017cm-3與約1018cm-3之間。在植入之後移除光阻，例如藉由合適的灰化製程。
在第二區域50C之植入後，在第二區域50C中，光阻形成於鰭片56及隔離區54上。對光阻作圖案化，以暴露基板50的第一區域50B，例如NMOS區域。可藉由使用旋塗技術來形成光阻，並可使用合適的光刻方法來將光阻圖案化。一旦將光阻圖案化後，可在第一區域50B中施予p型雜質的植入，且光阻可充當遮罩，以便基本上防止p型雜質被植入到第二區域50C中，例如PMOS區域。p型雜質可以是硼、BF2、或植入在第一區域中的類似物，其濃度等於或小於1018cm-3，例如介於約1017cm-3與約1018cm-3之間。在植入之後可移除光阻，例如藉由合適的灰化製程。
在第一區域50B及第二區域50C的植入後，可施予退火，以活化被植入的p型雜質及/或n型雜質。在一些實施方式中，在生長期間，可原位摻雜磊晶鰭片的生長材料，這可避免植入，儘管原位摻雜及植入摻雜是可以同時使用的。
第6A圖至第19C圖係根據一些實施方式之更進一步的FinFET製造中間階段的橫截面圖及平面圖。在第6A圖至第19C圖中，圖示標號以「A」結尾的圖係沿著第1圖之橫截面A-A來繪示，除了多個FinFET之外。而圖示標 號以「B」結尾的圖係沿著第1圖之橫截面B-B來繪示，任第一區域50B或第二區域50C，皆可表示FinFET。圖示標號以「C」結尾之圖係相對於各橫截面圖中的C-C線來繪示的平面圖。
在第6A圖及第6B圖中，虛設介電層58形成於鰭片56上。舉例而言，虛設介電層58可以是氧化矽、氮化矽、其一組合或其類似物，且可根據合適的方法沉積或熱生長。在一些實施方式中，虛設介電層58保形地形成在鰭片56及隔離區54上方。在一些實施方式(未圖示)中，虛設介電層58僅形成在鰭片56之頂表面上及側壁上，並沒有形成在隔離區54上方。
進一步地，在第6A圖及第6B圖中，虛設閘極層60形成在虛設介電層58上方。虛設閘極層60可沉積在虛設介電層58上方，隨後進行平坦化，例如藉由化學機械研磨(CMP)。虛設閘極層60可以是導電材料，且可選自包括多晶矽(複晶矽)、多晶矽鍺(poly-crystalline silicon-germanium,poly-SiGe)、金屬氮化物、金屬矽化物、金屬氧化物及金屬的一群組。在一個實施方式中，沉積及再結晶非晶矽，以產生多晶矽。可藉由物理氣相沉積、化學氣相沉積、濺射沉積或導電材料沉積技術中已知及已使用的其他方法來沉積虛設閘極層60。虛設閘極層60可由其他材料製成，這些材料係對隔離區的蝕刻具有高蝕刻選擇性。
進一步地，在第6A圖及第6B圖中，遮罩層62形成在虛設閘極層60上方。遮罩層62可沉積在虛設閘極層 60上方。遮罩層62可由介電質形成，舉例而言，可包括SiN、SiON或其類似物。
在此實施例中，單虛設閘極層60及單遮罩層62形成且橫跨第一區域50B及第二區域50C。在一些實施方式中，分隔的虛設閘極層可形成在第一區域50B及第二區域50C中，而分隔的遮罩層可形成在第一區域50B及第二區域50C中。
在第7A圖及第7B圖中，可使用合適的光刻及蝕刻技術來對遮罩層62圖案化，以形成遮罩72。可藉由合適的蝕刻技術，來將遮罩72的圖案轉移至虛設閘極層60及虛設介電層58，以形成虛設閘極70。虛設閘極70覆蓋鰭片56各別的通道區。虛設閘極70亦可具有一個縱向方向，此縱向方向基本上垂直於各別磊晶鰭片的縱向方向。
進一步地，在第7A圖及第7B圖中，閘極密封間隔層80可形成在虛設閘極70、遮罩72及/或鰭片56的暴露表面上。熱氧化或沉積，伴隨各向異性蝕刻可形成閘極密封間隔層80。
在形成閘極密封間隔層80之後，可對輕度摻雜的源極區/汲極區(Lightly doped source/drain,LDD)(未圖示)施予植入。在不同裝置類型之實施方式中，遮罩可形成於第一區域50B上方，例如光阻，類似於上述第5圖中的植入，同時暴露第二區域50C，且在第二區域50C中，合適類型的雜質(例如n型或p型)可被植入到暴露鰭片56中。隨後可移除遮罩。接下來，遮罩可形成於第二區域50C上方， 例如光阻，同時暴露第一區域50B，且在第一區域50B中，合適類型的雜質可被植入到暴露鰭片56中。隨後可移除遮罩。n型雜質可以是任一上述n型雜質，且p型雜質可以是任一上述p型雜質。輕度摻雜之源極區/汲極區可具有約1015cm-3至約1016cm-3的雜質濃度。退火可用以活化所植入的雜質。
在第8A圖及第8B圖中，磊晶源極區/汲極區82形成於鰭片56中。磊晶源極區/汲極區82形成於鰭片56中，使得每個虛設閘極70設置在一對對相鄰的磊晶源極區/汲極區82之間。在一些實施方式中，磊晶源極區/汲極區82可延伸入鰭片52中。
在第一區域50B中，例如NMOS區域，其內的磊晶源極區/汲極區82的形成，可藉由遮蔽第二區域50C，例如PMOS區域，並且在第一區域50B中保形地沉積虛設間隔層，隨後進行各向異性蝕刻，以沿著第一區域50B中的虛設閘極70的側壁，及/或閘極密封間隔層80之側壁，形成虛設閘極間隔層(未圖示)。接下來，蝕刻第一區域50B中之磊晶鰭片的源極區/汲極區，以形成凹口。第一區域50B中之磊晶源極區/汲極區82在凹口中進行磊晶生長。磊晶源極區/汲極區82可包括任一合適的材料，例如適用於n型FinFET的材料。舉例而言，若鰭片56為矽，磊晶源極區/汲極區82可包括矽、SiC、SiCP、SiP或其類似物。磊晶源極區/汲極區82可以具有從鰭片56個別表面升起之表面，且可具有 小面。接下來，移除第一區域50B中的虛設閘極間隔層，例如藉由蝕刻，如同第二區域50C上的遮罩。
在第二區域50C中，例如PMOS區域，其內的磊晶源極區/汲極區82的形成，可藉由遮蔽第一區域50B，例如NMOS區域，並且在第二區域50C中保形地沉積虛設間隔層，隨後進行各向異性蝕刻，以沿著第二區域50C中的虛設閘極70的側壁，及/或閘極密封間隔層80之側壁，形成虛設閘極間隔層(未圖示)。接下來，蝕刻第二區域50C中之磊晶鰭片之源極區/汲極區，以形成凹口。第二區域50C中之磊晶源極區/汲極區82在凹口中進行磊晶生長。磊晶源極區/汲極區82可包括任一合適的材料，例如適用於p型FinFET的材料。舉例而言，若鰭片56為矽，磊晶源極區/汲極區82可包括SiGe、SiGeB、Ge、GeSn或其類似物。磊晶源極區/汲極區82可具有自鰭片56個別表面升起之表面，且可具有小面。接下來，移除第二區域50C中的虛設閘極間隔層，例如藉由蝕刻，如同第一區域50B上的遮罩。
在第9A圖及第9B圖中，閘極間隔層86形成在沿著虛設閘極70及遮罩72之側壁的閘極密封間隔層80上。可藉由保形地沉積材料，隨後對此材料進行各向異性地蝕刻，以形成閘極間隔層86。閘極間隔層86的材料可以是介電材料，例如氮化矽、SiCN、其一組合或其類似物。
磊晶源極區/汲極區82及/或磊晶鰭片可被植入雜質，以形成源極區/汲極區，類似於上述用於形成輕度摻雜之源極區/汲極區，隨後進行退火的製程。源極區/汲極區 可具有介於約1019cm-3至約1021cm-3之間的雜質濃度。源極區/汲極區之n型雜質及/或p型雜質可以是前述雜質之任一者。在一些實施方式中，在生長期間，可原位摻雜磊晶源極區/汲極區82。
在第10A圖及第10B圖中，層間介電層88(interlayer dielectric,ILD)沉積在第9A圖及第9B圖中所示的結構上。層間介電層88可由介電材料或半導體材料形成，及可藉由任一合適方法，例如化學氣相沉積、電漿增強化學氣相沉積(plasma-enhanced CVD,PECVD)或流動化學氣相沉積(FCVD)而沉積。介電材料可包括磷酸矽酸鹽玻璃(Phospho-Silicate Glass,PSG)、硼矽酸鹽玻璃(Boro-Silicate Glass,BSG)、硼摻雜磷酸矽酸鹽玻璃(Boron-Doped Phospho-Silicate Glass,BPSG)、無摻雜矽酸鹽玻璃(undoped Silicate Glass,USG)或其類似物。半導體材料可包括非晶矽、矽鍺(SixGe1-x，其中x可介於約0與1之間)、純鍺或其類似物。可使用由任一合適製程形成的其他絕緣材料或半導體材料。
在第11A圖及第11B圖中，可施予平坦化製程，例如化學機械研磨(CMP)，以使得層間介電層88的頂表面與虛設閘極70的頂表面對齊。此平坦化製程亦可移除虛設閘極70上的遮罩72、部分的閘極密封間隔層80及部分的閘極間隔層86。在平坦化製程之後，虛設閘極70、閘極密封間隔層80、閘極間隔層86及層間介電層88之頂表面對齊。因此，虛設閘極70的頂表面穿過層間介電層88而暴露。
在第12A圖及第12B圖中，遮罩層90，例如硬遮罩，沉積在第11A圖及第11B圖所示之結構上。遮罩層90可由SiN、SiON、SiO2、其類似物或其組合製造得到。遮罩層90可藉由化學氣相沉積、物理氣相沉積、原子層沉積(Atomic layer deposition,ALD)、旋塗介電製程(spin-on-dielectric process)、其類似製程或其一組合而形成。
在第13A圖及第13B圖中，光阻92在遮罩層90上形成並被圖案化。在一些實施方式中，光阻92可藉由旋塗技術來形成，且可使用合適的光刻技術而被圖案化。在圖案化光阻92之後，可在光阻92上執行修整製程，以減少圖案化後光阻92的寬度。在一實施方式中，修整製程是一個各向異性電漿蝕刻製程，具有包括O2、CO2、N2/H2、H2、其類似氣體、其一組合、或適用於修整光阻之任何其他氣體之製程氣體。
在一些實施方式中，光阻92為三層光阻。在這些實施方式中，三層光阻92包括頂端光阻層、中間層及底層。隨著高階半導體製程已達到光刻製程的極限，產生了更薄的頂端光阻層之需求，以獲到更小之製程窗口。然而，薄的頂端光阻層的穩固性可能不足以支持標的層(例如遮罩層90)之蝕刻。三層光阻提供了相對薄的頂端光阻層。中間層可包括抗反射材料(例如，背側抗反射塗層(backside anti-reflective coating,BARC))以輔助頂端光阻層之製程的暴露及聚焦。藉由具有中間層，薄的頂端光阻層僅用以 圖案化中間層。底層可包括硬遮罩材料，例如可藉由O2或N2/H2電漿而輕易移除的含碳材料。中間層係用以圖案化底層。在一些實施方式中，中間層具有對底層的高蝕刻選擇性，以及在一些實施方式中，底層的厚度比中間層的厚度高出十倍以上。因而，三層光阻92成功使得其下方層(例如，遮罩層90)穩定地圖案化，同時仍然提供相對薄的頂端光阻層。
三層光阻92的頂端光阻層可使用任一合適的光刻技術而圖案化。舉例而言，光遮罩(未圖示)可設置在頂端光阻層上方，其隨後可暴露於輻射束，此輻射束包括紫外線(UV)或準分子雷射，例如來自氟化氪(KrF)248奈米光束的準分子雷射、來自氟化氬(ArF)193奈米光束的準分子雷射、或來自F2 157奈米光束的準分子雷射。進行頂端光阻層之暴露時，可使用浸入微影系統，以增大解析度及減小最小可獲得的間距。可進行烘烤或固化操作，以硬化頂端光阻層，且可根據所使用的顯影劑是正抗蝕劑還是負抗蝕劑，以移除頂端光阻層的暴露部分或未暴露部分。在圖案化三層光阻92的頂端光阻層之後，可執行修整製程，以減少三層光阻92之頂端光阻層的寬度。在一實施方式中，修整製程是一個各向異性電漿蝕刻製程，具有包括O2、CO2、N2/H2、H2、其類似氣體、其一組合、或適用於修整光阻之任何其他氣體之製程氣體。在修整製程之後，可圖案化中間層及底層，以留下圖案化的三層光阻92，如第13A圖及第13B圖所繪示。
在第14A圖、第14B圖及第14C圖中，使用光阻92作為遮罩，圖案化遮罩層90及虛設閘極70。可使用任一合適蝕刻製程來執行遮罩層90之圖案化，例如各向異性乾蝕刻製程。可持續蝕刻製程，以圖案化虛設閘極70。在一些實施方式中，可藉由蝕刻製程來移除部分虛設介電層58。此圖案化形成開口94，開口94分隔第一區域50B中的鰭片56與第二區域50C中的鰭片56。隔離區54的頂表面可由開口94而暴露。接下來移除光阻92。
開口94由隔離區54的暴露表面、虛設閘極70剩餘部分的側壁70S、以及閘極間隔層86的內表面而界定。在一些實施方式中，虛設閘極70剩餘部分的側壁70S相對傾斜於基板50的主要表面。換言之，虛設閘極70剩餘部分的側壁70S不平行於且不垂直於基板50的主要表面。在一些實施方式中，虛設閘極70剩餘部分的側壁70S與平行於基板50的主要表面之平面形成角度θ1。在一實施方式中，角度θ1大於約90°，例如介於約92°至約97°之範圍中。另外，從垂直於鰭片56之縱軸的方向上量測，開口94與隔離區54的交界面處(例如，開口94之底部)比開口94的頂端更狹窄，使得開口94自頂端向底部逐漸變細。另外在平面圖中，開口94具有啞鈴形狀。結果，開口94的第一寬度W1小於開口94的第二寬度W2，開口94的第一寬度W1位於遠離閘極間隔層86的中心部分內，開口94的第二寬度W2位於靠近閘極間隔層86的邊緣部分內。
在第15A圖、第15B圖及第15C圖中，犧牲氧化物96形成於開口94內虛設閘極70的暴露側壁上。犧牲氧化物96是虛設閘極70之材料的氧化物，例如可以是原生氧化物、電漿氧化物或其類似氧化物。犧牲氧化物96可以是類似於虛設介電層58，或可以是不同的。可使用氧化製程來形成犧牲氧化物96，例如熱氧化製程、快速熱氧化製程(rapid thermal oxidation,RTO)、化學氧化製程、臨場蒸氣產生製程(ISSG)或增強臨場蒸氣產生製程(EISSG)。舉例而言，可在含氧環境中施予快速熱退火(rapid thermal anneal,RTA)。熱氧化可在約800℃至約1100℃的溫度下進行，例如約800℃。溫度可有助於犧牲氧化物96的厚度；較高的溫度可產生較厚的犧牲氧化物96。施予熱氧化的時間跨度為約10秒至約20秒，例如約15秒。時間跨度亦可有助於犧牲氧化物96之厚度；較長的氧化時間跨度可產生較厚的犧牲氧化物96。在完成後，熱氧化可形成厚度為約28Å至約56Å的犧牲氧化物96，例如約40Å。在一些實施方式中，可施予其他氧化製程。氧化製程可僅氧化虛設閘極70的材料，使得犧牲氧化物96僅形成在虛設閘極70的側壁上，並不形成在遮罩層90上。
在第16A圖、第16B圖及第16C圖中，絕緣材料形成在開口94中，以形成隔離區98。隔離區98提供第一區域50B中的虛設閘極70與第二區域50C中的虛設閘極70之間的隔離。絕緣材料可以是氧化物，例如氧化矽、氮化物、其類似物或其一組合，並可藉由高密度電漿化學氣相沉積 (high density plasma chemical vapor deposition,HDP-CVD)、流動化學氣相沉積(FCVD)(例如在遠端電漿系統及後固化中，基於化學氣相沉積的材料沉積，以使其轉變為另一材料，例如氧化物)、其類似製程或其一組合而形成。可以使用藉由任一合適製程所形成的其他絕緣材料。隔離區98的絕緣材料可與絕緣材料54是相同的，也可以是不同的。在所示的實施方式中，絕緣材料為氮化矽。在形成隔離區98後，隔離區98被夾在犧牲氧化物96之間，犧牲氧化物96係形成於開口94的各別側壁上。由SiN形成隔離區98的實施方式中，形成於開口94中的結構可稱為氧化物-SiN-氧化物夾層結構，或更一般地可稱為氧化物-氮化物-氧化物夾層結構。
隔離區98的形狀係由開口94所界定，例如隔離區54的暴露表面、虛設閘極70的暴露側壁及閘極間隔層86的暴露側壁。換言之，隔離區98可具有的形狀類似於開口94之形狀。因而，隔離區98底部的寬度可小於隔離區98頂部的寬度(例如第16A圖)，且在平面圖中(例如第16C圖)，隔離區98可具有啞鈴形狀。隔離區98的縱軸平行於鰭片56的縱軸。位於相鄰的閘極間隔層86之間的隔離區98的側壁與一平面有角度θ1，此平面平行於基板50的主要表面，類似於虛設閘極70剩餘部分的對應側壁70S。另外在俯視圖中，虛設閘極70剩餘部分的側壁70S不是平面，而是凸出的，而在俯視圖中，隔離區98是較寬的。在俯視圖中，隔離區98具有啞鈴形狀。隔離區包括具有第一寬度W1的中間 部分98S1，及具有第二寬度W2的邊緣部分98S2。邊緣部分98S2接觸相鄰的閘極間隔層86的側壁，而中間部分98S1在邊緣部分98S2之間延伸。
在第17A圖、第17B圖及第17C圖中，在蝕刻步驟中，移除犧牲氧化物96、閘極密封間隔層80、直接位於暴露虛設閘極70下方的部分虛設介電層58、以及虛設閘極70之剩餘部分，以形成凹口100。在一些實施方式中，藉由各向異性乾蝕刻製程來移除虛設閘極70。舉例而言，蝕刻製程可包括乾蝕刻製程，乾蝕刻製程使用的反應氣體選擇性地蝕刻虛設閘極70，而不蝕刻隔離區98、層間介電層88或閘極間隔層86。每個凹口100暴露各別鰭片56的通道區。每個通道區設置在相鄰的每一對磊晶源極區/汲極區82之間。在移除期間，在蝕刻虛設閘極70時，虛設介電層58可用以作為蝕刻停止層。在移除虛設閘極70之後，接下來可移除虛設介電層58及閘極密封間隔層80。
可在用以移除虛設介電層58的相同蝕刻步驟中，移除犧牲氧化物96。所施予的蝕刻步驟可對犧牲氧化物96及/或虛設介電層58的材料具有選擇性。移除犧牲氧化物96可增大位於隔離區98與鰭片56之間的間隙填充距離(gap fill distance,Dg)(有時稱作「間隙填充窗口」)。在形成金屬閘電極104(示於下文)時，可沿著隔離區98及鰭片56的側壁形成金屬。增大間隙填充窗口可改進用於金屬填充之窗口，這可減少金屬在沿每個側壁形成時發生合併之機會。如此可避免在完成之FinFET裝置中形成孔洞及凹坑。 除了改進用於金屬填充之窗口外，增大間隙填充窗口亦可改進蝕刻之窗口。間隙填充距離Dg可藉由調整形成犧牲氧化物96之氧化製程參數來控制，從而控制犧牲氧化物96之厚度。
在第18A圖、第18B圖及第18C圖中，形成閘極介電層102及閘電極104以作為替換閘極。閘極介電層102保形地沉積在凹口100中，比如在鰭片56的側壁及頂表面上、在閘極間隔層86的側壁上，以及在層間介電層88的頂表面上。閘極介電層102可(或可沒有)沉積在隔離區98的側壁上。根據一些實施方式，閘極介電層102包括氧化矽、氮化矽或其多層。在其他實施方式中，閘極介電層102包括高介電常數介電材料，且在這些實施方式中，閘極介電層102可具有大於約7.0之介電常數值，並可包括Hf、Al、Zr、La、Mg、Ba、Ti、Pb及其組合之金屬氧化物或矽酸鹽。閘極介電層102的形成方法可包括分子束沉積(Molecular-Beam Deposition,MBD)、原子層沉積(ALD)、電漿增強化學氣相沉積(PECVD)及其類似方法。
接下來，閘電極104分別沉積在閘極介電層102上方，並充填凹口100的剩餘部分。閘電極104可包括含金屬材料，例如TiN、TaN、TaC、Co、Ru、Al、其組合或其多層。在充填閘電極104之後，可執行平坦化製程，例如化學機械研磨(CMP)，以移除閘極介電層102的多餘部分及閘電極104的材料，其多餘部分位於層間介電層88及隔離區98的頂表面上方。在平坦化製程之後，隔離區98、閘極介 電層102及閘電極104的頂表面是對齊的。所產生剩餘部分之閘電極104及閘極介電層102因此形成了所得到之FinFET的替換閘極。替換閘極可統稱為「閘極堆疊」或簡單地稱為「閘極」。
閘極介電層102的形成可同時發生，使得閘極介電層102包括相同材料，且閘電極104的形成可同時發生，使得閘電極104包括相同材料。然而，在其他實施方式中，閘極介電層102可由不同製程形成，使得閘極介電層102可包括不同材料，且閘電極104可由不同製程形成，使得閘電極104可包括不同材料。可使用各種遮蔽步驟，以便在使用不同製程時遮住及暴露合適的區域。
在形成替換閘極後，隔離區98將第一區域50B中的替換閘極與第二區域50C中具有相同縱軸的替換閘極分隔。隔離區98提供第一區域50B中的替換閘極與第二區域50C中的替換閘極之間的隔離。
在第19A圖、第19B圖及第19C圖中，層間介電層106沉積於層間介電層88上方，而接觸點108及接觸點110通過層間介電層106及層間介電層88而形成。層間介電層106形成於層間介電層88、替換閘極、閘極間隔層86及隔離區98的上方。層間介電層106由介電材料所形成，例如磷酸矽酸鹽玻璃(PSG)、硼矽酸鹽玻璃(BSG)、硼摻雜磷酸矽酸鹽玻璃(BPSG)、無摻雜矽酸鹽玻璃(USG)或其類似材料，並可藉由任一合適方法而沉積，例如化學氣相沉積(CVD)及電漿增強化學氣相沉積(PECVD)。接觸點108及 接觸點110通過層間介電層88及層間介電層106，而形成開口。可使用合適的光刻技術及蝕刻技術來形成開口。開口中形成襯層及導電材料，襯層例如擴散阻障層(diffusion barrier layer)、黏附層或其類似物。襯層可包括鈦、氮化鈦、鉭、氮化鉭或其類似物。導電材料可以是銅、銅合金、銀、金、鎢、鋁、鎳或其類似物。可執行平坦化製程從層間介電層106表面移除多餘的材料，例如化學機械研磨(CMP)。剩餘的襯層及導電材料在開口中形成接觸點108及接觸點110。可執行退火製程，以分別在磊晶源極區/汲極區82與接觸點108之間的界面形成矽化物。接觸點108實體上及電性耦接至磊晶源極區/汲極區82。接觸點110實體上及電性耦接至閘電極104。
儘管未明確繪示，然而所屬技術領域中具有普通技能者將易於理解的是，可對第19A圖、第19B圖及第19C圖中的結構執行進一步的加工步驟。舉例而言，可在層間介電層106上方形成各種金屬間介電層(Inter-Metal Dielectrics,IMD)，以及他們相對應的金屬化產物。
實施方式可得到一些優點。薄化鰭片之間的隔離區，可增大裝置的間隙填充窗口及蝕刻窗口，這可避免在最後所形成的裝置中形成孔洞及凹坑。增大間隙填充窗口使得能夠使用多晶矽形成虛設閘極，而非其他材料。在形成虛設閘極層時，採用多晶矽而非金屬的話，使得在替換虛設閘極時可減少層間介電層之損失量，可減少的損失量高達 30nm。多晶矽虛設閘極可較易於替換，這是因為縮小了裝置尺寸與接下來的閘極尺寸。
一實施方式包括一種方法。此方法包括：形成第一鰭片及第二鰭片於基板上；形成虛設閘極材料於第一鰭片及第二鰭片上方；形成凹口於第一鰭片與第二鰭片之間的虛設閘極材料中；形成犧牲氧化物於凹口中的虛設閘極材料的側壁上；充填絕緣材料於凹口中的虛設閘極材料的側壁上的犧牲氧化物之間；移除虛設閘極材料及犧牲氧化物；以及形成第一替換閘極於第一鰭片上方，並形成第二替換閘極於第二鰭片上方。
一實施方式包括一種裝置。此裝置包括：第一鰭片在基板上；第二鰭片在基板上，第二鰭片及第一鰭片具有平行縱軸；第一隔離區，圍繞第一鰭片及第二鰭片；第一閘極堆疊，在第一鰭片上方；第二閘極堆疊，在第二鰭片上方；以及第二隔離區，設置在第一隔離區上方，並位於第一閘極堆疊與第二閘極堆疊之間。
一實施方式包括一種方法。此方法包括：形成第一鰭片於基板之第一區域中，並形成第二鰭片在基板之第二區域中；形成第一隔離區於基板上，第一隔離區圍繞第一鰭片及第二鰭片；形成虛設閘極材料於第一鰭片及第二鰭片上方；形成凹口於虛設閘極材料中；形成犧牲氧化物於虛設閘極材料的側壁上的凹口中；充填絕緣材料於虛設閘極材料的側壁上的犧牲氧化物之間的凹口中；移除虛設閘極材料及 犧牲氧化物的剩餘部分；以及形成替換閘極於第一鰭片及第二鰭片上方。
前文概述若干實施方式之特徵，使得熟習此項技術者可更好地理解本揭示案之態樣。熟習此項技術者應瞭解，他們可輕易使用本揭示作為設計或修改其他製程及結構的基礎，以便實施與本揭示所介紹之實施方式相同之目的及/或實現相同優點。熟習此項技術者亦應認識到，此類等效結構並未脫離本揭示之精神及範疇，且可在不脫離本揭示之精神及範疇的情況下於此作出各種變化、替代及更改。

Claims (10)

  1. 一種用於製造半導體裝置的方法，該方法包含：形成一第一鰭片及一第二鰭片於一基板上；形成一虛設閘極材料於該第一鰭片及該第二鰭片上方；形成一凹口於該第一鰭片與該第二鰭片之間的該虛設閘極材料中；形成一犧牲氧化物於該凹口中的該虛設閘極材料的側壁上；充填一絕緣材料於該凹口中的該虛設閘極材料的所述側壁上的該犧牲氧化物之間；移除該虛設閘極材料及該犧牲氧化物；以及形成一第一替換閘極於該第一鰭片上方，並形成一第二替換閘極於該第二鰭片上方。
  2. 如請求項1所述之方法，其中充填該絕緣材料於所述側壁上的該犧牲氧化物之間，包含在所述側壁上的該犧牲氧化物之間形成氮化矽。
  3. 如請求項1所述之方法，其中在該虛設閘極材料中形成該凹口包含：形成具有一第一寬度及一第二寬度之該凹口，該第一寬度靠近該基板，該第二寬度遠離該基板，該第二寬度大於該第一寬度。
  4. 如請求項1所述之方法，其中在該第一鰭片上方形成該第一替換閘極及在該第二鰭片上方形成該第二替換閘極包含：在該第一鰭片與該絕緣材料之間，以及在該第二鰭片與該絕緣材料之間形成金屬。
  5. 一種半導體裝置，該裝置包含：一第一鰭片，在一基板上；一第二鰭片，在該基板上，該第二鰭片及該第一鰭片具有平行縱軸；一第一隔離區，圍繞該第一鰭片及該第二鰭片；一第一閘極堆疊，在該第一鰭片上方；一第二閘極堆疊，在該第二鰭片上方；一第二隔離區，設置在該第一隔離區上方及在該第一閘極堆疊與該第二閘極堆疊之間，該第二隔離區具有平行於該第一鰭片及該第二鰭片之所述縱軸的一縱軸；以及多個閘極間隔層，鄰近該第一閘極堆疊及該第二閘極堆疊，且該第二隔離區位於兩相鄰的該些閘極間隔層之間，其中該第二隔離區具有一第一寬度鄰近該些閘極間隔層，且具有一第二寬度遠離該些閘極間隔層，且該第一寬度大於該第二寬度。
  6. 如請求項5所述之裝置，其中該第二隔離區包含氮化矽。
  7. 如請求項5所述之裝置，其中該第一隔離區及該第二隔離區是不同的材料。
  8. 如請求項5所述之裝置，其中該第一閘極堆疊包含：一第一閘極介電質，在該第一隔離區上方，且在該第二隔離區的側壁上；以及一第一閘電極，在該第一閘極介電質上方。
  9. 如請求項8所述之裝置，其中該第一閘電極設置在該第一鰭片與該第二隔離區之間。
  10. 一種用於製造半導體裝置的方法，該方法包含：形成一第一鰭片於一基板之一第一區域中，並形成一第二鰭片於該基板之一第二區域中；形成一第一隔離區於該基板上，該第一隔離區圍繞該第一鰭片及該第二鰭片；形成虛設閘極材料於該第一鰭片及該第二鰭片上方；形成一凹口於該虛設閘極材料中；形成一犧牲氧化物於該虛設閘極材料的側壁上的該凹口中；充填一絕緣材料於該虛設閘極材料的所述側壁上的該犧牲氧化物之間的該凹口中；移除該虛設閘極材料及該犧牲氧化物的剩餘部分；以及形成替換閘極於該第一鰭片及該第二鰭片上方。
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