CN108807181B - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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CN108807181B
CN108807181B CN201710755358.9A CN201710755358A CN108807181B CN 108807181 B CN108807181 B CN 108807181B CN 201710755358 A CN201710755358 A CN 201710755358A CN 108807181 B CN108807181 B CN 108807181B
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fin
gate
forming
dummy gate
sidewalls
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CN108807181A (zh
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范家声
杨宝如
谢东衡
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
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Abstract

一种半导体装置及其制造方法。该方法包括：形成第一鳍片及第二鳍片于基板上；形成虚设栅极材料于第一鳍片及第二鳍片上方；形成凹口于第一鳍片与第二鳍片之间的虚设栅极材料中；形成牺牲氧化物于凹口中的虚设栅极材料的侧壁上；充填绝缘材料于虚设栅极材料的侧壁上的牺牲氧化物之间的凹口中；移除虚设栅极材料及牺牲氧化物；以及形成第一替换栅极于第一鳍片上方，并形成第二替换栅极于第二鳍片上方。

Description

半导体装置及其制造方法
技术领域
本揭示的实施方式是关于一种半导体装置及其制造方法。
背景技术
半导体装置用于各种电子应用中，例如个人电脑、手机、数字相机、及其他电子设备。半导体装置的制造通常通过依序地在半导体基板上方沉积绝缘层或介电层、导电层及半导体层，并使用微影制程及蚀刻制程对各材料层进行图案化，以在其上形成电路部件及元件。
半导体工业通过持续减小最小特征尺寸来持续改进各电子部件(例如，晶体管、二极管、电阻器、电容器等)的整合密度，此允许更多部件整合在给定区域中。然而，随着最小特征尺寸减小，在所使用的每个制程内出现额外问题，且应解决彼等额外问题。
发明内容
本揭示提供一种用于制造半导体装置的方法，此方法包括形成第一鳍片及第二鳍片于基板上；形成虚设栅极材料于第一鳍片及第二鳍片上方；形成凹口于第一鳍片与第二鳍片之间的虚设栅极材料中；形成牺牲氧化物于凹口中的虚设栅极材料的侧壁上；充填绝缘材料于凹口中的虚设栅极材料的侧壁上的牺牲氧化物之间；移除虚设栅极材料及牺牲氧化物；以及形成第一替换栅极于第一鳍片上方，并形成第二替换栅极于第二鳍片上方。
在其他实施方式中，本揭示提供一种半导体装置，此半导体装置包括第一鳍片在基板上；第二鳍片在基板上，第二鳍片及第一鳍片具有平行纵轴；第一隔离区，围绕第一鳍片及第二鳍片；第一栅极堆叠，在第一鳍片上方；第二栅极堆叠，在第二鳍片上方；以及第二隔离区，设置在第一隔离区上方及在第一栅极堆叠与第二栅极堆叠之间，第二隔离区具有平行于第一鳍片及第二鳍片的纵轴的纵轴。
在其他实施方式中，本揭示提供一种用于制造半导体装置的方法，此方法包括形成第一鳍片于基板的第一区域中，并形成第二鳍片在基板的第二区域中；形成第一隔离区于基板上，第一隔离区围绕第一鳍片及第二鳍片；形成虚设栅极材料于第一鳍片及第二鳍片上方；形成凹口于虚设栅极材料中；形成牺牲氧化物于虚设栅极材料的侧壁上的凹口中；充填绝缘材料于虚设栅极材料的侧壁上的牺牲氧化物之间的凹口中；移除虚设栅极材料及牺牲氧化物的剩余部分；以及形成替换栅极于第一鳍片及第二鳍片上方。
附图说明
当结合附图阅读时，自以下详细描述可以最佳地理解本揭示的态样。应当注意，根据工业中标准实务，各特征未按比例绘制。事实上，为论述的清楚性，各特征的尺寸可任意地增加或缩小。
图1是绘示根据一些实施方式的三维视图中的鳍式场效晶体管(FinFET)的实施例；
图2至图19C是根据一些实施方式的FinFET制造中间阶段的横截面及平面图。
具体实施方式
以下揭示提供许多不同实施方式或实施例，以实现本揭示的不同的特征。下文描述部件及排列的特定的实施例以简化本揭示。当然，此等仅为实施例而非用以作为限制。举例而言，在随后描述中在第二特征上方或在第二特征上第一特征的形成可包括第一特征及第二特征形成为直接接触的实施方式，亦可包括有另一特征可形成在第一及第二特征之间，使得第一及第二特征可不直接接触的实施方式。另外，本揭示可在各实施例中重复元件符号及/或字母。此重复为出于简化及清楚的目的，且本身不指示所论述的各实施方式及/或结构之间的关系。
另外，于此使用的空间相对术语，例如“之下”、“下方”、“下部”、“上方”、“上部”及类似用语，是为了便于描述图示中的一个元件或特征与另一元件(或多个元件)或特征(或多个特征)的关系。这些空间性相对用词本意上涵盖除了图中所绘示的位向之外，也涵盖使用或操作中的装置的不同位向。装置也可被转换成其他位向(旋转90度或其他位向)，因此本文中使用的空间性相对描述应做类似的解释。
根据各实施方式提供了半导体装置及其形成方法。详言之，隔离区形成于FinFET装置的邻近栅极之间。在一后栅极制程中，形成FinFET装置，且在中间制造阶段中，由多晶硅形成虚设栅极。凹部形成于相邻鳍片之间的虚设栅极中，且虚设栅极的暴露侧壁经氧化以形成牺牲氧化物。以绝缘材料充填凹口，形成隔离区。移除虚设栅极及牺牲氧化物，并以金属栅极替换。在形成隔离区后且形成金属栅极前，牺牲氧化物的形成增加了隔离区与金属栅极之间的间隙填充距离。因此，当形成金属栅极时，可减少隔离区与金属栅极之间的孔洞及凹坑的形成。
图1绘示在三维视图中的FinFET的实施例。FinFET包括鳍片56，鳍片56位于基板50上。基板50包括隔离区54，且鳍片56从相邻的隔离区54之间突出于上方。栅极介电质102是位于鳍片56的顶表面上，且沿着鳍片56的侧壁，而栅电极104位于栅极介电质102之上。源极区/漏极区82设置于鳍片56的侧边中，对向于栅极介电质102及栅电极104。图1进一步绘示在后续图中所使用的参考横截面及参考线。横截面A-A横跨FinFET的通道、栅极介电质102及栅电极104。横截面B-B垂直于横截面A-A，沿着鳍片56的纵轴，举例而言，并位于源极区/漏极区82之间的电流流动方向上。为清晰起见，后续图参考遵循这些参考横截面。
图2至图5是根据一些实施方式的FinFET制造中间阶段的横截面图。图2至图5是沿着图1的横截面A-A进行绘示，除了多个FinFET外。
图2中提供基板50。基板50可以是半导体基板，例如块状半导体(bulksemiconductor)、绝缘体上半导体(semiconductor-on-insulator,SOI)基板或其类似基板，其可以是有经过掺杂(例如，掺杂p型杂质或n型杂质)或无掺杂的。基板50可以是晶圆，例如硅晶圆。一般而言，SOI基板是形成在绝缘层上的半导体材料层。举例而言，绝缘层可以是内埋式氧化物(buried oxide,BOX)层、氧化硅层或其类似层。绝缘层设置在基板上，通常为硅基板或玻璃基板。亦可使用其他基板，例如多层基板或梯度基板(gradientsubstrate)。在一些实施方式中，基板50的半导体材料可包括硅、锗、化合物半导体、合金半导体或其组合，化合物半导体包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟及/或锑化铟，合金半导体包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP。
基板50具有第一区域50B及第二区域50C。第一区域50B可用于形成n型装置，例如n型金属-氧化物-半导体(n-type metal-oxide-semiconductor,NMOS)场效晶体管，n型FinFET即为一例。第二区域50C可用于形成p型装置，例如p型金属-氧化物-半导体(p-typemetal-oxide-semiconductor,PMOS)场效晶体管，p型FinFET即为一例。在一些实施方式中，第一区域50B与第二区域50C皆用于形成相同类型的装置，举例而言，这两个区域均用于n型装置或均用于p型装置。
在图3中，鳍片52形成于基板50中。鳍片52是条状半导体。在一些实施方式中，可通过在基板50中蚀刻沟槽，从而在基板50中形成鳍片52。蚀刻可以是任何合适的蚀刻制程，例如活性离子蚀刻(reactive ion etch,RIE)、中性束蚀刻(neutral beam etch,NBE)、其类似制程或其一组合。蚀刻可以是各向异性的。鳍片52可以具有各自平行的纵轴。
在图4中，绝缘材料54形成于相邻的鳍片52之间，以形成隔离区54。绝缘材料54可为氧化物，例如氧化硅、氮化物、其类似物或其一组合，并可通过高密度等离子化学气相沉积(high density plasma chemical vapor deposition,HDP-CVD)、流动化学气相沉积(flowable CVD,FCVD)(例如，在远程等离子系统中基于化学气相沉积的材料沉积及后续固化，以使其转换为另一材料，例如氧化物)、其类似制程等或其一组合来形成。可使用由任何合适的制程所形成的其他绝缘材料。在所绘示的实施方式中，绝缘材料54是通过流动化学气相沉积(FCVD)制程所形成的氧化硅。一旦形成绝缘材料后，可施予退火制程。绝缘材料54可称作隔离区54。另外在图4中，平坦化制程，例如化学机械研磨(chemical mechanicalpolish,CMP)，可移除任何多余的绝缘材料54，并形成隔离区54的顶表面及鳍片52的顶表面，隔离区54的顶表面及鳍片52的顶表面是对齐的。
在图5中，隔离区54内凹以形成浅沟槽隔离区(Shallow Trench Isolation,STI)54。隔离区54内凹而使得第一区域50B及第二区域50C中的鳍片56从相邻的隔离区54之间突出。此外，隔离区54的顶表面可具有如图所示的平坦表面、也可具有凸表面、凹表面(例如凹陷)或其一组合。可通过合适的蚀刻来形成平面、凸面及/或凹面的隔离区54顶表面。可使用合适的蚀刻制程使隔离区54内凹，例如对隔离区54的材料具有选择性的蚀刻制程。例如使用
Figure BDA0001392044830000051
蚀刻、应用材料SICONI(Applied Material SICONI)工具或稀释的氢氟酸(dilute hydrofluoric acid,dHF)的化学氧化物移除。
所属技术领域中具有普通技能者将易于理解的是，图2至图5所描述的制程仅是如何可形成鳍片56的一个实施例。在一些实施方式中，介电层可形成于基板50的顶表面上方；可穿过介电层蚀刻沟槽；同质磊晶结构可在沟槽中磊晶生长；且可内凹介电层，使得同质磊晶结构从介电层突出，以形成鳍片。在一些实施方式中，同质磊晶结构可用于鳍片52。举例而言，可内凹图4中的鳍片52，其位置中可磊晶生长不同于鳍片52的材料。在又一实施方式中，介电层可形成于基板50的顶表面上方；可穿过介电层蚀刻沟槽；可使用与基板50不同的材料，在沟槽中磊晶生长同质磊晶结构；且可内凹介电层，使得同质磊晶结构从介电层突出，以形成鳍片56。在磊晶生长同质磊晶或异质磊晶结构的一些实施方式中，在生长期间，可原位掺杂生长材料，这可避免预先植入和后续植入，尽管可同时使用原位掺杂及植入掺杂。更进一步而言，这有利于在NMOS区域中磊晶生长不同于PMOS区域中的材料。在各实施方式中，鳍片56可由硅锗(SixGe1-x，其中x可介于约0与1之间)、碳化硅、纯或基本上纯的锗、III价-V价化合物半导体、II价-VI价化合物半导体或其类似物所形成。举例而言，可用于形成III价-V价化合物半导体的材料包括但不限于InAs、AlAs、GaAs、InP、GaN、InGaAs、InAlAs、GaSb、AlSb、AlP、GaP及其类似材料。
另外在图5中，可在鳍片56、鳍片52及/或基板50中形成合适的井(未图示)。在一些实施方式中，可在第一区域50B中形成P井，并可在第二区域50C中形成N井。在一些实施方式中，第一区域50B及第二区域50C中皆形成P井或N井。
在具有不同井类型的实施方式中，使用光阻或其他遮罩(未图示)可达成在第一区域50B及第二区域50C的不同植入步骤。举例而言，在第一区域50B中，光阻可形成于鳍片56及隔离区54上方。对光阻作图案化，以暴露基板50的第二区域50C，例如PMOS区域。可通过使用旋涂技术来形成光阻，并可使用合适的光刻方法而图案化。一旦将光阻图案化后，在第二区域50C中施予n型杂质的植入，且光阻可充当遮罩，以便基本上防止n型杂质被植入到第一区域50B中，例如NMOS区域。n型杂质可以是磷、砷、或植入在第二区域中的类似物，其浓度等于或小于1018cm-3，例如介于约1017cm-3与约1018cm-3之间。在植入之后移除光阻，例如通过合适的灰化制程。
在第二区域50C的植入后，在第二区域50C中，光阻形成于鳍片56及隔离区54上。对光阻作图案化，以暴露基板50的第一区域50B，例如NMOS区域。可通过使用旋涂技术来形成光阻，并可使用合适的光刻方法来将光阻图案化。一旦将光阻图案化后，可在第一区域50B中施予p型杂质的植入，且光阻可充当遮罩，以便基本上防止p型杂质被植入到第二区域50C中，例如PMOS区域。p型杂质可以是硼、BF2、或植入在第一区域中的类似物，其浓度等于或小于1018cm-3，例如介于约1017cm-3与约1018cm-3之间。在植入之后可移除光阻，例如通过合适的灰化制程。
在第一区域50B及第二区域50C的植入后，可施予退火，以活化被植入的p型杂质及/或n型杂质。在一些实施方式中，在生长期间，可原位掺杂磊晶鳍片的生长材料，这可避免植入，尽管原位掺杂及植入掺杂是可以同时使用的。
图6A至图19C是根据一些实施方式的更进一步的FinFET制造中间阶段的横截面图及平面图。在图6A至图19C中，图示标号以“A”结尾的图是沿着图1的横截面A-A来绘示，除了多个FinFET之外。而图示标号以“B”结尾的图是沿着图1的横截面B-B来绘示，任第一区域50B或第二区域50C，皆可表示FinFET。图示标号以“C”结尾的图是相对于各横截面图中的C-C线来绘示的平面图。
在图6A及图6B中，虚设介电层58形成于鳍片56上。举例而言，虚设介电层58可以是氧化硅、氮化硅、其一组合或其类似物，且可根据合适的方法沉积或热生长。在一些实施方式中，虚设介电层58保形地形成在鳍片56及隔离区54上方。在一些实施方式(未图示)中，虚设介电层58仅形成在鳍片56的顶表面上及侧壁上，并没有形成在隔离区54上方。
进一步地，在图6A及图6B中，虚设栅极层60形成在虚设介电层58上方。虚设栅极层60可沉积在虚设介电层58上方，随后进行平坦化，例如通过化学机械研磨(CMP)。虚设栅极层60可以是导电材料，且可选自包括多晶硅(复晶硅)、多晶硅锗(poly-crystallinesilicon-germanium,poly-SiGe)、金属氮化物、金属硅化物、金属氧化物及金属的一群组。在一个实施方式中，沉积及再结晶非晶硅，以产生多晶硅。可通过物理气相沉积、化学气相沉积、溅射沉积或导电材料沉积技术中已知及已使用的其他方法来沉积虚设栅极层60。虚设栅极层60可由其他材料制成，这些材料是对隔离区的蚀刻具有高蚀刻选择性。
进一步地，在图6A及图6B中，遮罩层62形成在虚设栅极层60上方。遮罩层62可沉积在虚设栅极层60上方。遮罩层62可由介电质形成，举例而言，可包括SiN、SiON或其类似物。
在此实施例中，单虚设栅极层60及单遮罩层62形成且横跨第一区域50B及第二区域50C。在一些实施方式中，分隔的虚设栅极层可形成在第一区域50B及第二区域50C中，而分隔的遮罩层可形成在第一区域50B及第二区域50C中。
在图7A及图7B中，可使用合适的光刻及蚀刻技术来对遮罩层62图案化，以形成遮罩72。可通过合适的蚀刻技术，来将遮罩72的图案转移至虚设栅极层60及虚设介电层58，以形成虚设栅极70。虚设栅极70覆盖鳍片56各别的通道区。虚设栅极70亦可具有一个纵向方向，此纵向方向基本上垂直于各别磊晶鳍片的纵向方向。
进一步地，在图7A及图7B中，栅极密封间隔层80可形成在虚设栅极70、遮罩72及/或鳍片56的暴露表面上。热氧化或沉积，伴随各向异性蚀刻可形成栅极密封间隔层80。
在形成栅极密封间隔层80之后，可对轻度掺杂的源极区/漏极区(Lightly dopedsource/drain,LDD)(未图示)施予植入。在不同装置类型的实施方式中，遮罩可形成于第一区域50B上方，例如光阻，类似于上述图5中的植入，同时暴露第二区域50C，且在第二区域50C中，合适类型的杂质(例如n型或p型)可被植入到暴露鳍片56中。随后可移除遮罩。接下来，遮罩可形成于第二区域50C上方，例如光阻，同时暴露第一区域50B，且在第一区域50B中，合适类型的杂质可被植入到暴露鳍片56中。随后可移除遮罩。n型杂质可以是任一上述n型杂质，且p型杂质可以是任一上述p型杂质。轻度掺杂的源极区/漏极区可具有约1015cm-3至约1016cm-3的杂质浓度。退火可用以活化所植入的杂质。
在图8A及图8B中，磊晶源极区/漏极区82形成于鳍片56中。磊晶源极区/漏极区82形成于鳍片56中，使得每个虚设栅极70设置在一对对相邻的磊晶源极区/漏极区82之间。在一些实施方式中，磊晶源极区/漏极区82可延伸入鳍片52中。
在第一区域50B中，例如NMOS区域，其内的磊晶源极区/漏极区82的形成，可通过遮蔽第二区域50C，例如PMOS区域，并且在第一区域50B中保形地沉积虚设间隔层，随后进行各向异性蚀刻，以沿着第一区域50B中的虚设栅极70的侧壁，及/或栅极密封间隔层80的侧壁，形成虚设栅极间隔层(未图示)。接下来，蚀刻第一区域50B中的磊晶鳍片的源极区/漏极区，以形成凹口。第一区域50B中的磊晶源极区/漏极区82在凹口中进行磊晶生长。磊晶源极区/漏极区82可包括任一合适的材料，例如适用于n型FinFET的材料。举例而言，若鳍片56为硅，磊晶源极区/漏极区82可包括硅、SiC、SiCP、SiP或其类似物。磊晶源极区/漏极区82可以具有从鳍片56个别表面升起的表面，且可具有小面。接下来，移除第一区域50B中的虚设栅极间隔层，例如通过蚀刻，如同第二区域50C上的遮罩。
在第二区域50C中，例如PMOS区域，其内的磊晶源极区/漏极区82的形成，可通过遮蔽第一区域50B，例如NMOS区域，并且在第二区域50C中保形地沉积虚设间隔层，随后进行各向异性蚀刻，以沿着第二区域50C中的虚设栅极70的侧壁，及/或栅极密封间隔层80的侧壁，形成虚设栅极间隔层(未图示)。接下来，蚀刻第二区域50C中的磊晶鳍片的源极区/漏极区，以形成凹口。第二区域50C中的磊晶源极区/漏极区82在凹口中进行磊晶生长。磊晶源极区/漏极区82可包括任一合适的材料，例如适用于p型FinFET的材料。举例而言，若鳍片56为硅，磊晶源极区/漏极区82可包括SiGe、SiGeB、Ge、GeSn或其类似物。磊晶源极区/漏极区82可具有自鳍片56个别表面升起的表面，且可具有小面。接下来，移除第二区域50C中的虚设栅极间隔层，例如通过蚀刻，如同第一区域50B上的遮罩。
在图9A及图9B中，栅极间隔层86形成在沿着虚设栅极70及遮罩72的侧壁的栅极密封间隔层80上。可通过保形地沉积材料，随后对此材料进行各向异性地蚀刻，以形成栅极间隔层86。栅极间隔层86的材料可以是介电材料，例如氮化硅、SiCN、其一组合或其类似物。
磊晶源极区/漏极区82及/或磊晶鳍片可被植入杂质，以形成源极区/漏极区，类似于上述用于形成轻度掺杂的源极区/漏极区，随后进行退火的制程。源极区/漏极区可具有介于约1019cm-3至约1021cm-3之间的杂质浓度。源极区/漏极区的n型杂质及/或p型杂质可以是前述杂质的任一者。在一些实施方式中，在生长期间，可原位掺杂磊晶源极区/漏极区82。
在图10A及图10B中，层间介电层88(interlayer dielectric,ILD)沉积在图9A及图9B中所示的结构上。层间介电层88可由介电材料或半导体材料形成，及可通过任一合适方法，例如化学气相沉积、等离子增强化学气相沉积(plasma-enhanced CVD,PECVD)或流动化学气相沉积(FCVD)而沉积。介电材料可包括磷酸硅酸盐玻璃(Phospho-Silicate Glass,PSG)、硼硅酸盐玻璃(Boro-Silicate Glass,BSG)、硼掺杂磷酸硅酸盐玻璃(Boron-DopedPhospho-Silicate Glass,BPSG)、无掺杂硅酸盐玻璃(undoped Silicate Glass,USG)或其类似物。半导体材料可包括非晶硅、硅锗(SixGe1-x，其中x可介于约0与1之间)、纯锗或其类似物。可使用由任一合适制程形成的其他绝缘材料或半导体材料。
在图11A及图11B中，可施予平坦化制程，例如化学机械研磨(CMP)，以使得层间介电层88的顶表面与虚设栅极70的顶表面对齐。此平坦化制程亦可移除虚设栅极70上的遮罩72、部分的栅极密封间隔层80及部分的栅极间隔层86。在平坦化制程之后，虚设栅极70、栅极密封间隔层80、栅极间隔层86及层间介电层88的顶表面对齐。因此，虚设栅极70的顶表面穿过层间介电层88而暴露。
在图12A及图12B中，遮罩层90，例如硬遮罩，沉积在图11A及图11B所示的结构上。遮罩层90可由SiN、SiON、SiO2、其类似物或其组合制造得到。遮罩层90可通过化学气相沉积、物理气相沉积、原子层沉积(Atomic layer deposition,ALD)、旋涂介电制程(spin-on-dielectric process)、其类似制程或其一组合而形成。
在图13A及图13B中，光阻92在遮罩层90上形成并被图案化。在一些实施方式中，光阻92可通过旋涂技术来形成，且可使用合适的光刻技术而被图案化。在图案化光阻92之后，可在光阻92上执行修整制程，以减少图案化后光阻92的宽度。在一实施方式中，修整制程是一个各向异性等离子蚀刻制程，具有包括O2、CO2、N2/H2、H2、其类似气体、其一组合、或适用于修整光阻的任何其他气体的制程气体。
在一些实施方式中，光阻92为三层光阻。在这些实施方式中，三层光阻92包括顶端光阻层、中间层及底层。随着高阶半导体制程已达到光刻制程的极限，产生了更薄的顶端光阻层的需求，以获到更小的制程窗口。然而，薄的顶端光阻层的稳固性可能不足以支持标的层(例如遮罩层90)的蚀刻。三层光阻提供了相对薄的顶端光阻层。中间层可包括抗反射材料(例如，背侧抗反射涂层(backside anti-reflective coating,BARC))以辅助顶端光阻层的制程的暴露及聚焦。通过具有中间层，薄的顶端光阻层仅用以图案化中间层。底层可包括硬遮罩材料，例如可通过O2或N2/H2等离子而轻易移除的含碳材料。中间层是用以图案化底层。在一些实施方式中，中间层具有对底层的高蚀刻选择性，以及在一些实施方式中，底层的厚度比中间层的厚度高出十倍以上。因而，三层光阻92成功使得其下方层(例如，遮罩层90)稳定地图案化，同时仍然提供相对薄的顶端光阻层。
三层光阻92的顶端光阻层可使用任一合适的光刻技术而图案化。举例而言，光遮罩(未图示)可设置在顶端光阻层上方，其随后可暴露于辐射束，此辐射束包括紫外线(UV)或准分子激光，例如来自氟化氪(KrF)248纳米光束的准分子激光、来自氟化氩(ArF)193纳米光束的准分子激光、或来自F2 157纳米光束的准分子激光。进行顶端光阻层的暴露时，可使用浸入微影系统，以增大解析度及减小最小可获得的间距。可进行烘烤或固化操作，以硬化顶端光阻层，且可根据所使用的显影剂是正抗蚀剂还是负抗蚀剂，以移除顶端光阻层的暴露部分或未暴露部分。在图案化三层光阻92的顶端光阻层之后，可执行修整制程，以减少三层光阻92的顶端光阻层的宽度。在一实施方式中，修整制程是一个各向异性等离子蚀刻制程，具有包括O2、CO2、N2/H2、H2、其类似气体、其一组合、或适用于修整光阻的任何其他气体的制程气体。在修整制程之后，可图案化中间层及底层，以留下图案化的三层光阻92，如图13A及图13B所绘示。
在图14A、图14B及图14C中，使用光阻92作为遮罩，图案化遮罩层90及虚设栅极70。可使用任一合适蚀刻制程来执行遮罩层90的图案化，例如各向异性干蚀刻制程。可持续蚀刻制程，以图案化虚设栅极70。在一些实施方式中，可通过蚀刻制程来移除部分虚设介电层58。此图案化形成开口94，开口94分隔第一区域50B中的鳍片56与第二区域50C中的鳍片56。隔离区54的顶表面可由开口94而暴露。接下来移除光阻92。
开口94由隔离区54的暴露表面、虚设栅极70剩余部分的侧壁70S、以及栅极间隔层86的内表面而界定。在一些实施方式中，虚设栅极70剩余部分的侧壁70S相对倾斜于基板50的主要表面。换言之，虚设栅极70剩余部分的侧壁70S不平行于且不垂直于基板50的主要表面。在一些实施方式中，虚设栅极70剩余部分的侧壁70S与平行于基板50的主要表面的平面形成角度θ1。在一实施方式中，角度θ1大于约90°，例如介于约92°至约97°的范围中。另外，从垂直于鳍片56的纵轴的方向上量测，开口94与隔离区54的交界面处(例如，开口94的底部)比开口94的顶端更狭窄，使得开口94自顶端向底部逐渐变细。另外在平面图中，开口94具有哑铃形状。结果，开口94的第一宽度W1小于开口94的第二宽度W2，开口94的第一宽度W1位于远离栅极间隔层86的中心部分内，开口94的第二宽度W2位于靠近栅极间隔层86的边缘部分内。
在图15A、图15B及图15C中，牺牲氧化物96形成于开口94内虚设栅极70的暴露侧壁上。牺牲氧化物96是虚设栅极70的材料的氧化物，例如可以是原生氧化物、等离子氧化物或其类似氧化物。牺牲氧化物96可以是类似于虚设介电层58，或可以是不同的。可使用氧化制程来形成牺牲氧化物96，例如热氧化制程、快速热氧化制程(rapid thermal oxidation,RTO)、化学氧化制程、临场蒸气产生制程(ISSG)或增强临场蒸气产生制程(EISSG)。举例而言，可在含氧环境中施予快速热退火(rapid thermal anneal,RTA)。热氧化可在约800℃至约1100℃的温度下进行，例如约800℃。温度可有助于牺牲氧化物96的厚度；较高的温度可产生较厚的牺牲氧化物96。施予热氧化的时间跨度为约10秒至约20秒，例如约15秒。时间跨度亦可有助于牺牲氧化物96的厚度；较长的氧化时间跨度可产生较厚的牺牲氧化物96。在完成后，热氧化可形成厚度为约
Figure BDA0001392044830000111
至约
Figure BDA0001392044830000112
的牺牲氧化物96，例如约
Figure BDA0001392044830000113
在一些实施方式中，可施予其他氧化制程。氧化制程可仅氧化虚设栅极70的材料，使得牺牲氧化物96仅形成在虚设栅极70的侧壁上，并不形成在遮罩层90上。
在图16A、图16B及图16C中，绝缘材料形成在开口94中，以形成隔离区98。隔离区98提供第一区域50B中的虚设栅极70与第二区域50C中的虚设栅极70之间的隔离。绝缘材料可以是氧化物，例如氧化硅、氮化物、其类似物或其一组合，并可通过高密度等离子化学气相沉积(high density plasma chemical vapor deposition,HDP-CVD)、流动化学气相沉积(FCVD)(例如在远程等离子系统及后固化中，基于化学气相沉积的材料沉积，以使其转变为另一材料，例如氧化物)、其类似制程或其一组合而形成。可以使用通过任一合适制程所形成的其他绝缘材料。隔离区98的绝缘材料可与绝缘材料54是相同的，也可以是不同的。在所示的实施方式中，绝缘材料为氮化硅。在形成隔离区98后，隔离区98被夹在牺牲氧化物96之间，牺牲氧化物96是形成于开口94的各别侧壁上。由SiN形成隔离区98的实施方式中，形成于开口94中的结构可称为氧化物-SiN-氧化物夹层结构，或更一般地可称为氧化物-氮化物-氧化物夹层结构。
隔离区98的形状是由开口94所界定，例如隔离区54的暴露表面、虚设栅极70的暴露侧壁及栅极间隔层86的暴露侧壁。换言之，隔离区98可具有的形状类似于开口94的形状。因而，隔离区98底部的宽度可小于隔离区98顶部的宽度(例如图16A)，且在平面图中(例如图16C)，隔离区98可具有哑铃形状。隔离区98的纵轴平行于鳍片56的纵轴。位于相邻的栅极间隔层86之间的隔离区98的侧壁与一平面有角度θ1，此平面平行于基板50的主要表面，类似于虚设栅极70剩余部分的对应侧壁70S。另外在俯视图中，虚设栅极70剩余部分的侧壁70S不是平面，而是凸出的，而在俯视图中，隔离区98是较宽的。在俯视图中，隔离区98具有哑铃形状。隔离区包括具有第一宽度W1的中间部分98S1，及具有第二宽度W2的边缘部分98S2。边缘部分98S2接触相邻的栅极间隔层86的侧壁，而中间部分98S1在边缘部分98S2之间延伸。
在图17A、图17B及图17C中，在蚀刻步骤中，移除牺牲氧化物96、栅极密封间隔层80、直接位于暴露虚设栅极70下方的部分虚设介电层58、以及虚设栅极70的剩余部分，以形成凹口100。在一些实施方式中，通过各向异性干蚀刻制程来移除虚设栅极70。举例而言，蚀刻制程可包括干蚀刻制程，干蚀刻制程使用的反应气体选择性地蚀刻虚设栅极70，而不蚀刻隔离区98、层间介电层88或栅极间隔层86。每个凹口100暴露各别鳍片56的通道区。每个通道区设置在相邻的每一对磊晶源极区/漏极区82之间。在移除期间，在蚀刻虚设栅极70时，虚设介电层58可用以作为蚀刻停止层。在移除虚设栅极70之后，接下来可移除虚设介电层58及栅极密封间隔层80。
可在用以移除虚设介电层58的相同蚀刻步骤中，移除牺牲氧化物96。所施予的蚀刻步骤可对牺牲氧化物96及/或虚设介电层58的材料具有选择性。移除牺牲氧化物96可增大位于隔离区98与鳍片56之间的间隙填充距离(gap fill distance,Dg)(有时称作“间隙填充窗口”)。在形成金属栅电极104(示于下文)时，可沿着隔离区98及鳍片56的侧壁形成金属。增大间隙填充窗口可改进用于金属填充的窗口，这可减少金属在沿每个侧壁形成时发生合并的机会。如此可避免在完成的FinFET装置中形成孔洞及凹坑。除了改进用于金属填充的窗口外，增大间隙填充窗口亦可改进蚀刻的窗口。间隙填充距离Dg可通过调整形成牺牲氧化物96的氧化制程参数来控制，从而控制牺牲氧化物96的厚度。
在图18A、图18B及图18C中，形成栅极介电层102及栅电极104以作为替换栅极。栅极介电层102保形地沉积在凹口100中，比如在鳍片56的侧壁及顶表面上、在栅极间隔层86的侧壁上，以及在层间介电层88的顶表面上。栅极介电层102可(或可没有)沉积在隔离区98的侧壁上。根据一些实施方式，栅极介电层102包括氧化硅、氮化硅或其多层。在其他实施方式中，栅极介电层102包括高介电常数介电材料，且在这些实施方式中，栅极介电层102可具有大于约7.0的介电常数值，并可包括Hf、Al、Zr、La、Mg、Ba、Ti、Pb及其组合的金属氧化物或硅酸盐。栅极介电层102的形成方法可包括分子束沉积(Molecular-Beam Deposition,MBD)、原子层沉积(ALD)、等离子增强化学气相沉积(PECVD)及其类似方法。
接下来，栅电极104分别沉积在栅极介电层102上方，并充填凹口100的剩余部分。栅电极104可包括含金属材料，例如TiN、TaN、TaC、Co、Ru、Al、其组合或其多层。在充填栅电极104之后，可执行平坦化制程，例如化学机械研磨(CMP)，以移除栅极介电层102的多余部分及栅电极104的材料，其多余部分位于层间介电层88及隔离区98的顶表面上方。在平坦化制程之后，隔离区98、栅极介电层102及栅电极104的顶表面是对齐的。所产生剩余部分的栅电极104及栅极介电层102因此形成了所得到的FinFET的替换栅极。替换栅极可统称为“栅极堆叠”或简单地称为“栅极”。
栅极介电层102的形成可同时发生，使得栅极介电层102包括相同材料，且栅电极104的形成可同时发生，使得栅电极104包括相同材料。然而，在其他实施方式中，栅极介电层102可由不同制程形成，使得栅极介电层102可包括不同材料，且栅电极104可由不同制程形成，使得栅电极104可包括不同材料。可使用各种遮蔽步骤，以便在使用不同制程时遮住及暴露合适的区域。
在形成替换栅极后，隔离区98将第一区域50B中的替换栅极与第二区域50C中具有相同纵轴的替换栅极分隔。隔离区98提供第一区域50B中的替换栅极与第二区域50C中的替换栅极之间的隔离。
在图19A、图19B及图19C中，层间介电层106沉积于层间介电层88上方，而接触点108及接触点110通过层间介电层106及层间介电层88而形成。层间介电层106形成于层间介电层88、替换栅极、栅极间隔层86及隔离区98的上方。层间介电层106由介电材料所形成，例如磷酸硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂磷酸硅酸盐玻璃(BPSG)、无掺杂硅酸盐玻璃(USG)或其类似材料，并可通过任一合适方法而沉积，例如化学气相沉积(CVD)及等离子增强化学气相沉积(PECVD)。接触点108及接触点110通过层间介电层88及层间介电层106，而形成开口。可使用合适的光刻技术及蚀刻技术来形成开口。开口中形成衬层及导电材料，衬层例如扩散阻障层(diffusion barrier layer)、粘附层或其类似物。衬层可包括钛、氮化钛、钽、氮化钽或其类似物。导电材料可以是铜、铜合金、银、金、钨、铝、镍或其类似物。可执行平坦化制程从层间介电层106表面移除多余的材料，例如化学机械研磨(CMP)。剩余的衬层及导电材料在开口中形成接触点108及接触点110。可执行退火制程，以分别在磊晶源极区/漏极区82与接触点108之间的界面形成硅化物。接触点108实体上及电性耦接至磊晶源极区/漏极区82。接触点110实体上及电性耦接至栅电极104。
尽管未明确绘示，然而所属技术领域中具有普通技能者将易于理解的是，可对图19A、图19B及图19C中的结构执行进一步的加工步骤。举例而言，可在层间介电层106上方形成各种金属间介电层(Inter-Metal Dielectrics,IMD)，以及他们相对应的金属化产物。
实施方式可得到一些优点。薄化鳍片之间的隔离区，可增大装置的间隙填充窗口及蚀刻窗口，这可避免在最后所形成的装置中形成孔洞及凹坑。增大间隙填充窗口使得能够使用多晶硅形成虚设栅极，而非其他材料。在形成虚设栅极层时，采用多晶硅而非金属的话，使得在替换虚设栅极时可减少层间介电层的损失量，可减少的损失量高达30nm。多晶硅虚设栅极可较易于替换，这是因为缩小了装置尺寸与接下来的栅极尺寸。
一实施方式包括一种方法。此方法包括：形成第一鳍片及第二鳍片于基板上；形成虚设栅极材料于第一鳍片及第二鳍片上方；形成凹口于第一鳍片与第二鳍片之间的虚设栅极材料中；形成牺牲氧化物于凹口中的虚设栅极材料的侧壁上；充填绝缘材料于凹口中的虚设栅极材料的侧壁上的牺牲氧化物之间；移除虚设栅极材料及牺牲氧化物；以及形成第一替换栅极于第一鳍片上方，并形成第二替换栅极于第二鳍片上方。
根据一些实施例，当中充填绝缘材料于侧壁上的牺牲氧化物之间，包含在侧壁上的牺牲氧化物之间形成氮化硅。
根据一些实施例，当中形成牺牲氧化物，包含氧化虚设栅极材料的侧壁。
根据一些实施例，当中氧化虚设栅极材料的侧壁，包含在自800℃至1100℃的温度下氧化侧壁。
根据一些实施例，当中氧化虚设栅极材料的侧壁，包含氧化侧壁自10秒至20秒的时间跨度。
根据一些实施例，当中氧化虚设栅极材料的侧壁，包含将侧壁氧化至自
Figure BDA0001392044830000151
至
Figure BDA0001392044830000152
的厚度。
根据一些实施例，当中在虚设栅极材料中形成凹口包含：形成具有第一宽度及第二宽度的凹口，第一宽度靠近基板，第二宽度远离基板，第二宽度大于第一宽度。
根据一些实施例，当中凹口在平面图中呈凸形。
根据一些实施例，当中进一步包含形成栅极间隔层，邻近于第一鳍片及第二鳍片上方的虚设栅极材料。
根据一些实施例，当中在虚设栅极材料中形成凹口包含：形成具有第一宽度及第二宽度的凹口，在平面图中，第一宽度靠近各个栅极间隔层，且在平面图中，第二宽度远离栅极间隔层，第一宽度大于第二宽度。
根据一些实施例，当中在第一鳍片上方形成第一替换栅极及在第二鳍片上方形成第二替换栅极包含：在第一鳍片与绝缘材料之间，以及在第二鳍片与绝缘材料之间形成金属。
一实施方式包括一种装置。此装置包括：第一鳍片在基板上；第二鳍片在基板上，第二鳍片及第一鳍片具有平行纵轴；第一隔离区，围绕第一鳍片及第二鳍片；第一栅极堆叠，在第一鳍片上方；第二栅极堆叠，在第二鳍片上方；以及第二隔离区，设置在第一隔离区上方，并位于第一栅极堆叠与第二栅极堆叠之间。
根据一些实施例，当中第二隔离区包含氮化硅。
根据一些实施例，当中第一隔离区及第二隔离区是不同的材料。
根据一些实施例，当中第一栅极堆叠包含：第一栅极介电质，在第一隔离区上方，且在第二隔离区的侧壁上；以及第一栅电极，在第一栅极介电质上方。
根据一些实施例，当中第一栅电极设置在第一鳍片与第二隔离区之间。
根据一些实施例，当中进一步包含邻近于第一栅极堆叠及第二栅极堆叠的栅极间隔层。
根据一些实施例，当中第二隔离区进一步设置在相邻的栅极间隔层之间。
根据一些实施例，当中第二隔离区具有靠近栅极间隔层的第一宽度，及远离栅极间隔层的第二宽度。
一实施方式包括一种方法。此方法包括：形成第一鳍片于基板的第一区域中，并形成第二鳍片在基板的第二区域中；形成第一隔离区于基板上，第一隔离区围绕第一鳍片及第二鳍片；形成虚设栅极材料于第一鳍片及第二鳍片上方；形成凹口于虚设栅极材料中；形成牺牲氧化物于虚设栅极材料的侧壁上的凹口中；充填绝缘材料于虚设栅极材料的侧壁上的牺牲氧化物之间的凹口中；移除虚设栅极材料及牺牲氧化物的剩余部分；以及形成替换栅极于第一鳍片及第二鳍片上方。
前文概述若干实施方式的特征，使得熟悉此项技术者可更好地理解本揭示案的态样。熟悉此项技术者应了解，他们可轻易使用本揭示作为设计或修改其他制程及结构的基础，以便实施与本揭示所介绍的实施方式相同的目的及/或实现相同优点。熟悉此项技术者亦应认识到，此类等效结构并未脱离本揭示的精神及范畴，且可在不脱离本揭示的精神及范畴的情况下于此作出各种变化、替代及更改。

Claims (17)

1.一种用于制造半导体装置的方法，其特征在于，该方法包含：
形成一第一鳍片及一第二鳍片于一基板上；
形成一虚设栅极材料于该第一鳍片及该第二鳍片上方；
图案化该虚设栅极材料以形成一虚设栅极；
形成多个栅极间隔层邻近于该第一鳍片及该第二鳍片上方的该虚设栅极；
在图案化该虚设栅极材料及形成该些栅极间隔层后，形成一凹口于该第一鳍片与该第二鳍片之间的该虚设栅极中；
形成一牺牲氧化物于该凹口中的该虚设栅极的侧壁上；
充填一绝缘材料于该凹口中的该虚设栅极的所述侧壁上的该牺牲氧化物之间；
移除该虚设栅极及该牺牲氧化物；
沉积一栅极介电层于该第一鳍片、该第二鳍片及该绝缘材料上；
形成一金属于该栅极介电层上；以及
平坦化该金属、该栅极介电层及该绝缘材料的多个顶表面以形成一第一替换栅极于该第一鳍片上方，并形成一第二替换栅极于该第二鳍片上方。
2.根据权利要求1所述的方法，其特征在于，充填该绝缘材料于所述侧壁上的该牺牲氧化物之间，包含在所述侧壁上的该牺牲氧化物之间形成氮化硅。
3.根据权利要求1所述的方法，其特征在于，其中形成该牺牲氧化物，包含氧化该虚设栅极的所述侧壁。
4.根据权利要求3所述的方法，其特征在于，其中氧化该虚设栅极的所述侧壁，包含在自800℃至1100℃的一温度下氧化所述侧壁。
5.根据权利要求3所述的方法，其特征在于，其中氧化该虚设栅极的所述侧壁，包含氧化所述侧壁自10秒至20秒的一时间跨度。
6.根据权利要求3所述的方法，其特征在于，其中氧化该虚设栅极的所述侧壁，包含将所述侧壁氧化至自
Figure FDA0002991911940000021
至
Figure FDA0002991911940000022
的一厚度。
7.根据权利要求1所述的方法，其特征在于，在该虚设栅极中形成该凹口包含：
形成具有一第一宽度及一第二宽度的该凹口，该第一宽度靠近该基板，该第二宽度远离该基板，该第二宽度大于该第一宽度。
8.根据权利要求7所述的方法，其特征在于，其中该凹口在一平面图中呈一凸形。
9.根据权利要求1所述的方法，其特征在于，其中在该虚设栅极中形成该凹口包含：
形成具有一第一宽度及一第二宽度的该凹口，在一平面图中，该第一宽度靠近各个所述栅极间隔层，且在该平面图中，该第二宽度远离所述栅极间隔层，该第一宽度大于该第二宽度。
10.根据权利要求1所述的方法，其特征在于，平坦化该金属、该栅极介电层及该绝缘材料的该些顶表面包含：
在该第一鳍片与该绝缘材料之间，以及在该第二鳍片与该绝缘材料之间形成该金属的多个剩余部分。
11.一种半导体装置，其特征在于，该装置包含：
一第一鳍片，在一基板上；
一第二鳍片，在该基板上，该第二鳍片及该第一鳍片具有平行纵轴；
一第一隔离区，围绕该第一鳍片及该第二鳍片；
一第一栅极堆叠，在该第一鳍片上方；
一第二栅极堆叠，在该第二鳍片上方；
多个 栅极间隔层，邻近于该第一栅极堆叠及该第二栅极堆叠；以及
一第二隔离区，设置在该第一隔离区上方及在该第一栅极堆叠与该第二栅极堆叠之间，该第二隔离区具有平行于该第一鳍片及该第二鳍片的所述纵轴的一纵轴，
其中该第二隔离区包括具有一第一宽度的一中间部分、具有一第二宽度的一第一边缘部分及具有一第三宽度的一第二边缘部分，该第一边缘部分及该第二边缘部分分别接触相邻的该些栅极间隔层，该中间部分位于该第一边缘部分及该第二边缘部分之间，该第一宽度小于该第二宽度，且小于该第三宽度。
12.根据权利要求11所述的装置，其特征在于，该第二隔离区包含氮化硅。
13.根据权利要求11所述的装置，其特征在于，该第一隔离区及该第二隔离区是不同的材料。
14.根据权利要求11所述的装置，其特征在于，该第一栅极堆叠包含：
一第一栅极介电质，在该第一隔离区上方，且在该第二隔离区的侧壁上；以及
一第一栅电极，在该第一栅极介电质上方。
15.根据权利要求14所述的装置，其特征在于，该第一栅电极设置在该第一鳍片与该第二隔离区之间。
16.根据权利要求11所述的装置，其特征在于，其中该第二隔离区进一步设置在相邻的栅极间隔层之间。
17.一种用于制造半导体装置的方法，其特征在于，该方法包含：
形成一第一鳍片于一基板的一第一区域中，并形成一第二鳍片于该基板的一第二区域中；
形成一第一隔离区于该基板上，该第一隔离区围绕该第一鳍片及该第二鳍片；
形成虚设栅极材料于该第一鳍片及该第二鳍片上方；
沉积多个栅极间隔层沿着该虚设栅极材料的多个侧壁；
在沉积该些栅极间隔层后，形成一凹口于该虚设栅极材料中，该凹口暴露出该第一隔离区及该些栅极间隔层的多个侧壁；
形成一牺牲氧化物于该虚设栅极材料的侧壁上的该凹口中；
充填一绝缘材料于该虚设栅极材料的所述侧壁上的该牺牲氧化物之间的该凹口中；
移除该虚设栅极材料及该牺牲氧化物的剩余部分；以及
形成替换栅极于该第一鳍片及该第二鳍片上方。
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