CN110875252A - 半导体器件和制造半导体器件的方法 - Google Patents

半导体器件和制造半导体器件的方法 Download PDF

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CN110875252A
CN110875252A CN201910815947.0A CN201910815947A CN110875252A CN 110875252 A CN110875252 A CN 110875252A CN 201910815947 A CN201910815947 A CN 201910815947A CN 110875252 A CN110875252 A CN 110875252A
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dielectric
feature
fin
isolation
layer
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CN110875252B (zh
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吴以雯
李振铭
杨复凯
王美匀
张长昀
傅劲逢
王鹏
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种方法包括提供一种结构，该结构具有位于衬底上方并且总体沿第一方向纵向定向的第一和第二鳍，以及位于第一和第二鳍上方的源极/漏极(S/D)部件；形成覆盖S/D部件的层间介电(ILD)层；至少对S/D部件之间的区域实施第一蚀刻工艺，从而在ILD层中形成沟槽；在沟槽中沉积介电材料；实施第二蚀刻工艺以选择性地使介电材料凹进；并且实施第三蚀刻工艺以选择性地使ILD层凹进，从而形成暴露S/D部件的接触孔。本发明还涉及半导体器件和制造半导体器件的方法。

Description

半导体器件和制造半导体器件的方法
技术领域
本发明的实施例涉及半导体器件和制造半导体器件的方法。
背景技术
半导体集成电路(IC)行业经历了指数型增长。IC材料和设计中的技术进步已经产生了多代IC，其中，每一代都比上一代具有更小且更复杂的电路。在IC演变过程中，功能密度(即，每芯片区域的互连器件的数量)通常增加，而几何尺寸(即，使用制造工艺可产生的最小组件(或线))已经减小。这种按比例缩小工艺通常通过提高生产效率和降低相关成本来提供益处。这种按比例缩小也增加了处理和制造IC的复杂性。
在一些IC设计中，随着技术节点缩小而实现的一项进步是用金属栅极替换典型的多晶硅栅极，以通过减小部件尺寸来改善器件性能。形成金属栅极的一个工艺称为替换栅极或“后栅极”工艺，其中，金属栅极“后”制造，这允许减少后续工艺的数量，包括高温工艺，这必须在形成栅极之后实施。举例来说，金属栅极制造工艺可以包括金属栅极结构沉积以及随后的金属栅极结构切割工艺。然而，实现这种IC制造工艺存在挑战，特别是填充在金属栅极段之间用于隔离的介电材料可以延伸到源极/漏极(S/D)区域之间的层间介电(ILD)层中。在S/D接触件形成期间，介电材料的存在减少了S/D接触件接合区域并且增大了S/D接触电阻，这也恶化了器件集成。本发明的目的旨在解决该问题等。
发明内容
本发明的实施例提供了一种制造半导体器件的方法，包括：提供一种结构，所述结构具有：衬底；鳍，位于衬底上方并且总体沿第一方向纵向定向；源极/漏极(S/D)部件，位于所述鳍上方；第一介电层，覆盖所述S/D部件的顶面和侧壁；隔离部件，嵌入在所述第一介电层中，其中，所述隔离部件的顶面位于所述S/D部件之上；以及第二介电层，覆盖所述第一介电层和所述隔离部件；实施第一蚀刻工艺以使所述第二介电层凹进以暴露所述隔离部件；实施第二蚀刻工艺以选择性地使所述隔离部件凹进；以及实施第三蚀刻工艺以使所述第一介电层凹进以暴露所述S/D部件。
本发明的另一实施例提供了一种制造半导体器件的方法，包括：在衬底上形成第一鳍和第二鳍，所述第一鳍和所述第二鳍具有栅极区域和源极/漏极(S/D)区域；在所述栅极区域中的所述第一鳍和所述第二鳍上方形成栅极结构；在所述第一鳍和所述第二鳍之间沉积介电层，所述介电层覆盖所述栅极结构的侧壁；实施蚀刻工艺以形成划分所述栅极结构的沟槽，所述沟槽延伸到所述第一鳍和所述第二鳍之间的所述介电层的区域中；用介电材料填充所述沟槽；选择性地蚀刻所述介电材料；选择性地蚀刻所述介电层；以及在所述S/D区域中的所述第一鳍和所述第二鳍的顶上沉积与介电材料直接接触的导电材料。
本发明的又一实施例提供了一种半导体器件，包括：衬底；鳍，从所述衬底突出；外延源极/漏极(S/D)部件，位于所述鳍上方；介电部件，与所述外延S/D部件相邻，其中，所述介电部件位于所述外延S/D部件的面向上的侧壁之下；以及导电部件，与所述外延S/D部件和所述介电部件直接接触。
附图说明
当结合附图进行阅读时，从以下详细描述可以最佳理解本发明的各个方面。应该强调，根据工业中的标准实践，各个部件未按比例绘制并且仅用于说明的目的。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1A示出了根据本发明的各个方面的利用切割金属栅极工艺实现的半导体结构的顶视图。
图1B、图1C和图1D示出了根据一些实施例的图1A中的结构的截面图。
图2A、图2B和图2C示出了根据本发明的各个方面的用于形成图1A至图1D中所示的结构的方法的流程图。
图3、图4A、图4B、图5A、图5B、图6A、图6B、图7A、图7B、图8A、图8B、图9A、图9B、图10A、图10B、图11A、图11B、图12、图13、图14、图15、图16、图17和图18示出了根据一些实施例的根据图2A至图2C的方法的制造工艺期间的半导体结构的截面图。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同部件的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可以在各个实施例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。器件可以以其他方式定向(旋转90度或在其他方位上)，而本文使用的空间相对描述符可以同样地作出相应的解释。此外，当用“约”、“近似”等描述数值或数值范围时，该术语旨在包括在所描述数值的+/-10％内的数值，除非另有说明。例如，术语“约5nm”包括从4.5nm至5.5nm的尺寸范围。
本发明总体涉及半导体器件和制造方法，并且更具体地涉及利用切割金属栅极工艺制造FinFET半导体器件，使用隔离材料以用于栅极段之间的隔离，以及随后通过选择性蚀刻工艺使保留在偏离栅极段的区域中(例如在S/D部件之间的ILD层中)的隔离材料凹进，这有利地扩大了S/D接触件接合区域并且降低了S/D接触电阻。
切割金属栅极(CMG)工艺是指制造工艺，其中，在金属栅极(例如高k金属栅极或HKMG)替换伪栅极结构(例如，多晶硅栅极)之后，切割金属栅极(例如，通过蚀刻工艺)以将金属栅极分成两个或更多栅极段。每个栅极段用作单个晶体管的金属栅极。之后将隔离材料填充到金属栅极的相邻部分之间的沟槽中。在本发明中，这些沟槽被称为切割金属栅极沟槽或CMG沟槽。为了确保金属栅极完全切割，CMG沟槽通常进一步延伸到相邻区域，诸如覆盖金属栅极的侧壁的ILD层。因此，填充CMG沟槽的隔离材料之后保留在ILD层中。隔离材料通常具有与金属栅极相同的高度，其可以高于相邻的S/D部件。在ILD层中产生S/D接触孔的蚀刻工艺可能相对于隔离材料不具有足够的蚀刻选择性，从而使得隔离材料从S/D接触孔突出。突出的隔离材料遮蔽相邻的S/D部件并且减小S/D接触件接合区域，从而使得形成在S/D接触孔中的S/D接触件可能无法有效地落在S/D部件上。
根据本发明的工艺流程包括至少CMG工艺和选择性蚀刻工艺，以使S/D接触孔中的隔离材料凹进。CMG工艺将金属栅极分成多个栅极段。选择性蚀刻工艺使隔离材料凹进在S/D部件的一定高度以下。通过利用该工艺流程，S/D部件的顶面和侧壁(诸如朝上的侧壁)在S/D接触孔中更好地暴露，这允许更大的S/D接触件接合区域和更小的S/D接触电阻，并且还扩大了S/D接触件形成的工艺窗口。
图1A示出了半导体器件(或半导体结构)100的顶视图。图1B示出了沿图1A的B-B线的器件100的截面图。图1D示出了沿图1A的C-C线的器件100的截面图。
参考图1A和图1B，器件100包括衬底102、从衬底102突出的包括鳍104a、104b、104c和104d(统称为鳍104)的多个鳍、位于衬底102上方和鳍104之间的隔离结构106，以及设置在鳍104和隔离结构106上方的包括栅极结构112a和112b(统称为栅极结构112)的多个栅极结构。
鳍104沿X方向纵向定向，并且沿垂直于X方向的Y方向彼此间隔开。每个鳍104可以设计为用于形成n型FinFET或p型FinFET。栅极结构112沿Y方向纵向定向并且沿X方向彼此间隔开。栅极结构112在鳍相应的沟道区域中接合鳍104a、104b、104c和104d，从而形成FinFET。
器件100还包括S/D部件162。S/D部件162是外延生长的半导体部件。在外延生长工艺期间，S/D部件162可以形成多个侧壁，诸如示出的实施例中的侧壁163a、163b和163c。取决于侧壁的法线方向，如果法线向上指向，则相应的侧壁被称为面向上的侧壁(例如侧壁163a)；如果法线向下指向，则相应的侧壁称为面向下的侧壁(例如侧壁163b)；如果法线总体水平指向，则相应的侧壁被称为垂直侧壁(例如侧壁163c)。S/D部件162在它们相应的S/D区域中设置在每个鳍104上。鳍104a和104b沿Y方向具有边缘至边缘间隔P1。在实施例中，P1的范围在从约20至约30nm，其小于传统的鳍配置从而使得鳍104a和104b的相应S/D部件162合并。
器件100还包括一个或多个介电层，诸如位于隔离结构106上方并且部分地设置在S/D部件162的侧壁上的接触蚀刻停止层(CESL)164、设置在隔离结构106上方的第一ILD层166，以及设置在第一ILD层166上方的第二ILD层180。器件100还包括形成在穿过ILD层180和166开口的接触孔中的一种或多种导电材料184，从而接合S/D部件162。
仍然参考图1A和图1B，器件100还包括沿X方向纵向布置的多个介电部件，包括介电部件114a和114b(统称为介电部件114)。在所示实施例中，介电部件114a设置在鳍104b和104c之间并且与栅极结构112a和112b相交，并且介电部件114b设置在鳍104c和104d之间并且与栅极结构112a(但不与栅极结构112b)相交。每个介电部件114填充在CMG沟槽中，并且因此将与其相交的栅极结构112隔离成至少两个部分(或称为栅极段)。因此，介电部件114也称为隔离部件114。在所示实施例中，介电部件114a和114b共同将栅极结构112a分成三个栅极段，并且介电部件114a进一步将栅极结构112b分成两个栅极段。
参考图1A和图1D，每个栅极结构112包括高k介电层108和位于高k介电层108上方的导电层110。导电层110包括一个或多个金属材料层。因此，每个栅极结构112也称为高k金属栅极(或HK MG)112。栅极结构112还可以包括位于高k介电层108下方的界面层(未示出)。在各个实施例中，每个介电部件114a和114b沿Y方向至少从栅极结构112的一个边缘扩展到栅极结构112的相邻边缘并且沿着Z方向从栅极结构112的顶面扩展到隔离结构106的顶部。在所示实施例中，介电部件114a和114b将栅极结构112a分成左、中和右部分。左部分接合两个鳍104a和104b以形成一个晶体管，中间部分接合鳍104c以形成另一晶体管，以及右部分接合鳍104d以形成又一晶体管。
参考图1B，介电部件114a和114b也延伸到偏离栅极结构112的区域。在所示实施例中，介电部件114a设置在鳍104b和104c的S/D部件162之间，并且介电部件114b设置在鳍104c和104d的S/D部件162之间。与图1D相比，图1D中介电部件114的底部延伸到隔离结构106中，而在图1B中，介电部件114的底部嵌入在第一ILD层166内。这是因为在CMG沟槽的形成期间选择蚀刻金属栅极结构112以及第一ILD层166的蚀刻剂在这些材料中可能具有不等的蚀刻速率，从而使得在CMG沟槽的不同位置处的不同蚀刻速率可以导致不同的蚀刻深度。换句话说，在一些实施例中，介电部件114的沿X方向的底面可以具有阶梯轮廓，其中，阶梯高度在从约2nm和约10nm之间的范围内。在一些实施例中，介电部件114的底面位于隔离结构106的顶面之上的间隙Δ为S/D区域中的介电部件114a的高度h0的约5％至约20％，如图1B所示。在一些可选实施例中，介电部件114的底部也可以延伸到隔离结构106中，如图1C所示。介电部件114的顶部从ILD层166突出并且侵入导电材料184的底面。设置在介电部件114的相对侧壁上的第一ILD层166可以具有相同的高度或不等的高度。在所示实施例中，设置在介电部件114的相对侧壁上的第一ILD层的水平面是不均匀的。在所示实施例中，设置在介电部件114a的左侧壁上的第一ILD层166低于右侧壁上的第一ILD层166，诸如高度差h1为S/D区域中的介电部件114a的高度h0的约10％至约60％，诸如在从约1nm至约5nm的范围内。这主要是由于S/D接触孔中的介电部件114a的左侧比右侧上的更宽开口的蚀刻加载效应，从而使得第一ILD层166在介电部件114a的左侧上比在其右侧上更多的凹进。
与图1D相比，其中介于栅极段之间的介电部件114的顶面与栅极结构112的顶面基本上共面，而在图1B中，介电部件114凹进在导电材料184下方。仍然参考图1B，在一些实施例中，介电部件114可以在Z方向上凹进至少50nm。在所示实施例中，每个凹进的介电部件114位于相邻S/D部件162的面向上的侧壁163a之下。通过使介电部件114凹进，面向上的侧壁163a将不会被遮蔽，这为导电材料184提供了更大的接合区域，以充分接触面向上的侧壁163a。在所示实施例中，面向下的侧壁163b的顶部也暴露，这提供了来自S/D部件162的侧面的额外接触区域。
在介电部件114中，可能存在高度差。在所示实施例中，介电部件114b高于介电部件114a，诸如在一些实施例中高度差H在从约10nm至约40nm的范围内。参考图1A，区域190示出了形成S/D接触孔的位置，并且之后在其中填充S/D接触部件的位置。介电部件114a延伸穿过整个S/D接触孔，其中，重叠区域表示为虚线框192。介电部件114b稍微延伸到S/D接触孔中，其中，小得多的重叠区域表示为虚线框194。因此，当通过接触孔施加蚀刻剂以选择性地蚀刻介电部件114a和114b时，介电部件114a具有更大的开口面积(虚线框192)以接收比介电部件114b(虚线框194)更多的蚀刻剂。此外，蚀刻副产物也更容易通过较大的开口区域消散。因此，介电部件114a比介电部件114b凹进得更快。
在一些实施例中，每个介电部件114可以低于相应的相邻S/D部件162的面向上的侧壁163a的最底部分，但是高于相应的面向下的侧壁163b的最底部分。在一些可选实施例中，每个介电部件114可以低于相应的相邻S/D部件162的面向下的侧壁163b的最底部分。在又一些可选实施例中，介电部件114a可以在相应的相邻S/D部件162的面向下的侧壁163b的最底部分之下并且介电部件114b高于面向下的侧壁163b的最底部分，但是低于面向上的侧壁163a的最底部分。
下面进一步描述器件100的组件。在本实施例中，衬底102是硅衬底。可选地，衬底102可以包括另一元素半导体，诸如锗；化合物半导体、包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和锑化铟；合金半导体，包括硅锗、磷砷化镓、磷化铝铟、砷化铝镓、砷化镓铟、磷化镓铟和磷砷化镓铟；或它们的组合。
鳍104可以包括一种或多种半导体材料，诸如硅、锗、碳化硅、砷化镓、磷化镓、磷化铟、砷化铟、锑化铟、硅锗、磷砷化镓、磷化铝铟、砷化铝镓、砷化镓铟、磷化镓铟和磷砷化镓铟。在实施例中，鳍104可以包括两种不同半导体材料的交替堆叠层，诸如交替堆叠的硅和硅锗层。鳍104可以可选地包括掺杂剂以改善器件100的性能。例如，鳍104可以包括诸如磷或砷的n型掺杂剂，或诸如硼或铟的p型掺杂剂。
隔离结构106可以包括氧化硅、氮化硅、氮氧化硅、氟掺杂的硅酸盐玻璃(FSG)、低k介电材料和/或其他合适的绝缘材料。隔离结构106可以是浅沟槽隔离(STI)部件。诸如场氧化物、硅的局部氧化(LOCOS)和/或其他合适的结构的其他隔离结构也是可能的。隔离结构106可以包括多层结构，例如，具有与鳍104相邻的一个或多个热氧化物衬垫层。
高k介电层108可以包括一种或多种高k介电材料(或一个或多个高k介电材料层)，诸如氧化铪硅(HfSiO)、氧化铪(HfO2)、氧化铝(Al2O3)、氧化锆(ZrO2)、氧化镧(La2O3)、氧化钛(TiO2)、氧化钇(Y2O3)、钛酸锶(SrTiO3)或它们的组合。
导电层110包括一个或多个金属层，诸如功函金属层、导电阻挡层和金属填充层。取决于器件的类型(PFET或NFET)，功函金属层可以是p型或n型功函层。p型功函层包括选自但不限于氮化钛(TiN)、氮化钽(TaN)、钌(Ru)、钼(Mo)、钨(W)、铂(Pt)的金属或它们的组合。n型功函层包括选自但不限于钛(Ti)、铝(Al)、碳化钽(TaC)、碳氮化钽(TaCN)、氮化钽硅(TaSiN)、氮化钛硅(TiSiN)或它们的组合。金属填充层可以包括铝(Al)、钨(W)、钴(Co)和/或其他合适的材料。
介电部件114可以包括一种或多种介电材料，诸如氮化硅、氧化硅、氮氧化硅、氟掺杂的硅酸盐玻璃(FSG)、低k介电材料和/或其他合适的绝缘材料；并且可以通过CVD(化学汽相沉积)、PVD(物理汽相沉积)、ALD(原子层沉积)或其他合适的方法形成。
CESL 164可以包括氮化硅、氮氧化硅、具有氧(O)或碳(C)元素的氮化硅、和/或其他材料；并且可以通过CVD、PVD、ALD或其他合适的方法形成。第一ILD层166可以包括正硅酸乙酯(TEOS)氧化物、未掺杂的硅酸盐玻璃或掺杂的氧化硅(诸如硼磷硅酸盐玻璃(BPSG)、熔融石英玻璃(FSG)、磷硅酸盐玻璃(PSG)、硼掺杂的硅玻璃(BSG))和/或其他合适的介电材料。第一ILD层166可以通过PECVD(等离子体增强CVD)、FCVD(可流动CVD)或其他合适的方法形成。第二ILD层180是另一介电层，并且可以包括TEOS氧化物、未掺杂的硅酸盐玻璃或掺杂的氧化硅(诸如BPSG、FSG、PSG、BSG)和/或其他合适的介电材料。ILD层166和180可以包括不同的材料成分。可以通过PECVD、FCVD或其他合适的方法形成介电层180。
在一些实施例中，导电材料184包括诸如TaN或TiN的阻挡层186和诸如Al、Cu或W的金属填充层188。阻挡层186可以共形地覆盖介电层180、第一ILD层166、硅化物层165、介电部件114a和114b的侧壁。可以使用诸如CVD、PVD、PECVD、ALD或其他合适方法的工艺来沉积阻挡层186。可以使用CVD、PVD、镀或其他合适的方法来沉积金属填充层188。
图2A、图2B和图2C示出了根据实施例的用于形成半导体器件100的方法200的流程图。方法200仅仅是实例，并不旨在将本发明限制为超出权利要求中明确记载的内容。可以在方法200之前、期间和之后提供额外的操作，并且对于方法的额外实施例，可以替换、消除或移动所描述的一些操作。下面结合示出各个截面图的图3至图17来描述方法200，诸如在根据方法200的制造步骤期间沿着半导体器件100的A-A线、D-D线和E-E线。为简单起见，使用沿着D-D线或E-E线的半导体器件100的示出较少的鳍的截面图，而不是沿着B-B线或C-C线。
在操作202中，方法200(图2A)提供或提供有器件结构100，器件结构100具有衬底102、从衬底102突出的鳍104(包括鳍104a、104b和104c)以及位于衬底102上方和鳍104之间的隔离结构106，如图3所示。具体地，图3示出了沿图1A的E-E线的器件结构100的截面图。上面已经参考图1A至图1D讨论了用于衬底102、鳍104和隔离结构106的各种材料。
在实施例中，衬底102可以是诸如硅晶圆的晶圆。可以通过在衬底102的整个区域上方外延生长一个或多个半导体层，并且之后将其图案化以形成各个鳍104来形成鳍104。可以通过任何合适的方法图案化鳍104。例如，可以使用包括双重图案化或多重图案化工艺的一个或多个光刻工艺来图案化鳍104。通常，双重图案化或多重图案化工艺结合光刻和自对准工艺，允许创建具有例如比使用单个直接光刻工艺可以获得的间距更小的间距的图案。例如，在一个实施例中，在衬底上方形成牺牲层并且使用光刻工艺图案化牺牲层。使用自对准工艺在图案化的牺牲层旁边形成间隔件。之后去除牺牲层，之后可以使用剩余的间隔件或心轴通过蚀刻初始外延半导体层来图案化鳍104。蚀刻工艺可以包括干蚀刻、湿蚀刻、反应离子蚀刻(RIE)和/或其他合适的工艺。例如，干蚀刻工艺可以实施含氧气体、含氟气体(例如CF4、SF6、CH2F2、CHF3和/或C2F6)、含氯气体(例如Cl2、CHCl3、CCl4和/或BCl3)、含溴气体(例如HBr和/或CHBR3)、含碘气体、其他合适气体和/或等离子体和/或它们的组合。例如，湿蚀刻工艺可以包括在稀释的氢氟酸(DHF)；氢氧化钾(KOH)溶液；氨；含有氢氟酸(HF)、硝酸(HNO3)和/或乙酸(CH3COOH)的溶液；或其他合适的湿蚀刻剂中的蚀刻。
隔离结构106可以通过一种或多种沉积和蚀刻方法形成。沉积方法可以包括热氧化、化学氧化和化学汽相沉积(CVD)，诸如可流动CVD(FCVD)。蚀刻方法可以包括干蚀刻、湿蚀刻和化学机械平坦化(CMP)。
在操作204中，方法200(图2A)形成与鳍104接合的栅极结构112。在实施例中，操作204包括沉积包括栅极介电层108和导电层110的栅极结构112的各个层，以及图案化各个层以形成栅极结构112，如图1A和图1C所示。在特定实施例中，操作204使用替换栅极工艺，其中，其首先形成临时(或伪)栅极结构，并且之后用栅极结构112替换临时栅极结构。图2B中示出了替换栅极工艺的实施例，包括操作204a、204b和204c，这些将在下面进一步讨论。
在操作204a中，方法200(图2B)形成与鳍104接合的临时栅极结构149，如图4A和图4B所示，其分别示出了沿图1A的A-A线和E-E线切割的器件100的截面图。参考图4A和图4B，每个临时栅极结构149包括界面层150、电极层152和两个硬掩模层154和156。操作204a还在临时栅极结构149的侧壁上形成栅极间隔件160。
界面层150可以包括诸如氧化硅层(例如SiO2)或氮氧化硅(例如SiON)的介电材料，并且可以通过化学氧化、热氧化、原子层沉积(ALD)、CVD和/或其他合适的方法形成。栅电极152可以包括多晶硅(poly-Si)，并且可以通过合适的沉积工艺形成，诸如低压化学汽相沉积(LPCVD)和等离子体增强CVD(PECVD)。硬掩模层154和156的每个可以包括一个或多个介电材料层，介电材料诸如氧化硅和/或氮化硅，并且可以通过CVD或其他合适的方法形成。可以通过光刻和蚀刻工艺图案化各个层150、152、154和156。栅极间隔件160可以包括介电材料，诸如氧化硅、氮化硅、氮氧化硅、碳化硅、其他介电材料或它们的组合，并且可以包括一个或多个材料层。可以通过在隔离结构106、鳍104和临时栅极结构149上方沉积作为毯式层的间隔件材料来形成栅极间隔件160。之后通过各向异性蚀刻工艺蚀刻间隔件材料，以暴露隔离结构106、硬掩模层156和鳍104的顶面。临时栅极结构149的侧壁上的间隔件材料的部分变为栅极间隔件160。相邻的栅极间隔件160提供沟槽158，沟槽158暴露器件100的S/D区域中的鳍104。
在操作206中，方法200(图2A和图2B)形成源极/漏极(或S/D)部件162，诸如图5A和图5B所示，它们分别是沿着图1A的A-A线和D-D线的器件100的截面图。例如，操作206可以将凹槽蚀刻到暴露在沟槽158中的鳍104中，并且在凹槽中外延生长半导体材料。半导体材料可以升高到鳍104的顶面上方，如图5A和图5B所示。在本实施例中，一些S/D部件162合并在一起，诸如图5B所示。
在操作208中，方法200(图2A和图2B)形成各个部件，包括位于S/D部件162上方的接触蚀刻停止层(CESL)164，以及位于CESL 164上方的层间介电(ILD)层166，诸如图6A和图6B所示，它们分别是沿着图1A的A-A线和B-B线的器件100的截面图。CESL 164可以包括氮化硅、氮氧化硅、具有氧(O)或碳(C)元素的氮化硅和/或其他材料；并且可以通过CVD、PVD(物理汽相沉积)、ALD或其他合适的方法形成。ILD层166可以包括正硅酸乙酯(TEOS)氧化物、未掺杂的硅酸盐玻璃或掺杂的氧化硅(诸如硼磷硅酸盐玻璃(BPSG)、熔融石英玻璃(FSG)、磷硅酸盐玻璃(PSG)、硼掺杂的硅玻璃(BSG))和/或其他合适的介电材料。ILD层166可以通过PECVD、FCVD或其他合适的方法形成。操作208可以实施一个或多个CMP工艺以平坦化器件100的顶面，去除硬掩模层154和156，以及暴露电极层152。
在操作204b中，方法200(图2B)去除临时栅极结构149以形成栅极沟槽169，诸如图7A和图7B所示，它们分别是沿图1A的A-A和E-E线的器件100的截面图。栅极沟槽169暴露鳍104的表面和栅极间隔件160的侧壁表面。操作204b可以包括对电极层152和界面层150中的材料具有选择性的一个或多个蚀刻工艺。蚀刻工艺可以包括干蚀刻、湿蚀刻、反应离子蚀刻或其他合适的蚀刻方法。
在操作204c中，方法200(图2B)在栅极沟槽169中沉积栅极结构(例如高k金属栅极)112，诸如图8A和图8B所示，它们分别是沿图1A的A-A和E-E线的器件100的截面图。栅极结构112包括高k介电层108和导电层110。栅极结构112还可以包括位于高k介电层108和鳍104之间的界面层(例如SiO2)(未示出)。可以使用化学氧化、热氧化、ALD、CVD和/或其他合适的方法形成界面层。上面已经参考图1A至图1D讨论了高k介电层108和导电层110的材料。高k介电层108可以包括一个或多个高k介电材料层，并且可以使用CVD、ALD和/或其他合适的方法沉积。导电层110可以包括一个或多个功函金属层和金属填充层，并且可以使用诸如CVD、PVD、电镀和/或其他合适工艺的方法沉积。
在操作210中，方法200(图2A和图2B)在器件100上方形成一个或多个图案化的硬掩模层，诸如图9A和图9B所示，它们分别是沿着图1A的D-D线和E-E线的器件100的截面图。在该实例中示出了一个硬掩模层170。硬掩模层170可以包括氮化钛、氮化硅、非晶硅、硅酸钇(YSiOx)或其他合适的硬掩模材料。在实施例中，操作210使用CVD、PVD、ALD或其他合适的方法沉积硬掩模层170，并且随后图案化硬掩模层170以形成开口171。开口171对应于图1A的介电部件114的位置。开口171暴露导电层110和ILD层166。在实例中，操作210可以通过光刻胶涂覆、曝光、曝光后烘烤和显影在硬掩模层170上方形成图案化的光刻胶。在特定实施例中，操作210使用单次曝光工艺(例如使用EUV暴露)来曝光光刻胶层以具有潜像，并且之后显影光刻胶层以提供开口。之后，操作210使用图案化的光刻胶作为蚀刻掩模来蚀刻硬掩模层170，以形成开口171。蚀刻工艺可以包括湿蚀刻、干蚀刻、反应离子蚀刻或其他合适的蚀刻方法。之后，例如通过抗蚀剂剥离去除图案化的光刻胶。
在操作212中，方法200(图2A)通过开口171蚀刻栅极结构112。参考图10A，其是沿图1A的E-E线的器件100的截面图，操作212将开口171向下延伸并且穿过栅极结构112，并且在实施例中还延伸到隔离结构106中。蚀刻工艺可以使用蚀刻栅极结构112中的各个层的一种或多种蚀刻剂或蚀刻剂的混合物。在示例性实施例中，导电层110包括TiSiN、TaN、TiN、W或它们的组合。为了蚀刻这样的导电层和高k介电层108，操作218可以使用具有氯、氟、溴、氧、氢、碳或它们的组合的原子的蚀刻剂进行干蚀刻工艺。例如，蚀刻剂可以具有Cl2、O2、含碳和氟的气体、含溴和氟的气体以及含碳-氢和氟的气体的气体混合物。在实例中，蚀刻剂包括Cl2、O2、CF4、BCl3和CHF3的气体混合物。为了确保栅极结构112的其余部分之间的隔离，在一些实施例中，操作212实施一些过蚀刻以将开口171延伸到隔离结构106中。小心控制这种过蚀刻以不暴露衬底102。延伸的开口171也称为CMG沟槽171。
参考图10B，它是沿着图1A的D-D线的器件100的截面图，操作212中的蚀刻工艺也调整为蚀刻ILD层166。在CMG沟槽171的形成期间选择蚀刻栅极结构112以及ILD层166的蚀刻剂可能在这些材料中具有不等的蚀刻速率，从而使得不同的蚀刻速率可以CMG沟槽171的不同位置处产生不同的蚀刻深度。换句话说，CMG沟槽171的底面可以具有阶梯轮廓，从而使得栅极结构112外部的CMG沟槽171的底面位于隔离结构106之上，并且在栅极结构112的位置处延伸到隔离结构106中。
在操作214中，方法200(图2A)用一种或多种介电材料填充CMG沟槽171以形成介电部件114，并且实施化学机械抛光(CMP)工艺以去除图案化的硬掩模170并且平坦化器件100的顶面。所得到的结构如图11A和图11B所示，它们分别是沿着图1A的E-E线和D-D线的器件100的截面图。CMG沟槽171中的一种或多种介电材料形成介电部件114(具体地，介电部件114a)。由于栅极结构112的侧壁包含金属材料，所以至少介电部件114的外部(即与栅极结构112的侧壁直接接触)不含活性化学成分，诸如氧。例如，介电部件114的外部可以包括氮化硅并且不含氧或氧化物。在一些实施例中，介电部件114可以在其内部包括一些氧化物。可选地，介电部件114可以包括一个均匀的氮化硅层并且不含氧化物。可以使用CVD、PVD、ALD或其他合适的方法来沉积介电部件114。在本实施例中，使用ALD沉积介电部件114以确保其完全填充CMG沟槽171。
在操作216中，方法200(图2A)在器件100上方沉积介电层180，诸如图12所示，它是沿图1A的D-D线的器件的截面图。在实施例中，介电层180是另一ILD层，并且可以包括TEOS氧化物、未掺杂的硅酸盐玻璃或掺杂的氧化硅(诸如BPSG、FSG、PSG、BSG)和/或其他合适的介电材料。可以通过PECVD、FCVD或其他合适的方法形成介电层180。
在操作218中，方法200(图2C)在器件100中蚀刻接触孔182，暴露介电部件114，诸如图13所示，这是沿图1A的D-D线的器件的截面图。在实施例中，操作218包括在器件100上方涂覆光刻胶层，曝光和显影光刻胶层以形成开口，以及蚀刻第二ILD层180以形成接触孔182。覆盖层(未示出)可以设置在第一ILD层166和第二ILD层180之间。具体地，覆盖层可以用作蚀刻停止层，从而使得蚀刻工艺调整为选择性地蚀刻第二ILD层180而不是覆盖层。之后调整随后的蚀刻工艺以打开覆盖层以暴露第一ILD层166和介电部件114。在实施例中，蚀刻工艺是干蚀刻。例如，蚀刻剂可以具有CF4、H2和N2的气体混合物。
在操作220中，方法200(图2C)选择性地使介电部件114凹进而基本上不蚀刻第一ILD层166，诸如图14所示，它是沿图1A的D-D线的器件的截面图。凹进蚀刻工艺是选择性蚀刻工艺，其提供可以选择性地蚀刻介电部件114而不损坏或攻击第一ILD层166的蚀刻剂。因此，第一ILD层166保持完整。通过这样做，可以在不同的工艺阶段单独地和独立地蚀刻介电部件114和第一ILD层166。在实施例中，选择性凹进蚀刻工艺是干蚀刻。例如，蚀刻剂可以具有CH3F和H2的气体混合物。在操作202之后，在一些实施例中，介电部件114可以在Z方向上凹进至少50nm，并且可以形成介电部件114的凹形顶面。操作202可以使介电部件114一直地凹进到相邻S/D部件162的面向上的侧壁163a之下。可选地，介电部件114的顶部仍可以保持高于面向上的侧壁163a的底部，而第一ILD层166的后续蚀刻也将进一步使介电部件114凹进。
在操作222中，方法200(图2C)选择性地蚀刻第一ILD层166以向下延伸接触孔182以暴露S/D部件162的至少面向上的侧壁163a，诸如图15所示，它是沿图1A的D-D线的器件的截面图。在一些实施例中，凹进蚀刻工艺是选择性蚀刻工艺，其提供选择性蚀刻第一ILD层166而基本上不蚀刻介电部件114的蚀刻剂。在一些实施例中，凹进蚀刻工艺是选择性蚀刻工艺，其也被调整为蚀刻介电部件114，但是蚀刻速率较慢。例如，第一ILD层166在介电部件114上方的蚀刻速率比可以大于约5:1。在使第一ILD层166凹进之后，介电部件114可以从周围的第一ILD层166突出。由于操作222还可以蚀刻介电部件114的部分，因此介电部件114可以进一步凹进至位于相邻S/D部件162的面向上的侧壁163a之下。在实施例中，选择性凹进蚀刻工艺是干蚀刻。例如，蚀刻剂可以具有C4F6、CO、CO2和Ar的气体混合物。在蚀刻工艺期间，介电部件114的顶面可以变成凸的。
在操作224中，方法200(图2C)从接触孔182去除暴露的CESL 164，诸如图16所示，它是沿图1A的D-D线的器件的截面图。凹进蚀刻工艺是选择性蚀刻工艺，其提供可以选择性地蚀刻CESL 164而基本上不蚀刻第一ILD层166的蚀刻剂。在一些实施例中，CESL 164和介电部件114都包含氮化物，因此对于介电部件114的蚀刻选择性较差，这进一步使介电部件114凹进约2nm至约5nm。在一些实施例中，在操作224之后，介电部件114位于相邻S/D部件162的面向下的侧壁163b之下。
在操作226中，方法200(图2C)将一种或多种导电材料184沉积到接触孔182中作为S/D接触件，诸如图17所示，它是沿图1A的D-D线的器件的截面图。在实施例中，方法200可以在沉积导电材料184之前在S/D部件162的暴露表面上方形成硅化物部件165。在一些实施例中，硅化物部件165通过诸如自对准硅化物的硅化形成，在自对准硅化物中，在S/D部件162上方形成金属材料，之后升高温度以退火并且引起下面的硅和金属之间的反应以形成硅化物，并且蚀刻掉未反应的金属。硅化物部件165有助于降低接触电阻。在实施例中，导电材料184包括诸如TaN或TiN的阻挡层186和诸如Al、Cu或W的金属填充层188。可以使用CVD、PVD、PECVD、ALD、镀或其他合适的方法来沉积导电材料184中的层。由于S/D部件162的大表面积，S/D接触件与下面的S/D部件162具有足够大的界面，以用于降低S/D接触电阻。在图17中，介电部件114的底面位于栅极区域外部的隔离结构106的顶面之上，从而使得介电部件114的从栅极区域外部到栅极区域的沿X方向的底面可以具有阶梯轮廓，例如阶梯高度在从约2nm至约10nm的范围内。然而，在一些可选实施例中，如上所述，介电部件114的底部也可以延伸到隔离部件106中，如图18所示。因此，介电部件114的从栅极区域外部到栅极区域的沿X方向的底面可以是基本上平坦的或具有较小的阶梯高度，诸如在从约1nm至约5nm的范围内。
在操作228中，方法200(图2C)实施进一步的步骤以完成器件100的制造。例如，方法200可以实施CMP工艺以去除过量材料184并且形成电连接各个晶体管的源极、漏极、栅极端子的金属互连件，以形成完整的IC。
虽然不旨在限制，但是本发明的一个或多个实施例为半导体器件及其形成提供了许多益处。例如，本发明的实施例提供切割金属栅极工艺，以及随后的选择性蚀刻工艺以使S/D接触孔中的隔离材料凹进。这允许S/D接触件具有更大的接合区域。这不仅增加了器件集成度，还降低了S/D接触电阻。
在一个示例性方面，本发明针对方法。该方法包括提供一种结构，该结构具有衬底、位于衬底上方并且总体沿第一方向纵向定向的鳍、位于鳍上方的源极/漏极(S/D)部件、覆盖S/D部件的顶面和侧壁的第一介电层、嵌入在第一介电层中的隔离部件，其中，隔离部件的顶面位于S/D部件之上，以及覆盖第一介电层和隔离部件的第二介电层；实施第一蚀刻工艺以使第二介电层凹进以暴露隔离部件；实施第二蚀刻工艺以选择性地使隔离部件凹进；并且实施第三蚀刻工艺以使第一介电层凹进以暴露S/D部件。在一些实施例中，该方法还包括沉积与S/D部件和隔离部件直接接触的导电材料。在一些实施例中，S/D部件具有面向上的侧壁，其中，第二蚀刻工艺选择性地使隔离部件凹进，从而使得隔离部件的顶面的部分位于面向上的侧壁之下。在一些实施例中，该结构还具有位于鳍上方并且总体沿着垂直于第一方向的第二方向纵向定向的栅极结构，其中，隔离部件沿第一方向延伸并且将栅极结构分成两部分。在一些实施例中，在第二蚀刻工艺之后，隔离部件的顶面的部分与栅极结构的顶面共面。在一些实施例中，隔离部件的底面具有阶梯轮廓。在一些实施例中，在实施第三蚀刻工艺之前实施第二蚀刻工艺。在一些实施例中，第三蚀刻工艺调整为也蚀刻隔离部件。在一些实施例中，在第三蚀刻工艺之后，设置在隔离部件的相对侧壁上的第一介电层的水平面是不均匀的。在一些实施例中，在第二蚀刻工艺之后，隔离部件的顶面变成凹的，并且其中，在第三蚀刻工艺之后隔离部件的顶面变成凸的。
在另一示例性方面，本发明针对用于制造半导体器件的方法。该方法包括在衬底上形成第一和第二鳍，第一和第二鳍具有栅极区域和源极/漏极(S/D)区域；在栅极区域中的第一和第二鳍上方形成栅极结构；在第一和第二鳍之间沉积介电层，介电层覆盖栅极结构的侧壁；实施蚀刻工艺以形成划分栅极结构的沟槽，沟槽延伸到第一和第二鳍之间的介电层的区域中；用介电材料填充沟槽；选择性地蚀刻介电材料；选择性地蚀刻介电层；在S/D区域的第一和第二鳍的顶上沉积与介电材料直接接触的导电材料。在一些实施例中，介电材料和介电层具有不同的材料成分，从而使得介电材料的选择性蚀刻基本上不蚀刻介电层。在一些实施例中，在选择性蚀刻介电层之后，介电材料从介电层突出。在一些实施例中，在选择性蚀刻介电层之前，选择性地蚀刻介电材料。在一些实施例中，该方法还包括在第一和第二鳍的顶上形成S/D部件，S/D部件具有面向上的侧壁，其中，在选择性地蚀刻介电材料之前和之后，使介电材料的顶面从面向上的侧壁之上的位置凹进到面向上的侧壁之下。在一些实施例中，用介电材料填充沟槽包括实施原子层沉积(ALD)工艺。
在又一示例性方面，本发明针对半导体器件。半导体器件包括衬底；从衬底突出的鳍；位于鳍上方的外延源极/漏极(S/D)部件；与外延S/D部件相邻的介电部件，其中，介电部件位于外延S/D部件的面向上的侧壁之下；以及与外延S/D部件和介电部件直接接触的导电部件。在一些实施例中，半导体器件还包括围绕外延S/D部件和介电部件的介电层，其中，设置在介电部件的相对侧壁上的介电层的水平面是不均匀的。在一些实施例中，半导体器件还包括位于沟道区域中的鳍上方的金属栅极结构，其中，介电部件将金属栅极结构至少分成第一部分和第二部分。在一些实施例中，介电部件的底面具有阶梯轮廓。
上面概述了若干实施例的特征，使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中他们可以做出多种变化、替换以及改变。

Claims (10)

1.一种制造半导体器件的方法，包括：
提供一种结构，所述结构具有：
衬底；
鳍，位于所述衬底上方并且总体沿第一方向纵向定向；
源极/漏极(S/D)部件，位于所述鳍上方；
第一介电层，覆盖所述源极/漏极部件的顶面和侧壁；
隔离部件，嵌入在所述第一介电层中，其中，所述隔离部件的顶面位于所述源极/漏极部件之上；以及
第二介电层，覆盖所述第一介电层和所述隔离部件；
实施第一蚀刻工艺以使所述第二介电层凹进以暴露所述隔离部件；
实施第二蚀刻工艺以选择性地使所述隔离部件凹进；以及
实施第三蚀刻工艺以使所述第一介电层凹进以暴露所述源极/漏极部件。
2.根据权利要求1所述的方法，还包括：
沉积与所述源极/漏极部件和所述隔离部件直接接触的导电材料。
3.根据权利要求1所述的方法，其中，所述源极/漏极部件具有面向上的侧壁，其中，所述第二蚀刻工艺选择性地使隔离部件凹进，从而使得所述隔离部件的顶面的部分位于所述面向上的侧壁之下。
4.根据权利要求1所述的方法，其中，所述结构还具有位于所述鳍上方，并且总体沿着垂直于所述第一方向的第二方向纵向定向的栅极结构，其中，所述隔离部件沿所述第一方向延伸并且将所述栅极结构分成两部分。
5.根据权利要求4所述的方法，其中，在所述第二蚀刻工艺之后，所述隔离部件的顶面的部分与所述栅极结构的顶面共面。
6.根据权利要求4所述的方法，其中，所述隔离部件的底面具有阶梯轮廓。
7.根据权利要求1所述的方法，其中，在实施所述第三蚀刻工艺之前实施所述第二蚀刻工艺。
8.根据权利要求1所述的方法，其中，将所述第三蚀刻工艺调整为也蚀刻所述隔离部件。
9.一种制造半导体器件的方法，包括：
在衬底上形成第一鳍和第二鳍，所述第一鳍和所述第二鳍具有栅极区域和源极/漏极(S/D)区域；
在所述栅极区域中的所述第一鳍和所述第二鳍上方形成栅极结构；
在所述第一鳍和所述第二鳍之间沉积介电层，所述介电层覆盖所述栅极结构的侧壁；
实施蚀刻工艺以形成划分所述栅极结构的沟槽，所述沟槽延伸到所述第一鳍和所述第二鳍之间的所述介电层的区域中；
用介电材料填充所述沟槽；
选择性地蚀刻所述介电材料；
选择性地蚀刻所述介电层；以及
在所述源极/漏极区域中的所述第一鳍和所述第二鳍的顶上沉积与所述介电材料直接接触的导电材料。
10.一种半导体器件，包括：
衬底；
鳍，从所述衬底突出；
外延源极/漏极(S/D)部件，位于所述鳍上方；
介电部件，与所述外延源极/漏极部件相邻，其中，所述介电部件位于所述外延源极/漏极部件的面向上的侧壁之下；以及
导电部件，与所述外延源极/漏极部件和所述介电部件直接接触。
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