CN113257676A - 半导体器件及制造方法 - Google Patents
半导体器件及制造方法 Download PDFInfo
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- CN113257676A CN113257676A CN202110264642.2A CN202110264642A CN113257676A CN 113257676 A CN113257676 A CN 113257676A CN 202110264642 A CN202110264642 A CN 202110264642A CN 113257676 A CN113257676 A CN 113257676A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 63
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 238000000034 method Methods 0.000 claims abstract description 106
- 239000003989 dielectric material Substances 0.000 claims abstract description 74
- 125000006850 spacer group Chemical group 0.000 claims abstract description 29
- 239000013590 bulk material Substances 0.000 claims abstract description 7
- 239000000463 material Substances 0.000 claims description 121
- 239000002243 precursor Substances 0.000 claims description 61
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 38
- 239000000203 mixture Substances 0.000 claims description 30
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 25
- 239000001301 oxygen Substances 0.000 claims description 25
- 229910052760 oxygen Inorganic materials 0.000 claims description 25
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 24
- 229910052799 carbon Inorganic materials 0.000 claims description 24
- 229910052757 nitrogen Inorganic materials 0.000 claims description 19
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 13
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 13
- 238000000151 deposition Methods 0.000 claims description 12
- 238000000059 patterning Methods 0.000 claims description 8
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 claims description 5
- 239000010410 layer Substances 0.000 description 179
- 230000008569 process Effects 0.000 description 80
- 239000000758 substrate Substances 0.000 description 37
- 238000005530 etching Methods 0.000 description 24
- 239000012535 impurity Substances 0.000 description 18
- 229920002120 photoresistant polymer Polymers 0.000 description 15
- 238000006243 chemical reaction Methods 0.000 description 13
- 239000011810 insulating material Substances 0.000 description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 12
- 229910052710 silicon Inorganic materials 0.000 description 12
- 239000010703 silicon Substances 0.000 description 12
- 238000002513 implantation Methods 0.000 description 11
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 10
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 9
- 238000000231 atomic layer deposition Methods 0.000 description 9
- 239000008393 encapsulating agent Substances 0.000 description 9
- 238000011065 in-situ storage Methods 0.000 description 9
- 238000002955 isolation Methods 0.000 description 9
- ATUOYWHBWRKTHZ-UHFFFAOYSA-N Propane Chemical compound CCC ATUOYWHBWRKTHZ-UHFFFAOYSA-N 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 239000012467 final product Substances 0.000 description 6
- 238000000206 photolithography Methods 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- LXEXBJXDGVGRAR-UHFFFAOYSA-N trichloro(trichlorosilyl)silane Chemical compound Cl[Si](Cl)(Cl)[Si](Cl)(Cl)Cl LXEXBJXDGVGRAR-UHFFFAOYSA-N 0.000 description 6
- 229910021529 ammonia Inorganic materials 0.000 description 5
- 238000000137 annealing Methods 0.000 description 5
- 238000005137 deposition process Methods 0.000 description 5
- 238000007789 sealing Methods 0.000 description 5
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 5
- 229910010271 silicon carbide Inorganic materials 0.000 description 5
- 239000002356 single layer Substances 0.000 description 5
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 4
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 4
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 150000001875 compounds Chemical class 0.000 description 4
- 239000004020 conductor Substances 0.000 description 4
- 239000007943 implant Substances 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- 230000000873 masking effect Effects 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 239000005360 phosphosilicate glass Substances 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 239000001294 propane Substances 0.000 description 4
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 3
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 238000004380 ashing Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000005388 borosilicate glass Substances 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 230000009969 flowable effect Effects 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 239000000047 product Substances 0.000 description 3
- 229910005540 GaP Inorganic materials 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- 229910000673 Indium arsenide Inorganic materials 0.000 description 2
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 230000000704 physical effect Effects 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000008439 repair process Effects 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- IHGSAQHSAGRWNI-UHFFFAOYSA-N 1-(4-bromophenyl)-2,2,2-trifluoroethanone Chemical compound FC(F)(F)C(=O)C1=CC=C(Br)C=C1 IHGSAQHSAGRWNI-UHFFFAOYSA-N 0.000 description 1
- 229910015900 BF3 Inorganic materials 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229910002601 GaN Inorganic materials 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 description 1
- KXNLCSXBJCPWGL-UHFFFAOYSA-N [Ga].[As].[In] Chemical compound [Ga].[As].[In] KXNLCSXBJCPWGL-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- AUCDRFABNLOFRE-UHFFFAOYSA-N alumane;indium Chemical compound [AlH3].[In] AUCDRFABNLOFRE-UHFFFAOYSA-N 0.000 description 1
- FTWRSWRBSVXQPI-UHFFFAOYSA-N alumanylidynearsane;gallanylidynearsane Chemical compound [As]#[Al].[As]#[Ga] FTWRSWRBSVXQPI-UHFFFAOYSA-N 0.000 description 1
- MDPILPRLPQYEEN-UHFFFAOYSA-N aluminium arsenide Chemical compound [As]#[Al] MDPILPRLPQYEEN-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- AJGDITRVXRPLBY-UHFFFAOYSA-N aluminum indium Chemical compound [Al].[In] AJGDITRVXRPLBY-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052788 barium Inorganic materials 0.000 description 1
- DSAJWYNOEDNPEQ-UHFFFAOYSA-N barium atom Chemical compound [Ba] DSAJWYNOEDNPEQ-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- WTEOIRVLGSZEPR-UHFFFAOYSA-N boron trifluoride Chemical compound FB(F)F WTEOIRVLGSZEPR-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000000109 continuous material Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000001351 cycling effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- VTGARNNDLOTBET-UHFFFAOYSA-N gallium antimonide Chemical compound [Sb]#[Ga] VTGARNNDLOTBET-UHFFFAOYSA-N 0.000 description 1
- IWTIUUVUEKAHRM-UHFFFAOYSA-N germanium tin Chemical compound [Ge].[Sn] IWTIUUVUEKAHRM-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- WPBNNNQJVZRUHP-UHFFFAOYSA-L manganese(2+);methyl n-[[2-(methoxycarbonylcarbamothioylamino)phenyl]carbamothioyl]carbamate;n-[2-(sulfidocarbothioylamino)ethyl]carbamodithioate Chemical compound [Mn+2].[S-]C(=S)NCCNC([S-])=S.COC(=O)NC(=S)NC1=CC=CC=C1NC(=S)NC(=O)OC WPBNNNQJVZRUHP-UHFFFAOYSA-L 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910052914 metal silicate Inorganic materials 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- NFFIWVVINABMKP-UHFFFAOYSA-N methylidynetantalum Chemical compound [Ta]#C NFFIWVVINABMKP-UHFFFAOYSA-N 0.000 description 1
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 1
- 239000002135 nanosheet Substances 0.000 description 1
- 239000002070 nanowire Substances 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 1
- 239000012811 non-conductive material Substances 0.000 description 1
- -1 or the like Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 150000002978 peroxides Chemical class 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000010926 purge Methods 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 150000004760 silicates Chemical class 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000013589 supplement Substances 0.000 description 1
- 229910003468 tantalcarbide Inorganic materials 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
- H01L21/28132—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects conducting part of electrode is difined by a sidewall spacer or a similar technique, e.g. oxidation under mask, plating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
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Abstract
本公开涉及半导体器件及制造方法。提出了半导体器件及其制造方法,其中,在半导体器件的栅极的侧壁上制造间隔件。在实施例中,间隔件包括第一密封件、第二密封件和接触蚀刻停止层,其中,第一密封件包括第一壳体以及第一体材料,第二密封件包括第二壳体以及第二体材料,并且接触蚀刻停止层包括第三体材料和第二电介质材料。
Description
技术领域
本公开涉及半导体器件及制造方法。
背景技术
半导体器件被用于各种电子应用中,例如,个人计算机、蜂窝电话、数码相机、以及其他电子设备。半导体器件通常通过以下方式来制造:在半导体衬底之上顺序地沉积材料的绝缘层或电介质层、导电层和半导体层,并使用光刻对各个材料层进行图案化以在其上形成电路组件和元件。
半导体行业通过不断减小最小特征尺寸来不断提高各种电子组件(例如,晶体管、二极管、电阻器、电容器等)的集成密度,这允许将更多的组件集成到给定区域中。
发明内容
根据本公开的一个实施例,提供了一种半导体器件,包括:第一间隔件层,包括设置在两个外层之间的内层,其中,所述内层和所述两个外层各自包括第一材料,其中,所述两个外层的碳含量大于所述内层的碳含量,并且所述两个外层的氧含量小于所述内层的氧含量;以及第二间隔件层,包括第一层和第二层,所述第一层是所述第一材料并且与所述两个外层之一直接接触。
根据本公开的另一实施例,提供了一种半导体器件,包括:第一密封件,与栅极堆叠相邻,所述第一密封件包括:具有第一成分的第一材料的第一壳体;以及具有第二成分的所述第一材料的第一体材料,所述第二成分不同于所述第一成分;第二密封件,与所述第一密封件实体接触,所述第二密封件包括:具有第三成分的所述第一材料的第二壳体;以及具有第四成分的所述第一材料的第二体材料,所述第四成分不同于所述第三成分;以及接触蚀刻停止层,与所述第二密封件实体接触,所述接触蚀刻停止层包括:具有第五成分的所述第一材料的第三体材料;以及不同于所述第一材料的第二材料的第三壳体。
根据本公开的又一实施例,提供了一种制造半导体器件的方法,所述方法包括:在半导体鳍之上图案化虚设栅极电极;使用第一组暴露时间将第一组前体顺序地引入到所述虚设栅极电极,以形成第一壳层;使用不同于所述第一组暴露时间的第二组暴露时间将所述第一组前体顺序地引入到所述虚设栅极电极,以形成第一体电介质材料;使用第三组暴露时间将所述第一组前体顺序地引入到所述虚设栅极电极,以形成第二体电介质材料;使用不同于所述第一组暴露时间的第四组暴露时间将所述第一组前体顺序地引入到所述虚设栅极电极,以形成第二壳层;使用第五组暴露时间将所述第一组前体顺序地引入到所述虚设栅极电极,以形成第三体电介质材料;以及在使用所述第五组暴露时间将所述第一组前体顺序地引入到所述虚设栅极电极之后,沉积电介质材料。
附图说明
在结合附图阅读下面的具体实施方式时,可以从下面的具体实施方式中最佳地理解本公开的各方面。注意,根据行业的标准做法,各种特征不是按比例绘制的。事实上,为了讨论的清楚起见,各种特征的尺寸可被任意增大或减小。
图1示出了根据一些实施例的三维视图中的FinFET的示例。
图2、图3、图4、图5、图6、图7、图8A、图8B、图8C、图8D、图9A、图9B、图9C、图9D、图10A、图10B、图10C、图10D、图11A、图11B、图11C、图11D、图12A、图12B、图12C、图12D、图13A、图13B、图13C、图13D、图14A、图14B、图15A、图15B、图16A、图16B、图17A、图17B、图17C、图18A、图18B、图19A、以及图19B是根据一些实施例的制造FinFET的中间阶段的截面图。
具体实施方式
下面的公开内容提供了用于实现本发明的不同特征的许多不同的实施例或示例。下文描述了组件和布置的具体示例以简化本公开。当然,这些仅是示例而不意图是限制性的。例如,在下面的描述中,在第二特征上方或之上形成第一特征可包括以直接接触的方式形成第一特征和第二特征的实施例,并且还可包括可以在第一特征和第二特征之间形成附加特征,使得第一特征和第二特征可以不直接接触的实施例。此外,本公开可以在各个示例中重复参考数字和/或字母。该重复是出于简单和清楚的目的,并且其本身不指示所讨论的各种实施例和/或配置之间的关系。
此外,本文可使用空间相关术语(例如,“下方”、“之下”、“低于”、“以上”、“上部”等),以易于描述图中所示的一个元件或特征相对于另外(一个或多个)元件或(一个或多个)特征的关系。这些空间相关术语意在涵盖器件在使用或工作中除了图中所示朝向之外的不同朝向。装置可能以其他方式定向(旋转90度或处于其他朝向),并且本文中所用的空间相关描述符同样可被相应地解释。
现在将参考如下所述的特定实施例来讨论实施例,其中利用密封间隔件来辅助减少损坏,同时还保持适当的介电常数。然而,所描述的实施例是不旨在限制本文提出的思想的特定实施例。相反,可以在各种实施例中利用这些思想,并且所有这样的实施例完全旨在包括在说明书的范围内。
图1示出了根据一些实施例的三维视图中的FinFET的示例。FinFET包括衬底50(例如,半导体衬底)上的鳍52。隔离区域56设置在衬底50中,并且鳍52在相邻的隔离区域56之上并从相邻的隔离区域56之间突出。尽管隔离区域56被描述/示出为与衬底50分离,但如本文所用,术语“衬底”可用于指代仅半导体衬底或包括隔离区域的半导体衬底。此外,尽管鳍52被示为与衬底50一样的单一连续材料,但鳍52和/或衬底50可包括单一材料或多种材料。在该上下文中,鳍52指代在相邻的隔离区域56之间延伸的部分。
栅极电介质层92沿着鳍52的侧壁并且在鳍52的顶表面之上,并且栅极电极94位于栅极电介质层92之上。外延源极/漏极区域82被设置在鳍52的相对于栅极电介质层92和栅极电极94的相对侧。图1进一步示出了在后面的图中使用的参考横截面。横截面A-A沿着栅极电极94的纵轴,并且在例如与FinFET的外延源极/漏极区域82之间的电流流动的方向垂直的方向上。横截面B-B垂直于横截面A-A,并且沿着鳍52的纵轴并在例如FinFET的外延源极/漏极区域82之间的电流流动的方向上。横截面C-C平行于横截面A-A,并延伸穿过FinFET的源极/漏极区域。为了清楚起见,后续附图参考这些参考横截面。
在使用后栅极(gate-last)工艺形成的FinFET的上下文中讨论了本文讨论的一些实施例。在其他实施例中,可以使用先栅极(gate-first)工艺。此外,一些实施例考虑了在平面器件(例如,平面FET)、纳米结构(例如,纳米片、纳米线、栅极全环绕等)场效应晶体管(NSFET)等中使用的方面。
图2至图19B是根据一些实施例的制造FinFET的中间阶段的截面图。图2至图7示出了图1所示的参考横截面A-A,不同在于多个鳍/FinFET。图8A、图9A、图10A、图11A、图12A、图13A、图14A、图15A、图16A、图17A、图18A和图19A沿着图1所示的参考横截面A-A示出,并且图8B、图9B、图10B、图11B、图12B、图13B、图14B、图15B、图16B、图17B、图18B和图19B沿着图1所示的类似横截面B-B示出,不同在于多个鳍/FinFET。图8C、图8D、图9C、图9D、图10C、图10D、图11C、图11D、图12C、图12D、图13C和图13D沿着图1所示的参考横截面C-C示出,不同在于不同区域中的多个鳍/FinFET。
在图2中,提供衬底50。衬底50可以是半导体衬底,例如,体(bulk)半导体、绝缘体上半导体(SOI)衬底等,其可以是掺杂的(例如,掺杂有p型或n型掺杂剂)或未掺杂的。衬底50可以是晶圆,例如,硅晶圆。通常,SOI衬底是在绝缘体层上形成的半导体材料层。例如,绝缘体层可以是掩埋氧化物(BOX)层、氧化硅层等。绝缘体层被设置在衬底(通常是硅衬底或玻璃衬底)上。也可以使用其他衬底,例如,多层衬底或梯度衬底。在一些实施例中,衬底50的半导体材料可以包括:硅;锗;化合物半导体,包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟、和/或锑化铟;合金半导体,包括硅锗、磷化镓砷、砷化铝铟、砷化铝镓、砷化镓铟、磷化镓铟和/或磷砷化镓铟;或其组合。
衬底50具有n型区域50N和p型区域50P。n型区域50N可用于形成n型器件,例如,NMOS晶体管(例如,n型FinFET)。p型区域50P可用于形成p型器件,例如,PMOS晶体管(例如,p型FinFET)。n型区域50N可以与p型区域50P实体分离(如分隔符51所示),并且可以在n型区域50N和p型区域50P之间设置任何数量的器件特征(例如,其他有源器件、掺杂区域、隔离结构等)。
在图3中,在衬底50中形成鳍52。鳍52是半导体条带。在一些实施例中,可以通过在衬底50中蚀刻沟槽来在衬底50中形成鳍52。该蚀刻可以是任何可接受的蚀刻工艺,例如,反应离子蚀刻(RIE)、中性束蚀刻(NBE)等、或其组合。该蚀刻可以是各向异性的。
可以通过任何合适的方法来对鳍进行图案化。例如,可使用一个或多个光刻工艺(包括双图案化工艺或多图案化工艺)来对鳍52进行图案化。通常,双图案化工艺或多图案化工艺组合光刻工艺和自对准工艺,允许创建具有例如比使用单个直接光刻工艺可获得的间距更小的间距的图案。例如,在一个实施例中,在衬底之上形成牺牲层,并使用光刻工艺对牺牲层进行图案化。使用自对准工艺在经图案化的牺牲层旁边形成间隔件。然后去除牺牲层,并且然后可以使用剩余的间隔件来对鳍进行图案化。在一些实施例中,掩模(或其他层)可保留在鳍52上。
在图4中,在衬底50之上并且相邻的鳍52之间形成绝缘材料54。绝缘材料54可以是氧化物(例如,氧化硅)、氮化物等、或其组合,并且可以通过以下方式而形成:高密度等离子体化学气相沉积(HDP-CVD)、可流动CVD(FCVD)(例如,远程等离子体系统中的基于CVD的材料沉积和后固化以使其转换成另一种材料(例如,氧化物))等、或其组合。可以使用通过任何可接受的工艺形成的其他绝缘材料。在所示的实施例中,绝缘材料54是通过FCVD工艺形成的氧化硅。一旦形成绝缘材料,就可以执行退火工艺。在实施例中,绝缘材料54被形成为使得过量的绝缘材料54覆盖鳍52。尽管绝缘材料54被示为单个层,但一些实施例可以利用多个层。例如,在一些实施例中,可以首先沿着衬底50和鳍52的表面形成衬里(未示出)。此后,可以在衬里之上形成诸如上述填充材料之类的填充材料。
在图5中,去除工艺被应用于绝缘材料54以去除鳍52之上的过量的绝缘材料54。在一些实施例中,可以利用诸如化学机械抛光(CMP)、回蚀刻工艺、其组合等之类的平坦化工艺。该平坦化工艺暴露鳍52,使得在该平坦化工艺完成之后,鳍52和绝缘材料54的顶表面是齐平的。在其中掩模保留在鳍52上的实施例中,该平坦化工艺可以暴露掩模或去除掩模,使得在该平坦化工艺完成之后,掩模或鳍52以及绝缘材料54的顶表面分别齐平。
在图6中,绝缘材料54被凹陷以形成浅沟槽隔离(STI)区域56。绝缘材料54被凹陷为使得n型区域50N和p型区域50P中的鳍52的上部从相邻的STI区域56之间突出。此外,STI区域56的顶表面可以具有平坦表面(如图所示)、凸表面、凹表面(例如,碟形)、或其组合。STI区域56的顶表面可以通过适当的蚀刻而被形成为平坦的、凸的、和/或凹的。可以使用可接受的蚀刻工艺来凹陷STI区域56,例如,对绝缘材料54的材料具有选择性的蚀刻工艺(例如,以比鳍52的材料更快的速率蚀刻绝缘材料54的材料)。例如,可以使用采用例如稀氢氟(dHF)酸的氧化物去除。
参考图2至图6描述的工艺仅是可以如何形成鳍52的一个示例。在一些其他实施例中,鳍可以通过外延生长工艺来形成。例如,可以在衬底50的顶表面之上形成电介质层,并且可以穿过电介质层蚀刻沟槽以暴露下面的衬底50。可以在沟槽中外延生长同质外延结构,并且该电介质层可被凹陷以使得该同质外延结构从电介质层突出以形成鳍。此外,在一些实施例中,异质外延结构可以用于鳍52。例如,图5中的鳍52可被凹陷,并且可以在经凹陷的鳍52之上外延生长与鳍52不同的材料。在这样的实施例中,鳍52包括凹陷材料,以及布置在凹陷材料之上的外延生长材料。在另一实施例中,可以在衬底50的顶表面之上形成电介质层,并且可以穿过该电介质层蚀刻沟槽。然后可以使用与衬底50不同的材料来在沟槽中外延生长异质外延结构,并且电介质层可被凹陷以使得异质外延结构从电介质层突出以形成鳍52。在其中同质外延或异质外延结构被外延生长的一些实施例中,外延生长的材料可以在生长期间被原位掺杂,这可以避免之前和之后的注入,但原位掺杂和注入掺杂可被一起使用。
更进一步地,在其中期望异质外延结构的一些实施例中,与n型区域50N中的材料不同,可以外延生长第二半导体材料59而作为p型区域50P中的鳍52的一部分。例如,p型区域50P中的鳍52的上部可以由硅锗(SixGe1-x,其中x可以在0到1的范围内)、碳化硅、纯的或基本上纯的锗、III-V族化合物半导体、II-VI族化合物半导体等形成。例如,用于形成III-V族化合物半导体的可用材料包括但不限于:砷化铟、砷化铝、砷化镓、磷化铟、氮化镓、砷化铟镓、砷化铟铝、锑化镓、锑化铝、磷化铝、磷化镓等。然而,可以使用任何合适的材料和任何合适的工艺。
进一步参考图6,可以在鳍52和/或衬底50中形成适当的阱(未示出)。在一些实施例中,可以在n型区域50N中形成P阱,并且可以在p型区域50P中形成N阱。在一些实施例中,在n型区域50N和p型区域50P二者中形成P阱或N阱。
在具有不同阱类型的实施例中,可以使用光致抗蚀剂和/或其他掩模(未示出)来实现用于n型区域50N和p型区域50P的不同注入步骤。例如,可以在n型区域50N中的鳍52和STI区域56之上形成光致抗蚀剂。对光致抗蚀剂进行图案化以暴露衬底50的p型区域50P。可以通过使用旋涂技术来形成光致抗蚀剂,并且可以使用可接受的光刻技术对光致抗蚀剂进行图案化。一旦光致抗蚀剂被图案化,则在p型区域50P中执行n型杂质注入,并且光致抗蚀剂可以用作掩模以基本上防止n型杂质被注入到n型区域50N中。n型杂质可以是注入到该区域中的磷、砷、锑等,其浓度等于或小于1018cm-3,例如,在约1016cm-3与约1018cm-3之间。在注入之后,例如通过可接受的灰化工艺来去除光致抗蚀剂。
在p型区域50P的注入之后,在p型区域50P中的鳍52和STI区域56之上形成光致抗蚀剂。对光致抗蚀剂进行图案化以暴露衬底50的n型区域50N。可以通过使用旋涂技术来形成光致抗蚀剂,并且可以使用可接受的光刻技术对光致抗蚀剂进行图案化。一旦光致抗蚀剂被图案化,则可以在n型区域50N中执行p型杂质注入,并且光致抗蚀剂可以用作掩模以基本上防止p型杂质被注入到p型区域50P中。p型杂质可以是注入到该区域中的硼、氟化硼、铟等,其浓度等于或小于1018cm-3,例如,在约1016cm-3和约1018cm-3之间。在注入之后,可以例如通过可接受的灰化工艺来去除光致抗蚀剂。
在n型区域50N和p型区域50P的注入之后,可以执行退火以修复注入损伤并激活被注入的p型和/或n型杂质。在一些实施例中,外延鳍的生长材料可以在生长期间被原位掺杂,这可以避免注入,但原位掺杂和注入掺杂可一起使用。
在图7中,在鳍52上形成虚设电介质层60。例如,虚设电介质层60可以是氧化硅、氮化硅、其组合等,并且可以根据可接受的技术来沉积或热生长。在虚设电介质层60之上形成虚设栅极层62,并且在虚设栅极层62之上形成掩模层64。虚设栅极层62可被沉积在虚设电介质层60之上,并然后例如通过CMP来平坦化。掩模层64可被沉积在虚设栅极层62之上。虚设栅极层62可以是导电材料或非导电材料,并且可以选自包括如下项的组:非晶硅、多晶硅(polysilicon)、多晶硅锗(poly-SiGe)、金属氮化物、金属硅化物、金属氧化物和金属。虚设栅极层62可以通过物理气相沉积(PVD)、CVD、溅射沉积、或用于沉积所选材料的其他技术来沉积。虚设栅极层62可以由相对于隔离区域(例如,STI区域56和/或虚设电介质层60)的蚀刻具有高蚀刻选择性的其他材料制成。例如,掩模层64可包括一层或多层氮化硅、氮氧化硅等。在该示例中,跨n型区域50N和p型区域50P形成单个虚设栅极层62和单个掩模层64。注意,仅出于说明的目的,虚设电介质层60被示为仅覆盖鳍52。在一些实施例中,虚设电介质层60可被沉积为使得虚设电介质层60覆盖STI区域56,在STI区域之上以及在虚设栅极层62和STI区域56之间延伸。
图8A至图19B示出了制造实施例器件的各种附加步骤,其中为了方便起见,仅示出了n型区域50N中的单个鳍52以及p型区域50P中的单个鳍52。在图8A和图8B中,可以使用可接受的光刻和蚀刻技术来图案化掩模层64(参见图7)以形成掩模74。然后可以将掩模74的图案转移到虚设栅极层62以形成虚设栅极72。在一些实施例中(未示出),还可以将掩模74的图案转移到虚设电介质层60。虚设栅极72覆盖鳍52的相应的沟道区域58。掩模74的图案可用于将每个虚设栅极72与相邻的虚设栅极实体分开。虚设栅极72还可以具有与相应的外延鳍52的长度方向基本上垂直的长度方向。
图8C和图8D示出了鳍52的沿着线C-C(参见图1)的截面图,其中图8C示出了位于n型区域50N内的视图,并且图8D示出了位于p型区域50P内的视图。从制造工艺的这一点可以看出,p型区域50P中的鳍52的半导体材料的顶部已被第二半导体材料59代替。另外,即使在虚设栅极72(参见图8A-8B)的图案化之后,掩模74的一部分仍可以位于沿着鳍52的侧壁。
图9A-9D示出了一旦虚设栅极72已被图案化,则可以在虚设栅极72之上沉积第一密封件73(或第一间隔件)。在实施例中,第一密封件73可以是诸如SiCON之类的电介质材料,其被制造为不仅具有与虚设栅极72相邻的第一外壳81以助于第一密封件73减少蚀刻损失,而且还具有与第一外壳81相邻的第一体(bulk)电介质材料83以减小器件的有效电容(Ceff),以便提高器件的整体性能。然而,可以利用任何配置的任何合适数量的层。
在实施例中,使用诸如原子层沉积之类的沉积工艺来沉积第一密封件73的第一外壳81,但也可以利用任何合适的沉积工艺,例如,化学气相沉积、物理气相沉积等。在这样的使用原子层沉积的实施例中,将多个前体顺序地引入到结构(在各种前体之间进行适当的吹扫(purge)),这些前体将各自在自限反应(self-limiting reaction)中反应,从而循环地以逐个单层的方式形成期望材料(例如,SiCON)的各个层。
在其中第一外壳81是使用原子层沉积而由SiCON形成的具体实施例中,第一前体可以是含硅前体,例如,六氯乙硅烷。在该实施例中,可以将六氯乙硅烷引入到结构,其中,六氯乙硅烷将在自限反应中与结构的表面上的暴露部位进行反应。在这样的实施例中,可以在约20秒(+/-15秒)的时间内以约0.2slm和约1.0slm之间的流速将六氯乙硅烷引入到结构。此外,反应期间的温度可保持在约500℃和约680℃之间的温度。然而,可以利用任何合适的工艺参数。
第二前体可以是诸如丙烷之类的含碳前体,并且第二前体可以在引入第一前体之后被引入到结构。在引入时,第二前体(例如,丙烷)将在另一自限反应中与六氯乙硅烷反应的产物进行反应。在这样的实施例中,可以在约90秒(+/-30秒)的时间内以约0.5slm和约5.0slm之间的流速引入丙烷。此外,反应期间的温度可保持在约500℃和约680℃之间的温度。然而,可以利用任何合适的工艺参数。
第三前体可以是诸如氧(O2)之类的含氧前体,并且第三前体可以在引入第二前体之后被引入到结构。在引入到结构时,第三前体(例如,氧)将在另一自限反应中与先前反应的产物进行反应。在这样的实施例中,可以在约15秒(+/-10秒)的时间内以约1slm和约5slm之间的流速引入氧。此外,反应期间的温度可保持在约500℃和约680℃之间的温度。然而,可以利用任何合适的工艺参数。
第四前体可以是诸如氨之类的含氮前体,并且第四前体可以在引入第三前体之后被引入到结构。在引入到结构时,第四前体(例如,氨)将在另一自限反应中与先前反应的产物进行反应。在这样的实施例中,可以在约30秒(+/-15秒)的时间内以约0.5slm和约5.0slm之间的流速引入氨。此外,反应期间的温度可保持在约500℃和约680℃之间的温度。然而,可以利用任何合适的工艺参数。
一旦第一次引入了第四前体,则原子层沉积工艺的第一循环已经完成,并且可以开始第二循环以便形成期望材料的第二单层。循环可以根据需要重复多次,以便将第一外壳81形成为期望厚度,例如,在约0.2nm和约1nm之间。然而,可以利用任何合适的厚度。
通过如上所述形成第一密封件73的第一外壳81,第一外壳可被形成为更能抵抗来自随后的蚀刻工艺(下文进一步描述)的损坏。例如,在最终产品中,第一外壳81可形成为具有约2.5g/cm3和约2.7g/cm3之间的密度,以及约5.1和约5.5之间的介电常数。此外,利用如上所述的工艺条件,第一密封件73的第一外壳81可形成为富含碳和富含氮,其中碳浓度在约5%原子和约20%原子之间(例如,12%原子)并且氮浓度在约24%原子和约45%原子之间(例如,25%原子)。此外,第一外壳81可具有在约24%原子和约40%原子之间(例如,32%原子)的氧浓度,以及在约27%原子和约37%原子之间(例如,32%原子)的硅浓度。然而,可以利用任何合适的特性。
一旦形成了第一密封件73的第一外壳81,则第一体电介质材料83可以与第一外壳81原位沉积。在实施例中,第一体电介质材料83可以是与第一外壳81类似的材料,例如,通过是具有不同成分的同一材料。例如,在其中第一密封件73的第一外壳81是SiCON的实施例中,第一体电介质材料83也可以是SiCON,但具有不同的成分以有助于降低第一密封件73的介电常数。
在实施例中,可以使用与第一外壳81类似的工艺来沉积第一体电介质材料83,例如,利用类似前体的原子层沉积,如第一前体(例如,六氯乙硅烷)、第二前体(例如,丙烷)、第三前体(例如,氧)和第四前体(例如,氨)。然而,为了具有不同的成分,修改了每种前体被允许接触结构的时间量,使得第一组暴露时间与一组新的暴露时间不同。此外,在其他实施例中,也可以改变前体的顺序。
在一个特定示例中,为了形成第一体电介质材料83,可以在约20秒(+/-8秒)的时间内以约0.2slm和约1.0slm之间的流速引入第一前体,而可以在约90秒(+/-30秒)的时间内以约0.5slm和约5.0slm之间的流速引入第二前体。此外,在引入第三前体(例如,氧)之前,可以在约9秒(+/-5秒)的时间内以约0.5slm和约5.0slm之间的流速引入第四前体(例如,氮)。最后,在第四前体(例如,氮)之后,可以在约18秒(+/-10秒)的时间内以约0.5slm和约5.0slm之间的流速引入第三前体(例如,氧)。然而,可以利用任何合适的流速和时间。
一旦第一次引入了第四前体,则原子层沉积工艺的第一循环已经完成,并且可以开始第二循环以形成期望材料的第二单层。循环可以根据需要重复多次,以将第一体电介质材料83形成为期望厚度,例如,在约3nm和约5nm之间。然而,可以利用任何合适的厚度。
通过利用这些参数,第一体电介质材料83可形成有如下特性:更适合于降低介电常数,同时不像第一外壳81那样抵抗蚀刻工艺。例如,在最终产品中,第一体电介质材料83可形成为具有小于约5.0的介电常数。此外,第一体电介质材料83可形成为具有约2.0g/cm3和约2.4g/cm3之间的密度,并且可以是富氧膜,其中氧浓度在约40%原子和约65%原子之间(例如,53%原子,大于第一外壳81的氧含量)。最终,第一体电介质材料83可具有小于2%原子的碳浓度(例如,1%原子,小于第一外壳81的碳含量)、在约5%原子和约14%原子之间(例如,12%原子)的氮浓度、以及在约24%原子和约40%原子之间(例如,32%原子)的硅浓度。然而,可以利用任何合适的特性。
通过沉积第一外壳81和第一体电介质材料83,第一密封件73可沉积有这样的材料,这些材料允许第一密封件73既具有抗蚀刻部分(例如,第一外壳81)又具有电介质减小部分(例如,第一体电介质材料83)。此外,第一密封件73可具有梯度区域,其中,两个层部分地扩散到彼此中约0.5nm和约1nm之间。这样的布置允许整个第一密封件73在不完全牺牲较低介电常数的情况下具有期望的抗蚀刻破坏性,使得在制造工艺期间可出现较少缺陷。
在形成第一密封件73之后,可以执行用于轻掺杂源极/漏极(LDD)区域(未明确示出)的注入。在具有不同器件类型的实施例中,类似于以上图6中讨论的注入,可以在n型区域50N之上形成掩模(例如,光致抗蚀剂),同时暴露p型区域50P,并且可以将适当类型(例如,p型)的杂质注入到p型区域50P中的暴露的鳍52中。然后可以去除掩模。随后,可以在p型区域50P之上形成掩模(例如,光致抗蚀剂),同时暴露n型区域50N,并且可以将适当类型(例如,n型)的杂质注入到n型区域50N中的暴露的鳍52中。然后可以去除掩模。n型杂质可以是任何先前讨论的n型杂质,并且p型杂质可以是任何先前讨论的p型杂质。轻掺杂源极/漏极区域可以具有从约1015cm-3至约1019cm-3的杂质浓度。可以使用退火来修复注入损坏并激活所注入的杂质。
在已形成LDD区域之后,在第一密封件73之上形成第二密封件75。在实施例中,第二密封件75可以由与第一密封件73相似的材料并使用与第一密封件73相似的工艺来形成。例如,第二密封件75可以由SiCON形成,并且还可以包括第二体电介质材料85和第二外壳87。然而,可以利用任何合适的材料。
在实施例中,第二体电介质材料85可以如以上参考第一体电介质材料83所述而被原位沉积,以获得类似的物理特性。然而,第二体电介质材料85在沉积第二外壳87之前被沉积,使得第二体电介质材料85与第一体电介质材料83实体接触。
例如,在一些实施例中,在最终产品中,第二体电介质材料85可形成为约3nm和约5nm之间的厚度。此外,第二体电介质材料85可形成为约2.0g/cm3和约2.4g/cm3之间的密度,并且可以是富氧膜,其中氧浓度在约40%和约65%之间。最终,第二体电介质材料85可具有小于2%的碳浓度,以及约5%和约12%之间的氮浓度。然而,可以利用任何合适的成分。
一旦第二体电介质材料85已形成为与第一体电介质材料83实体接触,则可以沉积第二外壳87,以便保护第二体电介质材料85在随后的蚀刻工艺期间不受损坏。在实施例中,第二体电介质材料85可以如以上参考第一外壳81的沉积所述而沉积。
例如,在实施例中,可形成第二外壳87以抵抗蚀刻损伤。在一个特定实施例中,在最终产品中,第二外壳87可形成为约0.2nm和约1nm之间的厚度,并且可形成为具有在约2.5g/cm3和约2.7g/cm3之间的密度。此外,利用如上所述的工艺条件,第二外壳87可形成为富含碳和富含氮,其中碳浓度在约5%原子和约20%原子之间(例如,12%原子),并且氮浓度在约24%原子和约45%原子之间(例如,25%原子)。此外,第二外壳87与第二体电介质材料85之间的梯度区域,第二密封件75可具有梯度区域,其中,两个层部分地扩散到彼此中约0.5nm和约1nm之间。然而,可以利用任何合适的浓度。
通过沉积第二外壳87和第二体电介质材料85,第二密封件75可沉积有这样的材料,这些材料允许第二密封件75既具有抗蚀刻部分(例如,第二外壳87)又具有电介质减少部分(例如,第二体电介质材料85)。这样的特性分布允许增加抵抗随后的蚀刻的总体能力,同时还保持介电常数较低。
此外,尽管以上描述了其中形成第一密封件73、形成LDD区域、并然后在形成LDD区域之后形成第二密封件75的特定实施例,但这旨在是示例性的,并且不旨在进行限制。例如,在其他实施例中,第一密封件73和第二密封件75被原位且背对背(back to back)形成,并且仅在形成第二密封件75之后形成LDD区域。可以利用的任何适当的步骤组合,并且所有这样的实施例完全旨在包括在实施例的范围内。
图9A-9D还示出了一旦已经沉积第二密封件75,则在结构之上沉积掩模层77。在实施例中,掩模层77可以是使用诸如原子层沉积、化学气相沉积、溅射、这些项的组合等之类的沉积工艺而沉积的电介质层,例如,氮化硅、氧化铝。然而,可以利用任何合适的材料和制造方法。
在图10A-10D中,在p型FinFET的鳍52中形成外延源极/漏极区域82。在鳍52中形成外延源极/漏极区域82,使得每个虚设栅极72被设置在外延源极/漏极区域82的相应的相邻对之间。在一些实施例中,外延源极/漏极区域82可以延伸到鳍52中,并且还可以穿过鳍52。在一些实施例中,第一密封件73和第二密封件75被用于将外延源极/漏极区域82与虚设栅极72分隔开适当的横向距离,使得外延源极/漏极区域82不会使所得的FinFET的随后形成的栅极短路。可以选择外延源极/漏极区域82的材料以在相应的沟道区域58中施加应变,从而提高性能。
p型区域50P中的外延源极/漏极区域82可以通过掩蔽p型区域50P内的虚设栅极72以及n型区域50N,并进行蚀刻以暴露下面的鳍52(例如,第二半导体材料59)来形成。然后,在鳍52上外延生长p型区域50P中的外延源极/漏极区域82。外延源极/漏极区域82可以包括任何可接受的材料,例如,适合于p型FinFET的材料。例如,如果鳍52是硅锗,则p型区域50P中的外延源极/漏极区域82可以包括在沟道区域58中施加应变的材料,例如,硅、掺杂硼的硅锗、硅锗、锗锡等。p型区域50P中的外延源极/漏极区域82可以具有从鳍52的相应表面凸起的表面,并且可以具有小平面(facet)。
一旦形成了外延源极/漏极区域82,则可以去除掩模层77的任何剩余部分(例如,利用诸如H3PO4之类的蚀刻剂)。在实施例中,可以使用例如一个或多个蚀刻工艺(例如,湿法蚀刻工艺)来去除掩模层77的剩余部分。然而,可以利用任何合适的方法。在一些实施例中,多次蚀刻工艺(例如,去除鳍52的蚀刻和/或去除掩模层77的蚀刻)可以进一步去除第一密封件73和第二密封件75的部分至低于掩模74的位置。
图11A-11D示出了一旦已经在p型区域50P中形成外延源极/漏极区域82,则形成第二掩模层79以开始形成n型区域50N中的外延源极/漏极区域84。在实施例中,可以使用与掩模层77相似的工艺和相似的材料来形成第二掩模层79。然而,可以利用任何合适的方法和材料。
图12A至图12D示出了一旦形成第二掩模层79,则暴露n型区域50N中的鳍52,并且在鳍52上外延生长n型区域50N中的外延源极/漏极区域84。外延源极/漏极区域84可以包括任何可接受的材料,例如,适合于n型FinFET的材料。例如,如果鳍52是硅,则n型区域50N中的外延源极/漏极区域84可以包括在沟道区域58中施加拉伸应变的材料,例如,硅、碳化硅、掺杂磷的碳化硅、硅磷等。n型区域50N中的外延源极/漏极区域84可以具有从鳍52的相应表面凸起的表面,并且可以具有小平面。
一旦形成了外延源极/漏极区域84,则可以去除第二掩模层79的任何剩余部分。在实施例中,可以使用例如一个或多个蚀刻工艺(例如,湿法蚀刻工艺)来去除第二掩模层79的剩余部分。然而,可以利用任何合适的方法。在一些实施例中,多次蚀刻工艺(例如,去除鳍52的蚀刻、去除掩模层77的蚀刻)可以进一步去除第一密封件73和第二密封件75的部分至低于掩模74的位置。
此外,尽管以上描述了其中在鳍52上形成外延源极/漏极区域84和外延源极/漏极区域82的特定实施例,但这旨在是示例性的而不旨在是限制性的。相反,可以利用任何合适的工艺,例如,暴露鳍52,使鳍52凹陷,并且然后在凹槽中重新生长外延源极/漏极区域84和外延源极/漏极区域82。所有这样的工艺都应完全包括在实施例中。
可以用掺杂剂注入外延源极/漏极区域84和/或鳍52以形成源极/漏极区域,类似于先前讨论的用于形成轻掺杂源极/漏极区域的工艺,然后进行退火。源极/漏极区域可具有约1019cm-3和约1021cm-3之间的杂质浓度。用于源极/漏极区域的n型和/或p型杂质可以是任何前面讨论的杂质。在一些实施例中,外延源极/漏极区域84可以在生长期间被原位掺杂。
作为用于形成p型区域50P中的外延源极/漏极区域82以及n型区域50N中的外延源极/漏极区域84的外延工艺的结果,外延源极/漏极区域的上表面具有横向向外扩展超过鳍52的侧壁的小平面。在一些实施例中,这些小平面可使得同一FinFET的相邻的源极/漏极区域合并。在其他实施例中,相邻的源极/漏极区域在外延工艺完成之后保持分离。
在用于暴露和/或凹陷鳍52以便形成LDD区域以及外延源极/漏极区域82和外延源极/漏极区域84的所有蚀刻工艺期间,第一密封件73和第二密封件75的壳体用于保护第一密封件73和第二密封件75的内部部分(至少将保留在最终产品中的那些部分)。例如,尽管可以使用诸如硫酸(H2SO4)、过氧化物(H2O2)、稀氢氟酸(dHF)和氧等离子体之类的蚀刻剂来蚀刻、灰化、或以其他方式去除结构的部分,但第一外壳81和第二外壳87将用于夹住并保护第一体电介质材料83和第二体电介质材料85免受那些蚀刻剂的影响。此外,然而,尽管第二外壳87用于在蚀刻工艺期间保护内部材料,但第二外壳87的一部分本身可能在蚀刻工艺期间被蚀刻和/或损坏。
这样,图13A-13D示出了可以使用接触蚀刻停止层(CESL)97来补充第二密封件75的外层的工艺。在该实施例中,一旦已经形成了外延源极/漏极区域82和外延源极/漏极区域84并且已经执行了使用稀氢氟酸的可选预清洁(例如,在1:100下进行60秒),则接触蚀刻停止层(CESL)97被沉积在结构之上,并且与第二密封件75的第二外壳87实体接触。在实施例中,CESL 97可类似于第一密封件73和第二密封件75,例如,通过使第三体电介质材料91邻近第二密封件75而沉积,并且第三外壳93临近第三体电介质材料91。
在实施例中,可以如以上参考第一体电介质材料83和第二体电介质材料85所述来形成第三体电介质材料91,以获得类似的物理特性。例如,在最终产品中,第三体电介质材料91可形成为约1.0nm和约3.5nm之间的厚度。此外,第三体电介质材料91可形成为约2.0g/cm3和约2.4g/cm3之间的密度,并且可以是富氧膜,其中氧浓度在约40%原子和约65%原子之间。最终,第三体电介质材料91可具有小于2%原子的碳浓度,以及约5%原子和约12%原子之间的氮浓度。然而,可以利用任何合适的成分。
一旦已经形成第三体电介质材料91,则可以在第三体电介质材料91之上沉积第三外壳93。在实施例中,第三外壳93可被沉积为可用于辅助保护下面的层(例如,第三体电介质材料91)免于随后的蚀刻工艺的电介质。这样,在特定实施例中,第三外壳93可以是使用诸如原子层沉积、化学气相沉积、物理气相沉积、这些项的组合等之类的沉积工艺而沉积的电介质材料,例如,氮化硅。此外,第三体电介质材料91可形成为约1.5nm和约4.0nm之间的厚度。然而,可以利用任何合适的电介质材料和厚度。
通过沉积第三外壳93和第三体电介质材料91,CESL 97可沉积有这样的材料:这些材料允许CESL 97既具有抗蚀刻部分(例如,第三外壳93)又具有电介质减小部分(例如,第三体电介质材料91)。此外,CESL 97可具有由沉积工艺期间的循环而导致的约0.5nm和约2.0nm之间的梯度区域。
通过形成第一密封件73、第二密封件75和CESL 97,多层间隔件95(包括第一密封件73、第二密封件75和CESL 97)可形成为约4.5nm和约8.0nm之间的厚度。此外,多层间隔件95提供增强的抗蚀刻性(特别是对于诸如等离子体O2灰化、硫酸、过氧化氢、稀氢氟酸和磷酸之类的蚀刻剂),同时仍保持合适的介电常数并具有大的间隔件一致性(例如,在大于20的纵横比的情况下,<=95%的内部间隔件一致性)。在一些实施例中,间隔件的总介电常数可以在约4.2和约5.5之间。此外,通过如上所述彼此原位地形成各个层,在不同的膜之间未形成层间氧化膜。通过形成所述的层,总Ceff(RO%)可以增加约1%和约2%之间。
在图14A和图14B中,第一层间电介质(ILD)88被沉积在图13A和图13B所示的结构之上。第一ILD 88可以由电介质材料形成,并且可以通过诸如CVD、等离子体增强CVD(PECVD)、或FCVD之类的任何合适的方法来沉积。电介质材料可包括磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、掺杂硼的磷硅酸盐玻璃(BPSG)、未掺杂的硅酸盐玻璃(USG)等。可以使用通过任何可接受的工艺形成的其他绝缘材料。
一旦已经沉积了第一ILD 88,则可以利用退火工艺来致密第一ILD 88的材料。在实施例中,退火工艺可以是湿法退火,其中,第一ILD 88在含水分环境中在约400℃和约600℃之间的温度下被加热约0.5小时和约3小时之间的时间,并且然后在约500℃和约700℃之间的温度下被干燥约0.5小时和约3小时之间的时间。然而,可以利用任何合适的时间和温度。
在图15A和图15B中,可以执行平坦化工艺(例如,CMP)以使第一ILD 88的顶表面与虚设栅极72或掩模74的顶表面齐平。该平坦化工艺还可以去除虚设栅极72上的掩模74,以及第一密封件73、第二密封件75和CESL 97的沿着掩模74的侧壁的部分。在该平坦化工艺之后,虚设栅极72、第一密封件73、第二密封件75、CESL 97和第一ILD 88的顶表面是齐平的。因此,虚设栅极72的顶表面通过第一ILD 88而暴露。在一些实施例中,掩模74可保留,在这种情况下,该平坦化工艺使第一ILD 88的顶表面与掩模74的顶表面齐平。
在图16A和图16B中,在(一个或多个)蚀刻步骤中去除虚设栅极72和掩膜74(如果存在的话),从而形成凹槽90。虚设电介质层60的在凹槽90中的部分也可以被去除。在一些实施例中,仅虚设栅极72被去除,并且虚设电介质层60保留并由凹槽90暴露。在一些实施例中,虚设电介质层60从管芯的第一区域(例如,核心逻辑区域)中的凹槽90去除,并在管芯的第二区域(例如,输入/输出区域)的凹槽90中保留。在一些实施例中,通过各向异性干法蚀刻工艺去除虚设栅极72。例如,蚀刻工艺可包括使用(一种或多种)反应气体(例如,氨(NH3)和氢氟酸(HF))的干法蚀刻工艺,该(一种或多种)反应气体选择性地蚀刻虚设栅极72而较少蚀刻或不蚀刻第一ILD 88或多层间隔件95。每个凹槽90暴露和/或上覆于相应的鳍52的沟道区域58。每个沟道区域58被设置在外延源极/漏极区域82或外延源极/漏极区域84的相邻对之间。在去除期间,虚设电介质层60可以在蚀刻虚设栅极72时用作蚀刻停止层。然后在去除虚设栅极72之后可以可选地去除虚设电介质层60。
然而,在形成凹槽90时,抗蚀刻的第一外壳81的存在有助于减少对多层间隔件95的其余部分的损坏。例如,在去除虚设电介质层60期间第一外壳81可损失少于的材料(而其他材料可能损失超过),而仍保护第一体电介质材料83的材料(其可能损失高达)。对多层间隔件95的这种保护具有使LDD区域的损失最小化的附加益处,该LDD区域的损失将仅为或更少。
在图17A和图17B中,形成栅极电介质层92和栅极电极94以用于替换栅极。图17C示出了图17B的区域89的详细视图。栅极电介质层92的一层或多层被沉积在凹槽90中,例如,在鳍52的顶表面和侧壁上以及在多层间隔件95的侧壁上。栅极电介质层92还可以形成在第一ILD 88的顶表面上。在一些实施例中,栅极电介质层92包括一个或多个电介质层,例如,一层或多层氧化硅、氮化硅、金属氧化物、金属硅酸盐等。例如,在一些实施例中,栅极电介质层92包括通过热氧化或化学氧化而形成的氧化硅的界面层,以及上覆的高k电介质材料,例如,铪、铝、锆、镧、锰、钡、钛、铅及其组合的金属氧化物或硅酸盐。栅极电介质层92可以包括k值大于约7.0的电介质层。栅极电介质层92的形成方法可以包括分子束沉积(MBD)、ALD、PECVD等。在其中虚设电介质层60的部分保留在凹槽90中的实施例中,栅极电介质层92包括虚设电介质层60的材料(例如,SiO2)。
栅极电极94被分别沉积在栅极电介质层92之上,并填充凹槽90的其余部分。栅极电极94可包括含金属材料,例如,氮化钛、氧化钛、氮化钽、碳化钽、钴、钌、铝、钨、其组合、或其多层。例如,尽管在图17B中示出了单层栅极电极94,但栅极电极94可包括任何数量的衬里层94A、任何数量的功函数调整层94B、以及填充材料94C,如图17C所示。在填充凹槽90之后,可以执行诸如CMP之类的平坦化工艺,以去除栅极电极94的材料和栅极电介质层92的多余部分,这些多余部分在第一ILD 88的顶表面之上。栅极电极94的材料和栅极电介质层92的剩余部分因此形成所得FinFET的替换栅极。栅极电极94和栅极电介质层92可被统称为“栅极堆叠”,并且该栅极堆叠可具有约10nm和约20nm之间的栅极高度,并且栅极电极94可具有约14.5nm和约17nm之间的栅极长度Lg。栅极和栅极堆叠可以沿着鳍52的沟道区域58的侧壁延伸。
n型区域50N和p型区域50P中的栅极电介质层92的形成可以同时发生,使得每个区域中的栅极电介质层92由相同的材料形成,并且栅极电极94的形成可以同时发生,使得每个区域中的栅极电极94由相同的材料形成。在一些实施例中,每个区域中的栅极电介质层92可以通过不同的工艺形成,使得栅极电介质层92可以是不同的材料,和/或每个区域中的栅极电极94可以通过不同的工艺形成,使得栅极电极94可以是不同的材料。当使用不同的工艺时,可以使用各种掩蔽步骤来掩蔽和暴露适当的区域。
在图18A和图18B中,在栅极堆叠(包括栅极电介质层92和相应的栅极电极94)之上形成栅极掩模96,并且栅极掩模可被设置在多层间隔件95的相对部分之间。在一些实施例中,形成栅极掩模96包括使栅极堆叠凹陷,从而在栅极堆叠的正上方以及多层间隔件95的相对部分之间形成凹槽。栅极掩模96包括一层或多层电介质材料,例如,氮化硅、氮氧化硅等,其被填充在凹槽中,然后进行平坦化工艺以去除在第一ILD 88之上延伸的电介质材料的多余部分。
还如图18A和图18B所示,在第一ILD 88之上沉积第二ILD 108。在一些实施例中,第二ILD 108是通过可流动CVD方法形成的可流动膜。在一些实施例中,第二ILD 108由诸如PSG、BSG、BPSG、USG等之类的电介质材料形成,并且可以通过诸如CVD和PECVD之类的任何合适的方法来沉积。后续形成的栅极接触件110(图19A和图19B)穿过第二ILD 108和栅极掩模96,以接触经凹陷的栅极电极94的顶表面。
在图19A和图19B中,根据一些实施例,通过第二ILD 108和第一ILD 88形成栅极接触件110和源极/漏极接触件112。通过第一ILD 88和第二ILD 108形成用于源极/漏极接触件112的开口,并且通过第二ILD108和栅极掩模96形成用于栅极接触件110的开口。可以使用可接受的光刻和蚀刻技术形成开口。在开口中形成诸如扩散阻挡层、粘附层等之类的衬里(未示出),以及导电材料。衬里可包括钛、氮化钛、钽、氮化钽等。导电材料可以是铜、铜合金、银、金、钨、钴、铝、镍等。可以执行诸如CMP之类的平坦化工艺以从第二ILD 108的表面去除多余的材料。剩余的衬里和导电材料在开口中形成源极/漏极接触件112和栅极接触件110。可以执行退火工艺以在外延源极/漏极区域82和外延源极/漏极区域84与源极/漏极接触件112之间的界面处形成硅化物。源极/漏极接触件112实体耦合并电耦合至外延源极/漏极区域82和外延源极/漏极区域84,并且栅极接触件110实体耦合并电耦合至栅极电极94。源极/漏极接触件112和栅极接触件110可以以不同的工艺形成,或者可以以相同的工艺形成。尽管被示出为形成在相同的横截面中,但是应当理解,源极/漏极接触件112和栅极接触件110中的每一个可以形成在不同的横截面中,这可以避免接触件的短路。
通过形成如本文所述的多层间隔件95,可以获得益处。具体地,通过使用其中每一层都包括壳部分和体部分两者的多个层,可以在不过度增加总介电常数的情况下提高抗蚀刻性。这样,将发生较少损坏,并且可以提高器件的整体性能。
在一个实施例中,一种半导体器件包括:第一间隔件层,包括设置在两个外层之间的内层,其中,内层和两个外层各自包括第一材料,其中,两个外层的碳含量大于内层的碳含量,并且两个外层的氧含量小于内层的氧含量;以及第二间隔件层,包括第一层和第二层,第一层是第一材料并且与两个外层之一直接接触。在一个实施例中,第一材料包括SiOCN。在一个实施例中,第二层包括氮化硅。在一个实施例中,第二间隔件层的第一层的碳含量小于约2%。在一个实施例中,两个外层之一的密度在约2.5g/cm3和约2.7g/cm3之间。在一个实施例中,内层的氮浓度在约5%和约12%之间。在一个实施例中,两个外层之一的氮浓度在约25%和约45%之间。
在另一实施例中,一种半导体器件包括:第一密封件,与栅极堆叠相邻,该第一密封件包括:具有第一成分的第一材料的第一壳体;以及具有第二成分的该第一材料的第一体材料,该第二成分不同于第一成分;第二密封件,与第一密封件实体接触,该第二密封件包括:具有第三成分的该第一材料的第二壳体;以及具有第四成分的该第一材料的第二体材料,该第四成分不同于第三成分;以及接触蚀刻停止层,与第二密封件实体接触,该接触蚀刻停止层包括:具有第五成分的该第一材料的第三体材料;以及不同于第一材料的第二材料的第三壳体。在一个实施例中,第一材料包括硅碳氮氧化物(silicon carbonoxynitride)。在一个实施例中,第一成分具有比第二成分更小的氧浓度。在一个实施例中,第一成分具有比第二成分更大的氮浓度。在一个实施例中,第一成分具有比第二成分更大的碳浓度。在一个实施例中,第二材料包括氮化硅。在一个实施例中,第一成分的碳浓度在约5%和约20%之间。
在又一实施例中,一种制造半导体器件的方法包括:在半导体鳍之上图案化虚设栅极电极;使用第一组暴露时间将第一组前体顺序地引入到虚设栅极电极,以形成第一壳层;使用不同于第一组暴露时间的第二组暴露时间将第一组前体顺序地引入到虚设栅极电极,以形成第一体电介质材料;使用第三组暴露时间将第一组前体顺序地引入到虚设栅极电极,以形成第二体电介质材料;使用不同于第一组暴露时间的第四组暴露时间将第一组前体顺序地引入到虚设栅极电极,以形成第二壳层;使用第五组暴露时间将第一组前体顺序地引入到虚设栅极电极,以形成第三体电介质材料;以及在使用第五组暴露时间将第一组前体顺序地引入到虚设栅极电极之后,沉积电介质材料。在一个实施例中,第一壳层是硅碳氮氧化物。在一个实施例中,电介质材料是氮化硅。在一个实施例中,使用第三组暴露时间将第一组前体顺序地引入到虚设栅极电极是在形成轻掺杂源极/漏极区域之后发生的。在一个实施例中,使用第三组暴露时间将第一组前体顺序地引入到虚设栅极电极是在形成轻掺杂源极/漏极区域之前发生的。在一个实施例中,第一壳层具有比第一体电介质材料更高的氮浓度。
以上概述了若干实施例的特征,使得本领域技术人员可以更好地理解本公开的各方面。本领域技术人员应当理解,他们可以容易地使用本公开作为设计或修改其他工艺和结构以实现本文介绍的实施例的相同目的和/或实现本文介绍的实施例的相同优点的基础。本领域技术人员还应该认识到,这样的等同构造不脱离本公开的精神和范围,并且他们可以在不脱离本公开的精神和范围的情况下在本文中进行各种改变、替换和变更。
示例1是一种半导体器件,包括:第一间隔件层,包括设置在两个外层之间的内层,其中,所述内层和所述两个外层各自包括第一材料,其中,所述两个外层的碳含量大于所述内层的碳含量,并且所述两个外层的氧含量小于所述内层的氧含量;以及第二间隔件层,包括第一层和第二层,所述第一层是所述第一材料并且与所述两个外层之一直接接触。
示例2是示例1所述的半导体器件,其中,所述第一材料包括SiOCN。
示例3是示例1所述的半导体器件,其中,所述第二层包括氮化硅。
示例4是示例1所述的半导体器件,其中,所述第二间隔件层的所述第一层的碳含量小于约2%。
示例5是示例1所述的半导体器件,其中,所述两个外层之一的密度在约2.5g/cm3和约2.7g/cm3之间。
示例6是示例1所述的半导体器件,其中,所述内层的氮浓度在约5%和约12%之间。
示例7是示例1所述的半导体器件,其中,所述两个外层之一的氮浓度在约25%和约45%之间。
示例8是一种半导体器件,包括:第一密封件,与栅极堆叠相邻,所述第一密封件包括:具有第一成分的第一材料的第一壳体;以及具有第二成分的所述第一材料的第一体材料,所述第二成分不同于所述第一成分;第二密封件,与所述第一密封件实体接触,所述第二密封件包括:具有第三成分的所述第一材料的第二壳体;以及具有第四成分的所述第一材料的第二体材料,所述第四成分不同于所述第三成分;以及接触蚀刻停止层,与所述第二密封件实体接触,所述接触蚀刻停止层包括:具有第五成分的所述第一材料的第三体材料;以及不同于所述第一材料的第二材料的第三壳体。
示例9是示例8所述的半导体器件,其中,所述第一材料包括硅碳氮氧化物。
示例10是示例8所述的半导体器件,其中,所述第一成分具有比所述第二成分更小的氧浓度。
示例11是示例10所述的半导体器件,其中,所述第一成分具有比所述第二成分更大的氮浓度。
示例12是示例11所述的半导体器件,其中,所述第一成分具有比所述第二成分更大的碳浓度。
示例13是示例12所述的半导体器件,其中,所述第二材料包括氮化硅。
示例14是示例8所述的半导体器件,其中,所述第一成分的碳浓度在约5%和约20%之间。
示例15是一种制造半导体器件的方法,所述方法包括:在半导体鳍之上图案化虚设栅极电极;使用第一组暴露时间将第一组前体顺序地引入到所述虚设栅极电极,以形成第一壳层;使用不同于所述第一组暴露时间的第二组暴露时间将所述第一组前体顺序地引入到所述虚设栅极电极,以形成第一体电介质材料;使用第三组暴露时间将所述第一组前体顺序地引入到所述虚设栅极电极,以形成第二体电介质材料;使用不同于所述第一组暴露时间的第四组暴露时间将所述第一组前体顺序地引入到所述虚设栅极电极,以形成第二壳层;使用第五组暴露时间将所述第一组前体顺序地引入到所述虚设栅极电极,以形成第三体电介质材料;以及在使用所述第五组暴露时间将所述第一组前体顺序地引入到所述虚设栅极电极之后,沉积电介质材料。
示例16是示例15所述的方法,其中,所述第一壳层是硅碳氮氧化物。
示例17是示例16所述的方法,其中,所述电介质材料是氮化硅。
示例18是示例15所述的方法,其中,使用所述第三组暴露时间将所述第一组前体顺序地引入到所述虚设栅极电极是在形成轻掺杂源极/漏极区域之后发生的。
示例19是示例15所述的方法,其中,使用所述第三组暴露时间将所述第一组前体顺序地引入到所述虚设栅极电极是在形成轻掺杂源极/漏极区域之前发生的。
示例20是示例15所述的方法,其中,所述第一壳层具有比所述第一体电介质材料更高的氮浓度。
Claims (10)
1.一种半导体器件,包括:
第一间隔件层,包括设置在两个外层之间的内层,其中,所述内层和所述两个外层各自包括第一材料,其中,所述两个外层的碳含量大于所述内层的碳含量,并且所述两个外层的氧含量小于所述内层的氧含量;以及
第二间隔件层,包括第一层和第二层,所述第一层是所述第一材料并且与所述两个外层之一直接接触。
2.根据权利要求1所述的半导体器件,其中,所述第一材料包括SiOCN。
3.根据权利要求1所述的半导体器件,其中,所述第二层包括氮化硅。
4.根据权利要求1所述的半导体器件,其中,所述第二间隔件层的所述第一层的碳含量小于约2%。
5.根据权利要求1所述的半导体器件,其中,所述两个外层之一的密度在约2.5g/cm3和约2.7g/cm3之间。
6.根据权利要求1所述的半导体器件,其中,所述内层的氮浓度在约5%和约12%之间。
7.根据权利要求1所述的半导体器件,其中,所述两个外层之一的氮浓度在约25%和约45%之间。
8.一种半导体器件,包括:
第一密封件,与栅极堆叠相邻,所述第一密封件包括:
具有第一成分的第一材料的第一壳体;以及
具有第二成分的所述第一材料的第一体材料,所述第二成分不同于所述第一成分;
第二密封件,与所述第一密封件实体接触,所述第二密封件包括:
具有第三成分的所述第一材料的第二壳体;以及
具有第四成分的所述第一材料的第二体材料,所述第四成分不同于所述第三成分;以及
接触蚀刻停止层,与所述第二密封件实体接触,所述接触蚀刻停止层包括:
具有第五成分的所述第一材料的第三体材料;以及
不同于所述第一材料的第二材料的第三壳体。
9.根据权利要求8所述的半导体器件,其中,所述第一材料包括硅碳氮氧化物。
10.一种制造半导体器件的方法,所述方法包括:
在半导体鳍之上图案化虚设栅极电极;
使用第一组暴露时间将第一组前体顺序地引入到所述虚设栅极电极,以形成第一壳层;
使用不同于所述第一组暴露时间的第二组暴露时间将所述第一组前体顺序地引入到所述虚设栅极电极,以形成第一体电介质材料;
使用第三组暴露时间将所述第一组前体顺序地引入到所述虚设栅极电极,以形成第二体电介质材料;
使用不同于所述第一组暴露时间的第四组暴露时间将所述第一组前体顺序地引入到所述虚设栅极电极,以形成第二壳层;
使用第五组暴露时间将所述第一组前体顺序地引入到所述虚设栅极电极,以形成第三体电介质材料;以及
在使用所述第五组暴露时间将所述第一组前体顺序地引入到所述虚设栅极电极之后,沉积电介质材料。
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