CN111223936A - 半导体装置与其形成方法 - Google Patents

半导体装置与其形成方法 Download PDF

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CN111223936A
CN111223936A CN201911184969.8A CN201911184969A CN111223936A CN 111223936 A CN111223936 A CN 111223936A CN 201911184969 A CN201911184969 A CN 201911184969A CN 111223936 A CN111223936 A CN 111223936A
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source
layer
region
gate
drain regions
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徐梓翔
陈定业
李威养
杨丰诚
陈燕铭
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种半导体装置与其形成方法，该半导体装置包括自基板延伸的第一半导体鳍状物与第二半导体鳍状物，以及外延成长于第一半导体鳍状物与第二半导体鳍状物的凹陷中的源极/漏极区。源极/漏极区的上表面高于与第一半导体鳍状物与第二半导体鳍状物的上表面齐平的表面。源极/漏极区包括多个缓冲层。个别的缓冲层埋置于源极/漏极区的个别层之间。缓冲层的每一者的平均厚度可为
Figure DDA0002292162880000011
至
Figure DDA0002292162880000012

Description

半导体装置与其形成方法
技术领域
本发明实施例关于半导体装置，更特别关于外延的源及/漏极区的形成方法。
背景技术
半导体装置用于多种电子应用，比如个人电脑、手机、数码相机、与其他电子设备。半导体装置的制作方法通常为按序沉积绝缘或介电层、导电层、与半导体层的材料于半导体基板上，并采用光刻图案化多种材料层以形成电子构件与单元于基板上。
半导体产业持续减少最小结构尺寸，可持续改良多种电子构件(如晶体管、二极管、电阻、电容、或类似物)的集成密度，以让更多构件整合至给定面积中。然而随着最小结构尺寸缩小，产生需解决的额外问题。
集成电路工艺采用越来越多的鳍状场效晶体管，其具有小尺寸与高效能。完全应变的通道亦改善鳍状场效晶体管的效能，但完全应变的通道结构亦产生需解决的专属问题。
发明内容
本发明一实施例提供的半导体装置，包括：自基板延伸的第一半导体鳍状物与第二半导体鳍状物；栅极，位于第一半导体鳍状物与第二半导体鳍状物上；以及源极/漏极区，位于第一半导体鳍状物与第二半导体鳍状物上并与栅极相邻，其中源极/漏极区的上表面高于栅极下的第一半导体鳍状物与第二半导体鳍状物的上表面，其中源极/漏极区包括多个缓冲层与多个主体层，其中源极/漏极区包括互相交错的缓冲层与主体层，其中缓冲层的每一者的平均厚度为
Figure BDA0002292162860000011
至
Figure BDA0002292162860000012
本发明一实施例提供的半导体装置，包括：自基板凸起的第一半导体鳍状物与第二半导体鳍状物；以及第一源极/漏极区位于第一半导体鳍状物上，与第二源极/漏极区位于第二半导体鳍状物上，其中第一源极/漏极区与第二源极/漏极区分开，其中第一源极/漏极区与第二源极/漏极区的上表面高于第一半导体鳍状物与第二半导体鳍状物的上表面，其中第一源极/漏极区与第二源极/漏极区各自包括：第一缓冲层；第一主体层，位于第一缓冲层上；第二缓冲层，位于第一主体层上；以及第二主体层，位于第二缓冲层上，其中第一缓冲层与第二缓冲层的每一者的平均厚度为
Figure BDA0002292162860000021
至
Figure BDA0002292162860000022
本发明一实施例提供的半导体装置的形成方法，包括：形成自基板凸起的第一半导体鳍状物与第二半导体鳍状物；形成第一栅极结构于第一半导体鳍状物上；使第一半导体鳍状物凹陷，以形成与第一栅极结构相邻的第一凹陷；形成第一源极/漏极区于第一凹陷中，其中形成第一源极/漏极区的步骤包括：外延成长第一主体层于第一凹陷中；外延成长第二主体层于第一主体层上；以及形成一或多个结合层，其中形成每一结合层的步骤包括：外延成长上侧主体层；沉积缓冲层于上侧主体层上；以及使上侧主体层与缓冲层的侧壁凹陷。
附图说明
图1是一些实施例中，鳍状场效晶体管的三维图。
图2至图7图2至图7、图8A至图23A、图8B至图23B、图11C至图17C、图21C、图12D至图17D是一些实施例中，形成鳍状场效晶体管的中间阶段的剖视图。
附图标记说明：
A-A、B-B、C-C 参考剖面
H1 高度
L1、L2 横向距离
W1 宽度
50 基板
50N、50P、89 区域
51 分隔线
52 鳍状物
54 绝缘材料
56 隔离区
58 通道区
60 虚置介电层
62 虚置栅极层
64 遮罩层
70 栅极组件
72 虚置栅极
74 遮罩
80 栅极密封间隔物
81、90 凹陷
82 源极/漏极区
82A 第一层
82B 第二层
82C 第三层
82D 第四层
82E 第五层
84 缓冲层
84A 第一缓冲层
84B 第二缓冲层
84C 第三缓冲层
84D 第四缓冲层
86 栅极间隔物
87 接点蚀刻停止层
88 第一层间介电层
92 栅极介电层
94 栅极
94A 衬垫层
94B 功函数调整层
94C 填充材料
106 栅极
108 第二层间介电层
110 栅极接点
112 源极/漏极接点
具体实施方式
下述内容提供的不同实施例或例子可实施本发明实施例的不同结构。特定构件与排列的实施例是用以简化本公开而非局限本发明。举例来说，形成第一构件于第二构件上的叙述包含两者直接接触，或两者之间隔有其他额外构件而非直接接触。此外，本发明的多种实例可重复采用相同标号以求简洁，但多种实施例及/或设置中具有相同标号的元件并不必然具有相同的对应关系。
此外，空间性的相对用语如「下方」、「其下」、「下侧」、「上方」、「上侧」、或类似用语可用于简化说明某一元件与另一元件在图示中的相对关系。空间性的相对用语可延伸至以其他方向使用的元件，而非局限于图示方向。元件亦可转动90°或其他角度，因此方向性用语仅用以说明图示中的方向。
此处所述的一或多个实施例的有利特征包括源极/漏极区的多次循环外延成长工艺。多次循环成长采用重复的沉积与蚀刻以限制源极/漏极区的水平成长，并增加源极/漏极区的高度。在制作静态随机存取存储器装置时，限制水平成长可避免相邻的源极/漏极区合并。
多次循环的沉积与蚀刻成长源极/漏极区，可增加源极/漏极区的高度。在外延成长源极/漏极区处，源极/漏极区的上表面可高于半导体鳍状物的上表面。多次循环的沉积与蚀刻工艺亦改善源极/漏极区的关键尺寸一致性，并增加源极/漏极区的总体积。源极/漏极区的较高上表面与体积增加，可提供较大体积的源极/漏极区用于电性耦接金属接点，其可降低接点电阻以改善装置效能。
图1显示一些实施例中，鳍状场效晶体管的三维图。鳍状场效晶体管包含基板50(如半导体基板)上的鳍状物52。隔离区56位于基板50中，且鳍状物52自相邻的隔离区56之间凸起高于隔离区56。虽然隔离区56与基板50在附图与说明书中描述为不同单元，但此处所述的用语「基板」可单指半导体基板，或含有隔离区的半导体基板。此外，虽然附图中的鳍状物52与基板50为单一的连续材料，但鳍状物52及/或基板50可包含单一材料或多种材料。在本文中，鳍状物52指的是延伸于相邻的隔离区56之间的部分。
栅极介电层92沿着鳍状物52的上表面与侧壁，而栅极94位于栅极介电层92上。源极/漏极区82位于鳍状物52相对于栅极介电层92与栅极94的两侧中。图1亦显示后续附图所用的参考剖面。参考剖面A-A沿着栅极94的纵轴并垂直于鳍状场效晶体管的源极/漏极区82之间的电流方向。参考剖面B-B垂直于参考剖面A-A，并沿着鳍状物52的长度方向，并在鳍状场效晶体管的源极/漏极区82之间的电流方向中。参考剖面C-C平行于参考剖面A-A，并延伸穿过鳍状场效晶体管的源极/漏极区。后续附图将参考这些参考剖面以清楚说明。
此处所述的一些实施例内容为采用栅极后制工艺形成鳍状场效晶体管。在其他实施例中，可采用栅极优先工艺。此外，一些实施例可实施于平面装置如平面场效晶体管。
图2至图23B是一些实施例中，形成鳍状场效晶体管的中间阶段的剖视图。图2至图7显示沿着图1所示的参考剖面A-A的剖视图，差别在于多个鳍状物及/或鳍状场效晶体管。图8A、图9A、图10A、图11A、图12A、图13A、图14A、图15A、图16A、图17A、图18A、图19A、图20A、图21A、图22A、与图23A显示沿着图1所示的参考剖面A-A的剖视图，而图8B、图9B、图10B、图11B、图12B、图13B、图14B、图15B、图16B、图17B、图18B、图19B、图20B、图21B、图21C、图22B、与图23B显示沿着图1所示的参考剖面B-B的剖视图，差别在于多个鳍状物及/或鳍状场效晶体管。图11C、图12C、图12D、图13C、图13D、图14C、图14D、图15C、图15D、图16C、图16D、图17C、与图17D显示沿着图1所示的参考剖面C-C的剖面图，差别在于多个鳍状物及/或鳍状场效晶体管。
在图2中，提供基板50。基板50可为半导体基板，比如基体半导体、绝缘层上半导体基板、或类似物，其可掺杂(比如掺杂p型或n型掺质)或未掺杂。基板50可为晶圆如硅晶圆。一般而言，绝缘层上半导体基板为半导体材料层形成于绝缘层上。举例来说，绝缘层可为埋置氧化物层、氧化硅层、或类似物。绝缘层位于基板上，且基板通常为硅基板或玻璃基板。亦可采用其他基板如多层基板或组成渐变基板。在一些实施例中，基板50的半导体材料可包含硅、锗、半导体化合物(如碳化硅、砷化镓、磷化镓、磷化铟、砷化铟、及/或锑化铟)、半导体合金(如硅锗、磷砷化镓、砷化铝铟、砷化铝镓、砷化镓铟、磷化镓铟、及/或磷砷化镓铟)、或上述的组合。
基板50具有区域50N与区域50P。区域50N可用于形成n型装置，比如n型金属氧化物半导体晶体管如n型鳍状场效晶体管。区域50P可用于形成p型装置，比如p型金属氧化物半导体晶体管如p型鳍状场效晶体管。区域50N可与区域50P物理分隔(比如图示的分隔线51)，且在区域50N与50P之间可具有任何数目的装置结构(如其他主动装置、掺杂区、隔离结构、或类似物)。
在图3中，鳍状物52形成于基板50中。鳍状物52为半导体带。在一些实施例中，可蚀刻沟槽于基板50中，以形成鳍状物52于基板50中。蚀刻可为任何可接受的蚀刻工艺，比如反应性离子蚀刻、中性束蚀刻、类似方法、或上述的组合。蚀刻可为非等向。
可由任何合适方法图案化鳍状物。举例来说，可采用一或多道光刻工艺图案化鳍状物，包括双重图案化或多重图案化工艺。一般而言，双重图案化或多重图案化工艺结合光刻与自对准工艺，其产生的图案间距小于采用单一的直接光刻工艺所得的图案间距。举例来说，一实施例形成牺牲层于基板上，并采用光刻工艺图案化牺牲层。采用自对准工艺沿着图案化的牺牲层侧部形成间隔物。接着移除牺牲层，并采用保留之间隔物图案化鳍状物。
在图4中，绝缘材料54形成于基板50之上与相邻的鳍状物52之间。绝缘材料54可为氧化物如氧化硅、氮化物、类似物、或上述的组合，且其形成方法可为高密度等离子体化学气相沉积、可流动的化学气相沉积(如在远端等离子体系统中沉积化学气相沉积为主的材料，之后固化材料使其转变为另一材料如氧化物)、类似方法、或上述的组合。亦可采用任何可接受的工艺所形成的其他绝缘材料。在所述实施例中，绝缘材料54为可流动的化学气相沉积工艺所形成的氧化硅。一旦形成绝缘材料，可进行退火工艺。在一实施例中，形成绝缘材料54，使多余的绝缘材料54覆盖鳍状物52。虽然附图中的绝缘材料54为单层，一些实施例可采用多层的绝缘材料54。举例来说，一些实施例可先沿着基板50与鳍状物52的表面形成衬垫层(未图示)。之后可形成上述填充材料于衬垫层上。
在图5中，对绝缘材料54进行移除工艺，以移除鳍状物52上的多余绝缘材料54。在一些实施例中，可采用平坦化工艺如化学机械研磨、回蚀刻工艺、上述的组合、或类似方法。平坦化工艺露出鳍状物52，使完成平坦化工艺之后的鳍状物52与绝缘材料54的上表面齐平。
在图6中，使绝缘材料54凹陷，以形成浅沟槽的隔离区56。让绝缘材料54凹陷，使区域50N与区域50P中的鳍状物52的上侧部分自相邻的浅沟槽的隔离区56之间凸起。此外，浅沟槽的隔离区56的上表面可为平坦表面(如图所示)、凸起表面、凹陷表面(如碟化)、或上述的组合。通过合适蚀刻，可使浅沟槽的隔离区56具有平坦、凸起、或凹陷的上表面。可采用可接受的蚀刻工艺使浅沟槽的隔离区56凹陷，比如对绝缘材料54具有选择性的蚀刻工艺。举例来说，蚀刻工艺蚀刻绝缘材料54的速率比蚀刻鳍状物52的材料的速率快。举例来说，可采用化学氧化物移除法搭配合适的蚀刻工艺(比如采用稀氢氟酸)。
图2至图6所示的工艺仅为如何形成鳍状物52的一例。在一些实施例中，鳍状物的形成方法可为外延成长工艺。举例来说，可形成介电层于基板50的上表面上，并蚀刻沟槽穿过介电层以露出下方的基板50。可外延成长同质外延结构于沟槽中，并让介电层凹陷，使同质外延结构自介电层凸起以形成鳍状物。此外，一些实施例可采用异质外延结构作为鳍状物52。举例来说，可使图5中的鳍状物52凹陷，并可外延成长不同于鳍状物52的材料于凹陷的鳍状物52上。在这些实施例中，鳍状物52包含凹陷的材料，以及位于凹陷材料上的外延成长材料。在其他实施例中，可形成介电层于基板50的上表面上，并蚀刻沟槽穿过介电层。接着可外延成长不同于基板50的材料的异质外延结构于沟槽中，并让介电层凹陷，使异质外延结构自介电层凸起以形成鳍状物52。在一些实施例中，外延成长同质外延结构或异质外延结构，且在成长时可原位掺杂外延成长的材料以省略之前与之后的布植，但原位掺杂与布植掺杂亦可搭配使用。
此外，在区域50N(如n型金属氧化物半导体区)与区域50P(如p型金属氧化物半导体区)中外延成长不同的材料具有优点。在多种实施例中，鳍状物52的上侧部分的组成可为硅锗(SixGe1-x，其中x可为0至1)、碳化硅、纯锗或实质上纯锗、III-V族半导体化合物、II-VI族半导体化合物、或类似物。举例来说，形成III-V族半导体化合物的可行材料包括但不限于砷化铟、砷化铝、砷化镓、磷化铟、氮化镓、砷化铟镓、砷化铟铝、锑化镓、锑化铝、磷化铝、磷化镓、或类似物。
此外，图6中可形成合适的井(未图示)于鳍状物52及/或基板50中。在一些实施例中，p型井可形成于区域50N中，而n型井可形成于区域50P中。在一些实施例中，p型井(或n型井)可形成于区域50N与50P中。
在不同形态的井的实施例中，可采用光刻胶或其他遮罩(未图示)以达区域50N与区域50P所用的不同布植步骤。举例来说，可形成光刻胶于区域50N中的鳍状物52与浅沟槽的隔离区56上。图案化光刻胶以露出基板50的区域50P(如p型金属氧化物半导体区)。可采用旋转涂布技术形成光刻胶，并采用可接受的光刻技术图案化光刻胶。一旦图案化光刻胶，可在区域50P中进行n型杂质布植，而光刻胶可作为遮罩以实质上避免n型杂质布植至区域50N(如n型金属氧化物半导体区)中。n型杂质可为磷、砷、或类似物，其布植至区域中的浓度小于或等于1018cm-3，比如约1017cm-3至约1018cm-3。在布植之后移除光刻胶，且移除方法可为可接受的灰化工艺。
在布植区域50P之后，形成光刻胶于区域50P中的鳍状物52与浅沟槽的隔离区56上。图案化光刻胶已露出基板50的区域50N(如n型金属氧化物半导体区)。可采用旋转涂布技术形成光刻胶，并采用可接受的光刻技术图案化光刻胶。一旦图案化光刻胶，可在区域50N中进行p型杂质的布植，而光刻胶可作为遮罩以实质上避免p型杂质布植至区域50P(如p型金属氧化物半导体区)中。p型杂质可为硼、二氟化硼、或类似物，其布植于区域中的浓度小鱼或等于1018cm-3，比如约1017cm-3至约1018cm-3之间。在布植之后可移除光刻胶，且移除方法可为可接受的灰化工艺。
在布植区域50N与区域50P之后，可进行退火以活化布植的p型及/或n型杂质。在一些实施例中，在成长外延的鳍状物时可原位掺杂成长材料，其可省略布植步骤。不过原位掺杂与布植掺杂可搭配使用。
在图7中，虚置介电层60形成于鳍状物52上。举例来说，虚置介电层60可为氧化硅、氮化硅、上述的组合、或类似物，且其形成方法可依据可接受的技术如沉积或热成长。虚置栅极层62形成于虚置介电层60上，而遮罩层64形成于虚置栅极层62上。可沉积虚置栅极层62于虚置介电层60上，接着平坦化(比如化学机械研磨)虚置栅极层62。遮罩层64可沉积于虚置栅极层62上。虚置栅极层62可为导电材料，其可为多晶硅、多晶硅锗、金属氮化物、金属硅化物、金属氧化物、或金属。在一实施例中，沉积非晶硅后使其再结晶，以产生多晶硅。虚置栅极层62的沉积方法可为物理气相沉积、化学气相沉积、溅镀沉积、或沉积导电材料所用的其他已知技术。虚置栅极层62的组成可为在蚀刻隔离区时，具有高蚀刻选择性的其他材料。举例来说，遮罩层64可包含氮化硅、氮氧化硅、或类似物。在此例中，单一的虚置栅极层62与单一的遮罩层64越过区域50N与区域50P。在一些实施中，可在区域50N与区域50P中分别形成分开的虚置栅极层与分开的遮罩层。值得注意的是，虽然图中的虚置介电层60只覆盖鳍状物52，但只是为了举例说明的目的。在一些实施例中，可沉积虚置介电层60，使虚置介电层60覆盖浅沟槽的隔离区56并延伸于虚置栅极层62与浅沟槽的隔离区56之间。
图8A至图23B是形成实施例的装置时的多种额外步骤。图8A至图23B显示的结构可在区域50N与区域50P中。举例来说，图8A至图23B所示的结构可实施于区域50N与50P中。若区域50N与区域50P的结构具有任何差异，将依据附图进行说明。
在图8A与图8B中，可采用可接受的光刻与蚀刻技术图案化遮罩层64以形成遮罩74。接着可将遮罩74的图案转移至虚置栅极层62。在一些实施例中(未图示)，亦可由可接受的蚀刻技术将遮罩74的图案转移至虚置介电层60，以形成虚置栅极72。虚置栅极72覆盖鳍状物52的个别通道区58。遮罩74的图案可用于物理分开相邻的虚置栅极72。虚置栅极72的长度方向亦可实质上垂直于个别外延的鳍状物52的长度方向。
此外，图8A与图8B中的栅极密封间隔物80可形成于虚置栅极72、遮罩74、及/或鳍状物52的露出表面上。在热氧化或沉积之后进行非等向蚀刻，可形成栅极密封间隔物80。
在形成栅极密封间隔物80之后，可进行轻掺杂源极/漏极区(未图示)所用的布植。在不同装置形态的实施例中(与图6所述的杂质类似)，可形成遮罩如光刻胶于区域50N上并露出区域50P，并可将合适形态(如n型或p型)的杂质布植至区域50P中露出的鳍状物52中。接着可移除遮罩。之后可形成遮罩如光刻胶于区域50P上并露出区域50N，并可布植适当种类的杂质至区域50N中露出的鳍状物52中。接着可移除遮罩。n型杂质可为任何前述的n型杂质，而p型杂质可为任何前述的p型杂质。轻掺杂源极/漏极区的杂质浓度可为约1015cm-3至约1016cm-3。可采用退火活化布植的杂质。
在图9A与图9B中，栅极间隔物86形成于沿着虚置栅极72与遮罩74的侧壁的栅极密封间隔物80上。栅极间隔物86的形成方法可为顺应性的沉积绝缘材料，之后非等向的蚀刻绝缘材料。栅极间隔物86的绝缘材料可为氮化硅、碳氮化硅、上述的组合、或类似物。栅极间隔物86可包含多层。栅极间隔物86的层状物亦可包含不同材料。非等向蚀刻可不自相邻鳍状物52之间的隔离区56完全移除栅极间隔物86的水平部分。在这些实施例中，栅极间隔物86的未移除水平部分可覆盖相邻鳍状物52之间的隔离区56的上表面。虚置栅极72、遮罩74、与栅极间隔物86包含栅极组件70。
在图10A与图10B中，蚀刻凹陷81于鳍状物52中。蚀刻工艺可为等向或非等向，其可对鳍状材料的一或多个结晶平面具有选择性。如此一来，虽然图10B所示的凹陷81具有圆润化的底部轮廓，但凹陷81实际上具有多种轮廓形状，端视采用的蚀刻工艺而定。蚀刻工艺可为干蚀刻(如反应性离子蚀刻、中性束蚀刻、或类似方法)或湿蚀刻(比如采用氢氧化四甲基铵、氢氧化铵、或其他蚀刻剂的湿蚀刻)。图10B显示凹陷81，其沿着图1所示的参考剖面B-B。
在图11A至图17D中，外延的源极/漏极区82形成于鳍状物52中，以施加应力于个别通道区58中，进而改善效能。外延的源极/漏极区82形成于鳍状物52中，使每一虚置栅极72位于个别的相邻一对外延的源极/漏极区82之间。外延的源极/漏极区82可延伸至鳍状物52中。栅极间隔物86可用于使外延的源极/漏极区82与虚置栅极72隔有合适的横向距离，使外延的源极/漏极区82不会向外短接至最终鳍状场效晶体管之后续形成的栅极。
区域50N(如n型金属氧化物半导体区)中的外延的源极/漏极区82，其形成方法可为遮罩区域50P(如p型金属氧化物半导体区)，并蚀刻区域50N中的鳍状物52的源极/漏极区以形成凹陷于鳍状物52中。接着外延成长区域50N中的外延的源极/漏极区82于凹陷中。外延的源极/漏极区82可包含任何可接受的材料，比如适用于n型鳍状场效晶体管的材料。举例来说，若鳍状物52为硅，则区域50N中的外延的源极/漏极区82可包含施加拉伸应力于通道区58中的材料，比如硅、碳化硅、碳磷化硅、磷化硅、或类似物。区域50N中的外延的源极/漏极区82亦可具有自鳍状物52的个别表面隆起的表面。在一实施例中，可外延成长外延的源极/漏极区82于区域50N中，且外延成长的工艺不会产生晶面。在其他实施例中，外延的源极/漏极区82可具有晶面。
区域50P(如p型金属氧化物半导体区)中的外延的源极/漏极区82，其形成方法可为遮罩区域50N(如n型金属氧化物半导体区)，并蚀刻区域50P中的鳍状物52的源极/漏极区以形成凹陷于鳍状物52中。接着外延成长区域50P中的外延的源极/漏极区82于凹陷中。外延的源极/漏极区82可包含任何可接受的材料，比如适用于p型鳍状场效晶体管的材料。举例来说，若鳍状物52为硅，则区域50P中的外延的源极/漏极区82可包含施加压缩应力于通道区58中的材料，比如硅锗、硼化硅锗、锗、锗锡、或类似物。区域50P中的外延的源极/漏极区82亦可具有自鳍状物52的个别表面隆起的表面。在一实施例中，可外延成长外延的源极/漏极区82于区域50P中，且外延成长的工艺不会产生晶面。在其他实施例中，外延的源极/漏极区82可具有晶面。
外延的源极/漏极区82及/或鳍状物52可布植掺质以形成源极/漏极区，之后再进行退火。上述布植掺质的步骤可与前述形成轻掺杂的源极/漏极区的步骤类似。源极/漏极区的杂质浓度可为约1019cm-3至约1021cm-3。源极/漏极区所用的n型及/或p型杂质可为前述的任何杂质。在一些实施例中，在成长外延的源极/漏极区82时可进行原位掺杂。
图11A至图17D显示在区域50P中形成外延的源极/漏极区82的步骤，而源极/漏极区82可包含掺杂硼的硅锗(如SixGe1-x，且x可为0至1)。在一些实施例中，每一外延的源极/漏极区82包含第一层82A、第二层82B、第三层82C、第四层82D、与第五层82E，如图17B所示。第一层82A亦可称作第一主体层，第二层82B亦可称作第二主体层，第三层82C亦可称作第三主体层，第四层82D亦可称作第四主体层，而第五层82E亦可称作第五主体层。在其他实施例中，外延的源极/漏极区82可具有更少或更多层。在n型金属氧化物半导体装置的其他实施例中，外延的源极/漏极区82可形成于区域50N中，其可包含硅并掺杂砷或磷。
外延的源极/漏极区82的外延成长法可采用有机金属化学气相沉积、分子树外延、液相外延、气相外延、选择性外延成长、上述的组合、或类似方法。当外延的源极/漏极区82的组成为掺杂硼的硅锗时，外延成长工艺采用合适的硅前驱物、合适的锗前驱物、与合适的硼前驱物。硼前驱物提供的硼源在外延成长工艺时，可用于原位掺杂外延的源极/漏极区82。合适的硅前驱物可为硅烷、乙硅烷、丙硅烷、上述的组合、或类似物。在一些实施例中，合适的锗前驱物可为四氢化锗、乙锗烷、上述的组合、或类似物。在其他实施例中，合适的硼前驱物可为乙硼烷。
图11B与图11C显示以例示性工艺形成第一层82A的步骤。鳍状物52周围的虚线显示参考剖面A-A中鳍状物52的最大高度，用以与图11C所示的参考剖面C-C中的外延的源极/漏极区的高度作比较。在例示性工艺中，
第一层82A的锗浓度可为约10原子％至40原子％。在一些实施例中，第一层82A的硼浓度可为约5×1019原子/cm3至2×1021原子/cm3。硅前驱物的流速可为约5sccm至约500sccm，且锗前驱物的流速可为约10sccm至约800sccm。硼前驱物的流速可为约10sccm至约800sccm。外延成长工艺的温度可为约350℃至约800℃，且压力可为约5Torr至约450Torr。
图11B与图11C更显示形成第一缓冲层84A于第一层82A上的步骤。第一缓冲层84A可包含硅锗(Si1-xGex，x可为0至0.1)，其可掺杂硼。在一些实施例中，缓冲层位于源极/漏极区82中以改良源极/漏极结构的外延成长。第一缓冲层84A的锗浓度为约0原子％至约15原子％。第一缓冲层84A的硼浓度可为约0原子/cm3至5×1020原子/cm3。硅前驱物的流速可为约5sccm至约500sccm。在一些实施例中，锗前驱物的流速可为约10sccm至约800sccm，而硼前驱物的流速可为约10sccm至约800sccm。外延成长工艺的温度可为约350℃至约800℃，且压力可为约5Torr至约450Torr。第一缓冲层84A的厚度可为约
Figure BDA0002292162860000121
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Figure BDA0002292162860000122
图12B、图12C、与图12D显示形成第二层82B的步骤。图12C显示的实施例包括制作逻辑电路，其中相邻鳍状物上的源极/漏极区合并。图12D显示的实施例包括制作静态随机存取存储器装置，其中相邻鳍状物上的源极/漏极区分开而不合并。通过对源极/漏极区的致密区具有选择性的蚀刻工艺，可限制相邻鳍状物上的源极/漏极区合并。蚀刻工艺可为干蚀刻，其采用的蚀刻剂包含氢氟酸、氯化氢、溴化氢、含氟气体(如四氟化碳、二氟甲烷、氟化甲烷、氟仿、八氟环丁烷、六氟丁二烯、三氟化氮、或六氟化硫)、一些碳聚合物气体(如甲烷、一氧化碳、二氧化碳、或羰基硫)、类似物、或上述的组合。干蚀刻可在合适压力(比如约2mTorr至约100mTorr)与合适温度(比如约30℃至约80℃)下进行。
第二层82B的锗浓度可为约30原子％至约70原子％，且第二层82B的硼浓度可为约1×1020原子/cm3至2×1021原子/cm3。硅前驱物的流速可为约5sccm至约500sccm，且锗前驱物的流速可为约10sccm至约800sccm。硼前驱物的流速可为约10sccm至约800sccm。外延成长工艺的温度可为约350℃至约800℃，且压力可为约5Torr至约450Torr。可进行外延成长工艺，使第二层82B不具有晶面。进行对源极/漏极区的致密区具有选择性的蚀刻工艺，可限制晶面成长。蚀刻工艺可为干蚀刻，其采用的蚀刻剂包含氢氟酸、氯化氢、溴化氢、含氟气体(如四氟化碳、二氟甲烷、氟化甲烷、氟仿、八氟环丁烷、六氟丁二烯、三氟化氮、或六氟化硫)、一些碳聚合物气体(如甲烷、一氧化碳、二氧化碳、或羰基硫)、类似物、或上述的组合。干蚀刻可在合适压力(比如约2mTorr至约100mTorr)与合适温度(比如约30℃至约80℃)下进行。
如图12C所示，在相邻鳍状物上的源极/漏极区合并的实施例中，鳍状物52与第二层82B的外侧顶点之间的横向距离L1可小于约10nm。鳍状物52的宽度W1与横向距离L1的比例可为约3：10至3：3。此外，气隙可位于第二层82B与栅极间隔物86之间，如图12C所示，气隙的高度H1可为约5nm至约30nm。
图12B、图12C、与图12D更显示形成第二缓冲层84B于第二层82B上的步骤。第二缓冲层84B可包含硅锗(Si1-xGex，x可为0至0.15)，其可掺杂硼。在一些实施例中，缓冲层位于源极/漏极区82中以改良源极/漏极结构的外延成长。第二缓冲层84B的锗浓度为约0原子％至约15原子％。第二缓冲层84B的硼浓度可为约0原子/cm3至5×1020原子/cm3。硅前驱物的流速可为约5sccm至约500sccm。在一些实施例中，锗前驱物的流速可为约10sccm至约800sccm，而硼前驱物的流速可为约10sccm至约800sccm。外延成长工艺的温度可为约350℃至约800℃，且压力可为约5Torr至约450Torr。第二缓冲层84B的厚度可为约
Figure BDA0002292162860000141
至约
Figure BDA0002292162860000142
图13C至图16D显示的实施例中，进行源极/漏极区82的额外外延成长层的两次循环的沉积与回蚀刻步骤。在其他实施例中，可进行超过两次循环的沉积与蚀刻步骤。图13C与图13D显示形成第三层82C的步骤。图13C显示的实施例包括制作逻辑电路，其中相邻鳍状物上的源极/漏极区合并。图13D显示的实施例包括制作静态随机存取存储器装置，其中相邻鳍状物上的源极/漏极区分开而不合并。第三层82C的锗浓度可为约30原子％至约70原子％，且第三层82C的硼浓度可为约2×1020原子/cm3至2×1021原子/cm3。硅前驱物的流速可为约5sccm至约500sccm，且锗前驱物的流速可为约10sccm至约800sccm。硼前驱物的流速可为约10sccm至约800sccm。外延成长工艺的温度可为约350℃至约800℃，且压力可为约5Torr至约450Torr。
图13C与图13D更显示形成第三缓冲层84C于第三层82C上的步骤。第三缓冲层84C可包含硅锗(Si1-xGex，x可为0至0.15)，其可掺杂硼。在一些实施例中，缓冲层位于源极/漏极区82中以改良源极/漏极结构的外延成长。第三缓冲层84C的锗浓度为约0原子％至约15原子％。第三缓冲层84C的硼浓度可为约0原子/cm3至5×1020原子/cm3。硅前驱物的流速可为约5sccm至约500sccm。在一些实施例中，锗前驱物的流速可为约10sccm至约800sccm，而硼前驱物的流速可为约10sccm至约800sccm。外延成长工艺的温度可为约350℃至约800℃，且压力可为约5Torr至约450Torr。第三缓冲层84C的厚度可为约
Figure BDA0002292162860000143
至约
Figure BDA0002292162860000144
图14C与图14D显示第一回蚀刻第三层82C与第三缓冲层84C的步骤。图14C显示的实施例包括制作逻辑电路，其中相邻鳍状物上的源极/漏极区可合并。图14D显示的实施例包括制作静态随机存取存储器装置，其中相邻鳍状物上的源极/漏极区分开而不合并。第一回蚀刻工艺可为干蚀刻，其采用的气体包含氯化氢、氢氟酸、溴化氢、氢气、锗、或上述的组合。在一些实施例中，干蚀刻采用的混合气体包括氯化氢、锗、与氢气。第一回蚀刻的温度可为约400℃至约700℃，且历时20秒至600秒。第一回蚀刻可采用氮气或氢气作为载气。在第一回蚀刻之后，可由氢气进行净化步骤，其历时约10秒至约60秒。如图14C与图14D所示，第一回蚀刻移除个别侧壁上的第三层82C与第三缓冲层84C的部分，以减少第三层82C与第三缓冲层84C的水平宽度。图14D所示的一些实施例如静态随机存取存储器装置，减少水平宽度有助于避免相邻的源极/漏极区82合并。
图15C与图15D显示形成第四层82D的步骤。图15C显示的实施例包括制作逻辑电路，其中相邻鳍状物上的源极/漏极区合并。图15D显示的实施例包括制作静态随机存取存储器装置，其中相邻鳍状物上的源极/漏极区分开而不合并。第四层82D的锗浓度可为约30原子％至约70原子％，且第四层82D的硼浓度可为约2×1020原子/cm3至2×1021原子/cm3。硅前驱物的流速可为约5sccm至约500sccm，且锗前驱物的流速可为约10sccm至约800sccm。硼前驱物的流速可为约10sccm至约800sccm。外延成长工艺的温度可为约350℃至约800℃，且压力可为约5Torr至约450Torr。
图15C与图15D更显示形成第四缓冲层84D于第四层82D上的步骤。第四缓冲层84D可包含硅锗(Si1-xGex，x可为0至0.15)，其可掺杂硼。第四缓冲层84D的锗浓度为约0原子％至约15原子％，且第四缓冲层84D的硼浓度可为约0原子/cm3至5×1020原子/cm3。硅前驱物的流速可为约5sccm至约500sccm。锗前驱物的流速可为约10sccm至约800sccm，而硼前驱物的流速可为约10sccm至约800sccm。外延成长工艺的温度可为约350℃至约800℃，且压力可为约5Torr至约450Torr。第四缓冲层84D的厚度可为约
Figure BDA0002292162860000151
至约
Figure BDA0002292162860000152
图16C与图16D显示第二回蚀刻第四层82D与第四缓冲层84D的步骤。图16C所示的实施例包含制作逻辑电路，其中相邻鳍状物上的源极/漏极区合并。图16D所示的实施例包含制作静态随机存取存储器装置，其中相邻鳍状物上的源极/漏极区分开而不合并。第二回蚀刻工艺可为干蚀刻，其可采用氯化氢、氢氟酸、溴化氢、氢气、锗、类似物、或上述的组合。在一些实施例中，干蚀刻采用含氯化氢、锗、与氢气的混合气体。第二回蚀刻的温度违约400℃至约700℃，且历时20秒至600秒。第二回蚀刻可采用氮气或氢气作为载气。在第二回蚀刻之后，可采用氢气进行净化，且净化时间为约10秒至60秒。如图16C与图16D所示，第二回蚀刻可移除个别侧壁上的第四层82D与第四缓冲层84D的部分，以减少第四层82D与第四缓冲层84D的水平宽度。
如图17B至图17D所示，形成第五层82E并完成源极/漏极区82。图17B沿着图1的参考剖面B-B，显示完成的源极/漏极区82。图17C沿着图1所示的参考剖面C-C并显示制作逻辑电路的实施例，其中相邻鳍状物上的源极/漏极区合并。图17D沿着图1所示的参考剖面C-C并显示制作静态随机存取存储器装置的实施例，其中相邻鳍状物上的源极/漏极区分开而不合并。在图17B至图17D所示的一些实施例中，第五层82E形成于第四层82D与第四缓冲层84D上。第五层82E亦可称作盖层或保护层。第五层可包含掺杂硼的硅锗(Si1-xGex，其中x可为0至0.3)。第五层82E的沉积法或外延成长法可采用有机金属化学气相沉积、分子束外延、液相外延、气相外延、选择性外延成长、上述的组合、或类似方法。第五层82E的厚度可小于6nm。源极/漏极区82的沉积层与缓冲层84的总厚度可为约40nm至约80nm。在一实施例中，源极/漏极区82的沉积层与缓冲层84的总厚度为约12nm。如图17D所示，在相邻鳍状物上的源极/漏极区分开而不合并的实施例中，鳍状物52的侧壁与源极/漏极区82的外侧顶点之间的横向距离L2，可小于相邻鳍状物52之间的间距的一半，以避免外延的源极/漏极区82合并。举例来说，横向距离L2可为约15nm。鳍状物52的宽度W1与横向距离L2的比例可为约1：1至1：2.5之间。
在图18A与图16B中，第一层间介电层88沉积于图10A与图10B所示的结构上。第一层间介电层88的组成可为介电材料，且其沉积方法可为任何合适方法如化学气相沉积、等离子体辅助化学气相沉积、或可流动的化学气相沉积。介电材料可包含磷硅酸盐玻璃、硼硅酸盐玻璃、硼磷硅酸盐玻璃、未掺杂的硅酸盐玻璃、或类似物。半导体材料可包含非晶硅、硅锗(SixGe1-x，其中x可介于近似0与1之间)、纯锗、或类似物。亦可采用任何可接受的工艺所形成的其他绝缘或半导体材料。在一些实施例中，接点蚀刻停止层87位于第一层间介电层88以及外延的源极/漏极区82、硬遮罩74、与栅极间隔物86之间。接点蚀刻停止层87可包含介电材料，比如与上方的第一层间介电层88具有不同蚀刻速率的氮化硅、氧化硅、氮氧化硅、或类似物。
在图19A与图19B中，可进行平坦化工艺如化学机械研磨，使第一层间介电层88的上表面与虚置栅极72的上表面齐平。平坦化工艺亦可移除虚置栅极72上的遮罩74，以及栅极密封间隔物80与栅极间隔物86沿着遮罩74的侧壁的部分。在平坦化工艺之后，虚置栅极72的上表面、栅极密封间隔物80的上表面、栅极间隔物86的上表面、与第一层间介电层88的上表面齐平。综上所述，可自第一层间介电层88露出虚置栅极72的上表面。
在图20A与图20B中，由蚀刻步骤移除虚置栅极72，以形成凹陷90。亦可移除凹陷90中的虚置介电层60的部分。在一些实施例中，只移除虚置栅极72，而凹陷90露出保留的虚置介电层60。在一些实施例中，自晶粒的第一区(如核心逻辑区)中的凹陷90移除虚置介电层60，并保留晶粒的第二区(如输入/输出区)中的虚置介电层60于凹陷90中。在一些实施例中，移除虚置栅极72的方法为非等向干蚀刻工艺。举例来说，蚀刻工艺可包含干蚀刻工艺，其采用的反应气体可选择性蚀刻虚置栅极72而不蚀刻第一层间介电层88或栅极间隔物86。每一凹陷90露出个别鳍状物52的通道区58。每一通道区58位于相邻的一对外延的源极/漏极区82之间。在蚀刻移除虚置栅极72时，虚置介电层60可作为蚀刻停止层。在移除虚置栅极72之后，接着可视情况移除虚置介电层60。
在图21A与图21B中，形成栅极介电层92与栅极94以用于置换栅极。图21C显示图21B中区域89的细节。栅极介电层92顺应性地沉积于凹陷90中，比如沉积于鳍状物52的上表面与侧壁上、栅极密封间隔物80的侧壁上、与栅极间隔物86的侧壁上。栅极介电层92亦可形成于第一层间介电层88的上表面上。在一些实施例中，栅极介电层92包含氧化硅、氮化硅、或上述的多层。在一些实施例中，栅极介电层92为高介电常数的介电材料。在这些实施例中，栅极介电层92的介电常数可大于约7.0，且可包含铪、铝、锆、镧、镁、钡、钛、铅、或上述的组合的金属氧化物或硅酸盐。栅极介电层92的形成方法可包含分子束沉积、原子层沉积、等离子体辅助化学气相沉积、或类似方法。在虚置介电层60的部分保留于凹陷90中的实施例中，栅极介电层92包含虚置介电层60的材料(如氧化硅)。
栅极94沉积于栅极介电层92上，并填入凹陷90的其余部分。栅极94可为含金属材料如氮化钛、氧化钛、氮化钽、碳化钽、钴、钌、铝、钨、上述的组合、或上述的多层。举例来说，虽然图21B显示单层的栅极94，但栅极94可包含任何数目的衬垫层94A、任何数目的功函数调整层94B、与填充材料94C，如图21C所示。在填入栅极94之后，可进行平坦化工艺如化学机械研磨，以移除栅极介电层92与栅极94的材料位于第一层间介电层88的上表面上的多余部分。因此栅极94的材料与栅极介电层92的保留部分形成最终鳍状场效晶体管的置换栅极。栅极94与栅极介电层92可一起称作栅极堆叠。栅极与栅极堆叠可沿着鳍状物52的通道区58的侧壁延伸。
可同时形成区域50N与区域50P中的栅极介电层92，使每一区中的栅极介电层92由相同材料组成。亦可同时形成栅极94，使每一区中的栅极94由相同材料组成。在一些实施例中，可由分开工艺形成每一区中的栅极介电层92，使每一区中的栅极介电层92可为不同材料。可由分开工艺形成每一区中的栅极94，使每一区中的栅极94可为不同材料。在采用分开的工艺时，可采用多种遮罩步骤以遮罩与露出合适区域。在图22A与图22B中，第二层间介电层108沉积于第一层间介电层88上。在一实施例中，第二层间介电层108为可流动的化学气相沉积法所形成的可流动膜。在一些实施例中，第二层间介电层108的组成为介电材料如磷硅酸盐玻璃、硼硅酸盐玻璃、硼磷硅酸盐玻璃、未掺杂的硅酸盐玻璃、或类似物，且其沉积方法可为任何合适方法如化学气相沉积或等离子体辅助化学气相沉积。在图23A与图23B所示的一些实施例中，栅极接点110与源极/漏极接点112穿过第二层间介电层108与第一层间介电层88。可形成源极/漏极接点112所用的开口穿过第一层间介电层88与第二层间介电层108，并形成栅极接点110所用的开口穿过第二层间介电层108。可采用可接受的光刻与蚀刻技术形成开口。衬垫层(如扩散阻障层、粘着层、或类似物)以及导电材料可形成于开口中。衬垫层可包含钛、氮化钛、钽、氮化钽、或类似物。导电材料可为铜、铜合金、银、金、钨、钴、铝、镍、或类似物。可进行平坦化工艺如化学机械研磨以自第二层间介电层108的表面移除多余材料。保留的衬垫曾与导电材料形成源极/漏极接点112与栅极接点110于开口中。可进行退火工艺以形成硅化物于外延的源极/漏极区82与源极/漏极接点112之间的界面。源极/漏极接点112物理与电性耦接至外延的源极/漏极区82，与门极接点110物理与电性耦接至栅极106。源极/漏极接点112与栅极接点110可由不同工艺形成，或由相同工艺形成。虽然附图中的源极/漏极接点112与栅极接点110形成在相同剖面中，但上述接点可形成于不同剖面中以避免接点短路。
如上所述，鳍状场效晶体管为主的装置包含静态随机存取存储器装置与逻辑装置，其可得利于外延成长的源极/漏极区的体积增加。源极/漏极区高于半导体鳍状物的上表面的高度增加，其中埋置源极/漏极区并增加体积，可降低接点电阻以改善装置效能。这是因为中间的制作工艺会消耗大量外延成长的源极/漏极区，因此外延成长阶段所增加的源极/漏极体积可使源极/漏极区的最终体积较大。增加外延成长的源极/漏极区体积，可降低后续形成的源极/漏极接点与外延成长的源极/漏极区之间的能障(因外延成长的源极/漏极区的高掺质浓度)，有利于降低鳍状场效晶体管装置的接点电阻。通过采用重复沉积与蚀刻的多次循环成长可达上述结构，以增加源极/漏极区的高度并限制源极/漏极区的水平成长。
在一实施例中，半导体装置包括：自基板延伸的第一半导体鳍状物与第二半导体鳍状物；栅极，位于第一半导体鳍状物与第二半导体鳍状物上；以及源极/漏极区，位于第一半导体鳍状物与第二半导体鳍状物上并与栅极相邻，其中源极/漏极区的上表面高于栅极下的第一半导体鳍状物与第二半导体鳍状物的上表面，其中源极/漏极区包括多个缓冲层与多个主体层，其中源极/漏极区包括互相交错的缓冲层与主体层，其中缓冲层的每一者的平均厚度为
Figure BDA0002292162860000191
至
Figure BDA0002292162860000192
在一实施例中，源极/漏极区的上表面比第一半导体鳍状物与第二半导体鳍状物的上表面高至少6nm。在一实施例中，缓冲层包括掺杂硼的硅锗。在一实施例中，缓冲层的锗浓度为0原子％至15原子％。在一实施例中，源极/漏极区包括的锗浓度为约10原子％至约70原子％。在一实施例中，栅极与源极/漏极区为逻辑电路中的晶体管构件。在一实施例中，气隙夹设于源极/漏极区与基板之间。在一实施例中，气隙的高度为5nm至30nm。
在另一实施例中，半导体装置包括：自基板凸起的第一半导体鳍状物与第二半导体鳍状物；以及第一源极/漏极区位于第一半导体鳍状物上，与第二源极/漏极区位于第二半导体鳍状物上，其中第一源极/漏极区与第二源极/漏极区分开，其中第一源极/漏极区与第二源极/漏极区的上表面高于第一半导体鳍状物与第二半导体鳍状物的上表面，其中第一源极/漏极区与第二源极/漏极区各自包括：第一缓冲层；第一主体层，位于第一缓冲层上；第二缓冲层，位于第一主体层上；以及第二主体层，位于第二缓冲层上，其中第一缓冲层与第二缓冲层的每一者的平均厚度为
Figure BDA0002292162860000201
至
Figure BDA0002292162860000202
在一实施例中，第一源极/漏极区与第二源极/漏极区包括10原子％至70原子％的锗。在一实施例中，第一源极/漏极区与第二源极/漏极区为静态随机存取存储器装置的构件。在一实施例中，第一半导体鳍状物的宽度，与第一半导体鳍状物的侧壁及第一源极/漏极区的外侧顶点之间的横向距离的比例为1：1至1：2.5。
在又一实施例中，半导体装置的形成方法包括：形成自基板凸起的第一半导体鳍状物与第二半导体鳍状物；形成第一栅极结构于第一半导体鳍状物上；使第一半导体鳍状物凹陷，以形成与第一栅极结构相邻的第一凹陷；以及形成第一源极/漏极区于第一凹陷中。形成第一源极/漏极区的步骤包括：外延成长第一主体层于第一凹陷中；外延成长第二主体层于第一主体层上；以及形成一或多个结合层，其中形成每一结合层的步骤包括：外延成长上侧主体层；沉积缓冲层于上侧主体层上；以及使上侧主体层与缓冲层的侧壁凹陷。在一实施例中，最上侧的上侧主体层的上表面，比第一半导体鳍状物的上表面高6nm。在一实施例中，使上侧主体层的侧壁凹陷的步骤包括采用氯化氢、氢氟酸、或溴化氢的干蚀刻。在一实施例中，方法还包括沉积保护层于最上侧的上侧主体层上。在一实施例中，方法还包括：形成第二栅极结构于第二半导体鳍状物上；以及使第二半导体鳍状物凹陷，以形成与第二栅极结构相邻的第二凹陷，其中形成第一源极/漏极区的步骤同时形成第二源极/漏极区，且其中第一源极/漏极区与第二源极/漏极区维持分开。在一实施例中，形成一或多个结合层的步骤包括形成超过两个结合层。在一实施例中，一或多个结合层的总厚度为约12nm。在一实施例中，使上侧主体层的侧壁凹陷的步骤包括采用氯化氢、锗、与氢气的混合气体的干蚀刻。
上述内容已说明几个实施例的特征，以利本技术领域中技术人员理解详细说明。本技术领域中技术人员应理解，本发明实施例明显可作为设计或调整其他工艺和结构的基础，以实现此处介绍的实施例的相同目的及/或相同优点。本技术领域中技术人员亦应理解，这些等效构造并未脱离本发明实施例的构思与范围，且在不脱离本发明实施例的构思与范围的前提下，可进行多种改变、取代、或变更。

Claims (1)

1.一种半导体装置，包括：
自一基板延伸的一第一半导体鳍状物与一第二半导体鳍状物；
一栅极，位于该第一半导体鳍状物与该第二半导体鳍状物上；以及
一源极/漏极区，位于该第一半导体鳍状物与该第二半导体鳍状物上并与该栅极相邻，其中该源极/漏极区的上表面高于该栅极下的该第一半导体鳍状物与该第二半导体鳍状物的上表面，其中该源极/漏极区包括多个缓冲层与多个主体层，其中该源极/漏极区包括互相交错的该些缓冲层与该些主体层，其中该些缓冲层的每一者的平均厚度为
Figure FDA0002292162850000011
至
Figure FDA0002292162850000012
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