CN112447586A - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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Publication number
CN112447586A
CN112447586A CN201910833224.3A CN201910833224A CN112447586A CN 112447586 A CN112447586 A CN 112447586A CN 201910833224 A CN201910833224 A CN 201910833224A CN 112447586 A CN112447586 A CN 112447586A
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Prior art keywords
layer
forming
opening
epitaxial layer
ions
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CN201910833224.3A
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张青淳
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN201910833224.3A priority Critical patent/CN112447586A/zh
Priority to US17/004,937 priority patent/US11417738B2/en
Publication of CN112447586A publication Critical patent/CN112447586A/zh
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Abstract

一种半导体结构及其形成方法，包括：提供衬底，所述衬底内具有第一开口；在第一开口内形成第一外延层，所述第一外延层内具有第二开口；在所述第二开口的侧壁表面和底部表面形成停止层、以及位于所述停止层表面的第二外延层；在形成所述第二外延层之后，在衬底上形成介质层，所述介质层内具有暴露出所述第二外延层表面的第三开口；刻蚀第三开口底部暴露出的第二外延层直至暴露出所述停止层为止，在所述第二外延层内形成第四开口；采用半导体金属化工艺在第四开口的侧壁表面和底部表面形成接触层。通过所述停止层能够保证刻蚀仅在第二外延层内进行，提高形成第四开口的可控性与精确性，提高形成的半导体结构的性能与良率。

Description

半导体结构及其形成方法
技术领域
本发明涉及半导体制造技术领域，尤其涉及一种半导体结构及其形成方法。
背景技术
随着半导体技术的不断进步，半导体器件的特征尺寸逐渐变小。关键尺寸的缩小意味着在芯片上可布置更多数量的晶体管，同时给半导体工艺提出了更高的要求。
由于金属具有良好的导电性，在半导体技术中，往往通过金属接触层实现源漏掺杂层与外部电路的电连接。然而，由于金属与源漏掺杂层之间的费米能级相差较大，金属接触层与源漏掺杂层之间的势垒较高，导致金属接触层与源漏掺杂层之间的接触电阻较大。现有技术通过增大金属接触层与源漏掺杂区之间的金属硅化物的表面积来降低接触电阻，提高半导体结构的性能。
然而，现有技术中在形成金属接触层的过程中，形成的金属接触层质量较差，影响形成的半导体结构的性能与良率。
发明内容
本发明解决的问题是提供一种半导体结构及其形成方法，能够提升所述接触层的形成质量，进而提高形成的半导体结构的性能与良率。
为解决上述问题，本发明提供一种半导体结构的形成方法，包括：提供衬底，所述衬底内具有第一开口；在所述第一开口内形成第一外延层，所述第一外延层内具有第二开口；在所述第二开口的侧壁表面和底部表面形成停止层、以及位于所述停止层表面的第二外延层；在形成所述第二外延层之后，在所述衬底上形成介质层，所述介质层内具有暴露出所述第二外延层表面的第三开口；刻蚀所述第三开口底部暴露出的第二外延层直至暴露出所述停止层为止，在所述第二外延层内形成第四开口；采用半导体金属化工艺在所述第四开口的侧壁表面和底部表面形成接触层。
可选的，所述第一开口的形成方法包括：在所述衬底上形成第一掩膜结构；在所述第一掩膜结构上形成第一图形化层，所述第一图形化层具有暴露部分所述第一掩膜结构的开口；以所述第一图形化层为掩膜刻蚀部分所述第一掩膜结构与所述衬底，形成所述第一开口；在所述第一开口形成之后，去除所述第一图形化层与所述第一掩膜结构。
可选的，所述介质层和第三开口的形成方法包括：在所述衬底上形成初始介质层；在所述初始介质层上形成第二掩膜结构；在所述第二掩膜结构上形成第二图形化层，所述第二图形化层具有暴露部分所述初始介质层的开口；以所述第二图形化层为掩膜刻蚀部分所述第二掩膜结构与所述初始介质层，直至暴露出所述第二外延层的表面为止，形成所述介质层与所述第三开口；在形成所述介质层与所述第三开口之后，去除所述第二图形化层与所述第二掩膜结构。
可选的，所述停止层的材料为掺杂有第一类型离子的半导体材料；所述半导体材料包括硅、锗、锗化硅、碳化硅、砷化镓或镓化铟。
可选的，所述第一外延层内掺杂有第一类型离子。
可选的，在所述第一外延层内掺杂第一类型离子的工艺为原位掺杂工艺。
可选的，所述第二外延层内掺杂有第一类型离子，且所述第二外延层内的第一类型离子的掺杂浓度小于所述停止层内的第一类型离子的掺杂浓度。
可选的，在所述第二外延层内掺杂第一类型离子的工艺为原位掺杂工艺。
可选的，所述第一类型离子为P型离子或N型离子；所述P型离子包括硼离子或铟离子；所述N型离子包括磷离子或砷离子。
可选的，所述第一外延层的形成工艺包括外延沉积工艺；所述停止层的形成工艺包括外延沉积工艺；所述第二外延层的形成工艺包括外延沉积工艺；所述停止层的厚度为1nm～5nm。
可选的，在所述第三开口的侧壁表面形成侧墙；所述侧墙的材料包括氧化硅或氮化硅。
可选的，形成所述侧墙的工艺包括原子层沉积工艺、化学气相沉积工艺或物理气相沉积工艺。
可选的，所述第三开口底部还延伸入所述第二外延层内，且所述侧墙还位于所述第三开口侧壁暴露出的第二外延层侧壁表面。
可选的，所述第四开口的侧壁具有向所述衬底内凹陷的顶角。
可选的，所述第四开口的形成工艺包括湿法刻蚀工艺；所述湿法刻蚀工艺的刻蚀液为碱性溶液。
可选的，所述碱性溶液包括氨水或四甲基氢氧化铵溶液。
可选的，在形成所述第四开口之后，形成所述接触层之前，还包括：对所述第二外延层进行离子注入处理；所述离子注入采用的离子包括硼离子、磷离子或砷离子。
可选的，在对所述第二外延层进行离子注入之后，形成所述接触层之前，还包括：对所述第二外延层进行预非晶化处理。
可选的，所述接触层的形成方法包括：在所述第四开口内形成初始接触层；对所述初始接触层进行退火处理，形成所述接触层。
相应的，本发明还提供了一种由上述方法所形成的半导体结构，包括：衬底，所述衬底具有第一开口；位于所述第一开口内的第一外延层，所述第一外延层内具有第二开口；位于所述第二开口侧壁表面和底部表面的停止层、以及位于所述停止层表面的第二外延层；位于所述衬底上的介质层，所述介质层内具有暴露出所述第二外延层表面的第三开口；位于所述第二外延层内的第四开口，所述第三开口暴露出所述第四开口；位于所述第四开口的侧壁表面和底部表面的接触层。
与现有技术相比，本发明的技术方案具有以下优点：
在本发明的技术方案中，在所述衬底内形成第一外延层；在所述第一外延层内形成停止层、以及位于所述停止层表面上的第二外延层；刻蚀所述第二外延层直至暴露出所述停止层的顶部表面为止，形成第四开口；在所述第四开口的侧壁表面和底部表面形成接触层。停止层用于定义第四开口形成工艺的停止位置，通过所述停止层能够保证刻蚀仅在所述第二外延层内进行，而不会贯穿所述停止层继续向下延伸刻蚀，提高形成所述第四开口的可控性与精确性，进而保证了所述接触层的形成质量，提高形成的半导体结构的性能与良率。
进一步，在本发明的技术方案中，所述第四开口的侧壁具有向所述衬底内凹陷的顶角(西格玛形)，通过西格玛形的第四开口能够进一步的增大最终形成的接触层的表面积，进而减小接触电阻。
进一步，在本发明的技术方案中，对所述第二外延层进行离子注入。由于第二外延层采用的是掺杂有第一类型离子的半导体材料，该种材料的电阻较大，通过对所述第二外延层进行所述离子注入，能够有效减小所述第二外延层的电阻，进而减小最终的接触电阻。
进一步，在本发明的技术方案中，对所述第二外延层进行预非晶化处理。通过对所述第二外延层进行预非晶化处理，能够将所述第二外延层内形成非晶层，从而有利于提高后续由金属硅化物形成的接触层的质量以及质量均一性，从而降低所述半导体结构的肖基特势垒，并使得所述半导体结构的接触电阻得以减小，提高所述半导体结构的电学性能。
附图说明
图1和图2是一种半导体结构形成方法各步骤结构示意图；
图3至图12是本发明实施例中半导体结构方法各步骤结构示意图。
具体实施方式
正如背景技术所述，现有技术中形成的金属接触层质量较差，形成的半导体结构的性能与良率有待提高，以下将结合图1和图2进行说明，图1和图2是一种半导体结构的形成过程实施例的结构示意图。
参考图1，提供衬底100，所述衬底100内具有第一开口(未标示)；在所述第一开口内形成外延层101；在所述衬底100上形成介质层102，所述介质层102内具有暴露出所述外延层101表面的第二开口103；刻蚀所述第二开口103底部暴露出的所述外延层101，在所述外延层101内形成第三开口104。
请参考图2，采用半导体金属化工艺在所述第三开口104的侧壁表面和底部表面形成接触层105。
在上述实施例中，所述第二开口103和所述第三开口104内用于形成导电结构，所述外延层101用于形成晶体管的源区或漏区，形成所述第三开口104用于增大所述导电结构与源区或漏区之间的接触面积，以此减小导电结构与源区或漏区之间的接触电阻。
由于在刻蚀所述外延层101形成所述第三开口104时，所述第三开口104的刻蚀深度是通过控制刻蚀的时间来完成，然而刻蚀工艺对不同材料的刻蚀速率存在着一定的差异，因此通过刻蚀时间来控制刻蚀深度存在着很大的不可控性与不确定性，容易造成外延层被贯穿或是第三开口104深度超过预设的问题。
在此基础上，本发明提供一种半导体结构及其形成方法，在所述衬底内形成第一外延层；在所述第一外延层内形成停止层、以及位于所述停止层表面上的第二外延层；刻蚀所述第二外延层直至暴露出所述停止层的顶部表面为止，形成第四开口；采用半导体金属化工艺在所述第四开口的侧壁表面和底部表面形成接触层。利用所述停止层与所述第二外延层的刻蚀选择性，能够保证刻蚀仅在所述第二外延层内进行，而不会贯穿所述停止层继续向下延伸刻蚀，提高形成所述第四开口的可控性与精确性，进而保证了所述接触层的形成质量，提高形成的半导体结构的性能与良率。
为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细地说明。
图3至图12是本发明实施例中半导体结构形成方法各步骤结构示意图。
请参考图3，提供衬底200，所述衬底200内具有第一开口(未标示)。
在本实施例中，所述衬底200的材料为硅；在其他实施例中，所述衬底的材料还可以为锗、锗化硅、碳化硅、砷化镓或镓化铟；在其他实施例中，所述衬底还可以为绝缘体上的硅衬底或者绝缘体上的锗衬底。
在本实施例中，所述第一开口的形成方法包括：在所述衬底200上形成第一掩膜结构(未图示)；在所述第一掩膜结构上形成第一图形化层(未图示)，所述第一图形化层具有暴露部分所述第一掩膜结构的开口；以所述第一图形化层为掩膜刻蚀部分所述第一掩膜结构与所述衬底，形成所述第一开口；在所述第一开口形成之后，去除所述第一图形化层与所述第一掩膜结构。
在本实施例中，所述第一掩膜结构包括位于所述衬底200上的第一掩膜层、以及位于所述第一掩膜层上的第二掩膜层；在其他实施例中，所述第一掩膜结构开可以为单层掩膜层。
在本实施例中，所述第一掩膜层的材料为掺氮的碳氧化硅；通过掺氮的碳氧化硅所形成的所述第一掩膜层与所述衬底的结合能力好，在后续以刻蚀后的所述第一掩膜层为掩膜刻蚀所述衬底200时，所述第一掩膜层不易发生剥离或曲翘，因此所述第一掩膜层保持刻蚀图形的能力好，有利于使形成于所述衬底200内的所述第一开口形貌良好，有效提升了刻蚀后图形的精准性。
在本实施例中，所述第二掩膜层的材料为氮化钛，所述第二掩膜层与所述第一掩膜层之间的结合能力好，所述第二掩膜层能够在后续刻蚀所述衬底200时保护所述第一掩膜层表面，使所述第一掩膜层不会被减薄；而且，所述第二掩膜层的物理强度较大，在后续刻蚀所述衬底200时，所述第二掩膜层和第一掩膜层的图形能够保持稳定，有利于形成形貌良好的开口。
在其他实施例中，所述第二掩膜层的材料还可以为碳化硅、碳氮化硅、碳氮氧化硅、氮氧化硅、氮化硼或碳氮化硼。
在本实施例中，所述第一掩膜层与所述第二掩膜层采用原子层沉积工艺形成，采用所述原子层沉积工艺形成的所述第一掩膜层与所述第二掩膜层具有均匀、精确的特点，能够保证最终形成的所述第一开口图形良好且精确；在其他实施例中，所述第一掩膜层与所述第二掩膜层还可以采用化学气相沉积或物理气相沉积或旋转涂覆工艺形成。
所述第一图形化层的材料包括光刻胶，所述第一图形化层的形成工艺包括光刻图形化工艺；去除所述第一图形化层的工艺包括湿法去胶工艺或灰化工艺，所述灰化工艺的气体为含氧气体，例如氧气或臭氧。
在本实施例中，去除所述第一掩膜结构采用的工艺为湿法刻蚀工艺；在其他实施例中，去除所述第一掩膜结构采用的工艺还可以为干法刻蚀工艺。
请考图4，在所述第一开口内形成第一外延层201，所述第一外延层201内具有第二开口(未标示)。
在本实施例中，所述第一外延层201的形成工艺采用外延沉积工艺。
请参考图5，在所述第二开口的侧壁表面和底部表面形成停止层202、以及位于所述停止层202表面的第二外延层203。
在本实施例中，所述停止层202与所述第二外延层203形成的工艺也均采用外延沉积工艺；所述停止层202的厚度为1nm～5nm，所述厚度指的是垂直于所述第一开口侧壁表面的方向的尺寸。
所述停止层202的材料为掺杂有第一类型离子的半导体材料；在本实施例中，所述半导体材料包括硅；在其他实施例中，所述半导体材料还可以为锗、锗化硅、碳化硅、砷化镓或镓化铟。
在本实施例中，所述第一外延层201内掺杂有第一类型离子，所述第一外延层201内掺杂第一类型离子的工艺为原位掺杂工艺。
在本实施例中，所述第二外延层203内掺杂有第一类型离子，且所述第二外延层203内的第一类型离子的掺杂浓度小于所述停止层202内的第一类型离子的掺杂浓度。
在本实施例中，所述第二外延层203内掺杂第一类型离子的工艺为原位掺杂工艺。
在本实施例中，所述第一类型离子为P型离子，所述P型离子为硼离子；在其他实施例中，所述P型离子可以为铟离子；在其他实施例中，所述第一类型离子为N型离子，所述N型离子可以为磷离子或砷离子。
在本实施例中，所述停止层202内掺杂的第一类型离子浓度大于1E20/cm3；所述第二外延层203内掺杂的第一类型离子浓度小于1E19/cm3。
请参考图6，在形成所述第二外延层203之后，在所述衬底200上形成介质层204，所述介质层204内具有暴露出所述第二外延层203表面的第三开口205。
在本实施例中，所述介质层204形成于所述衬底200顶部表面、所述第一外延层201顶部表面、所述停止层202顶部表面以及所述第二外延层203顶部表面上。
在本实施例中，所述介质层204和所述第三开口205的形成方法包括：在所述衬底200上形成初始介质层；在所述初始介质层上形成第二掩膜结构(未图示)；在所述第二掩膜结构上形成第二图形化层(未图示)，所述第二图形化层具有暴露部分所述初始介质层的开口；以所述第二图形化层为掩膜刻蚀部分所述第二掩膜结构与所述初始介质层，直至暴露出所述第二外延层的表面为止，形成所述介质层204与所述第三开口205；在形成所述介质层204与所述第三开口205之后，去除所述第二图形化层与所述第二掩膜结构。
所述初始介质层的材料包括二氧化硅、低k介质材料(低k介质材料指相对介电常数低于3.9的介质材料)或超低k介质材料(超低k介质材料指相对介电常数低于2.5的介质材料)。
所述初始介质层的材料为低k介质材料或超低k介质材料时，所述初始介质层的材料为碳硅氧氢化物(SiCOH)、掺氟的二氧化硅(FSG)、掺硼的二氧化硅(BSG)、掺磷的二氧化硅(PSG)、掺硼磷的二氧化硅(BPSG)、氢化硅倍半氧烷或甲基硅倍半氧烷。
在本实施例中，所述初始介质层的材料为超低k介质材料(介电常数小于2.5)，所述超低k介质材料为碳硅氧氢化物(SiCOH)。
形成所述初始介质层的工艺包括原子层沉积工艺、化学气相沉积、物理气相沉积或旋转涂覆工艺形成；在本实施例中，所述初始介质层的形成工艺采用化学气相沉积工艺。
在本实施例中，所述第二掩膜结构采用上述的第一掩膜层与第二掩膜层，在此不作赘述；在其他实施例中，所述第二掩膜结构还可以采用单层结构。
在本实施例中，所述第二图形化层的材料包括光刻胶，所述第二图形化层的形成工艺包括光刻图形化工艺。
去除所述第二图形化层的工艺包括湿法去胶工艺或灰化工艺，所述灰化工艺的气体为含氧气体，例如氧气或臭氧。
请参考图7，在所述第三开口205的侧壁表面形成侧墙206。
在本实施例中，所述侧墙206的材料包括氧化硅；在其他实施例中，所述侧墙的材料还可以为氮化硅。
在本实施例中，所述侧墙206的形成工艺采用原子层沉积工艺；在其他实施例中，所述侧墙的形成工艺还可以包括化学气相沉积工艺或物理气相沉积工艺。
通过在所述第三开口205的侧壁形成所述侧墙206，其目的是为了减小最终形成的导电插塞的特征尺寸。
请参考图8，刻蚀所述第三开口206底部暴露出的第二外延层203直至暴露出所述停止层202为止，在所述第二外延层203内形成第四开口207。
由于停止层202中的掺杂的第一类型离子浓度与第二外延层203中掺杂的第一类型浓度不同，因此刻蚀溶液对所述第二外延层203与所述停止层202之间存在刻蚀选择性，进而能够保证刻蚀仅在所述第二外延层203中进行，直至暴露出所述停止层202为止。
在本实施例中，所述第三开口205底部延伸入所述第二外延层203内，且所述侧墙206位于所述第三开口205侧壁暴露出的第二外延层203侧壁表面。
在本实施例中，所述第四开口207的侧壁具有向所述衬底内凹陷的顶角(西格玛形)，通过西格玛形的第四开口207能够进一步的增大最终形成的接触层的表面积，进而减小接触电阻。
在本实施例中，形成所述第四开口207的工艺为湿法刻蚀工艺；所述湿法刻蚀工艺的刻蚀溶液为碱性溶液。
在本实施例中，所述碱性溶液采用四甲基氢氧化铵溶液(TMAH)。由于四甲基氢氧化铵溶液对硅衬底{100}晶面族和{110}晶面族的刻蚀速率大于对硅衬底{111}晶面族的刻蚀速率，因此，可以将第四开口207处理成呈西格玛形的凹槽，并且四甲基氢氧化铵溶液具有晶向选择性好、刻蚀速率高、无毒、无污染和便于操作等优点。四甲基氢氧化铵溶液中还可以添加表面活化剂(surfactants)。
在其他实施例中，所述碱性溶液还可以采用氨水(NH3·H2O)。
请参考图9，在形成所述第四开口207之后，对所述第二外延层203进行离子注入处理(Ion-implantation，IMP)。
在本实施例中，所述离子注入采用的离子包括硼离子；在其他实施例中，所述离子注入采用的离子包括磷离子或砷离子。
在本实施例中，由于第二外延层203采用的是掺杂有第一类型离子的半导体材料，该种材料的电阻较大，通过对所述第二外延层203进行所述离子注入，能够有效减小所述第二外延层203的电阻，进而减小最终的接触电阻。
请参考图10，在对所述第二外延层203进行离子注入之后，对所述第四开口207进行预非晶化处理(Pre-amorphization Implant，PAI)。
通过对所述第二外延层203进行预非晶化处理，能够将所述第二外延层203内形成非晶层，从而有利于提高后续由金属硅化物形成的接触层的质量以及质量均一性，从而降低所述半导体结构的肖基特势垒，并使得所述半导体结构的接触电阻得以减小，提高所述半导体结构的电学性能。
对所述第二外延层203进行预非晶化离子注入处理的掺杂离子为：碳、锗和硅中的一种或者多种。在本实施例中，所述掺杂离子为碳，所述预非晶化离子注入处理的工艺参数包括：所述掺杂离子的注入能量为5kev至20kev，掺杂离子的注入剂量为4.0e13atom/cm2至2.3e15atom/cm2。
在本实施例中，所述离子注入与所述预非晶化处理中的离子注入均采用倾斜式注入，倾斜注入的角度由所述第三开口205的宽深比决定；通过倾斜式注入离子，能够增大离子覆盖的面积，保证所述第四开口207的底部与侧壁表面均能够得以覆盖。
在本实施例中，后续采用半导体金属化工艺在所述第四开口207的侧壁表面和底部表面形成接触层。具体如图11和图12所示。
请参考图11，在所述第四开口207内形成初始接触层208。
所述初始接触层208的材料为金属，所述金属包括钛、镍或掺杂的铂；在本实施例中，所述初始接触层208的材料为钛。
请参考图12，对所述初始接触层208进行退火处理，形成所述接触层209。
在本实施例中，所述初始接触层208的材料为钛，所述第一外延层201和第二外延层203的材料为硅，因此在所述退火处理的过程中，所述初始接触层208中的钛原子与所述第一外延层201和所述第二外延层203中的硅原子相互扩散并反应，从而形成材料为硅化钛(TiSi)的接触层；在其他实施例中，所述初始接触层还可以为镍，相应的，所述接触层的材料为硅化镍(NiSi)。
在本实施例中，所述退火处理为激光退火处理，所述激光退火处理的工艺压强为一个标准大气压；在其他实施例中，所述退火处理还可以为快速热退火处理。
需要说明的是，为了保证所述金属层与所述第一外延层201和第二外延层203反应的效果，使所形成接触层的厚度和质量满足工艺需求，且避免对所述衬底200内已有的掺杂离子造成不良影响，在本实施例中，退火温度为350℃至700℃。
还需要说明的是，所述接触层209的厚度影响所述接触区域的接触电阻；且当所述接触层的厚度过大时，容易导致所述初始接触层208在所述第四开口207表面的覆盖性较差，所述接触层209中容易出现孔(void)缺陷，从而降低所形成接触层的质量，进而影响所形成半导体结构的电学性能。因此，为了使得所形成半导体结构的电学性能满足工艺需求，所述接触层209的厚度为5nm～30nm。
在本实施例中，采用物理气相沉积工艺形成所述初始接触层208；在其他实施例中，形成所述初始接触层的工艺还可以为化学气相沉积工艺或原子层沉积工艺。
请继续参考图12，相应的，本发明还提供了一种由上述方法所形成的半导体结构，包括：衬底200，所述衬底200具有第一开口；位于所述第一开口内的第一外延层201，所述第一外延层201内具有第二开口；位于所述第二开口侧壁表面和底部表面的停止层202、以及位于所述停止层202表面的第二外延层203；位于所述衬底200上的介质层204，所述介质层204内具有暴露出所述第二外延层203表面的第三开口205；位于所述第二外延层203内的第四开口207，所述第三开口205暴露出所述第四开口207；位于所述第四开口207的侧壁表面和底部表面的接触层209。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (20)

1.一种半导体结构的形成方法，其特征在于，包括：
提供衬底，所述衬底内具有第一开口；
在所述第一开口内形成第一外延层，所述第一外延层内具有第二开口；
在所述第二开口的侧壁表面和底部表面形成停止层、以及位于所述停止层表面的第二外延层；
在形成所述第二外延层之后，在所述衬底上形成介质层，所述介质层内具有暴露出所述第二外延层表面的第三开口；
刻蚀所述第三开口底部暴露出的第二外延层直至暴露出所述停止层为止，在所述第二外延层内形成第四开口；
采用半导体金属化工艺在所述第四开口的侧壁表面和底部表面形成接触层。
2.如权利要求1所述半导体结构的形成方法，其特征在于，所述第一开口的形成方法包括：在所述衬底上形成第一掩膜结构；在所述第一掩膜结构上形成第一图形化层，所述第一图形化层具有暴露部分所述第一掩膜结构的开口；以所述第一图形化层为掩膜刻蚀部分所述第一掩膜结构与所述衬底，形成所述第一开口；在所述第一开口形成之后，去除所述第一图形化层与所述第一掩膜结构。
3.如权利要求1所述半导体结构的形成方法，其特征在于，所述介质层和所述第三开口的形成方法包括：在所述衬底上形成初始介质层；在所述初始介质层上形成第二掩膜结构；在所述第二掩膜结构上形成第二图形化层，所述第二图形化层具有暴露部分所述初始介质层的开口；以所述第二图形化层为掩膜刻蚀部分所述第二掩膜结构与所述初始介质层，直至暴露出所述第二外延层的表面为止，形成所述介质层与所述第三开口；在形成所述介质层与所述第三开口之后，去除所述第二图形化层与所述第二掩膜结构。
4.如权利要求1所述半导体结构的形成方法，其特征在于，所述停止层的材料为掺杂有第一类型离子的半导体材料；所述半导体材料包括硅、锗、锗化硅、碳化硅、砷化镓或镓化铟。
5.如权利要求4所述半导体结构的形成方法，其特征在于，所述第一外延层内掺杂有第一类型离子。
6.如权利要求5所述半导体结构的形成方法，其特征在于，在所述第一外延层内掺杂第一类型离子的工艺为原位掺杂工艺。
7.如权利要求4所述半导体结构的形成方法，其特征在于，所述第二外延层内掺杂有第一类型离子，且所述第二外延层内的第一类型离子的掺杂浓度小于所述停止层内的第一类型离子的掺杂浓度。
8.如权利要求7所述半导体结构的形成方法，其特征在于，在所述第二外延层内掺杂第一类型离子的工艺为原位掺杂工艺。
9.如权利要求7所述半导体结构的形成方法，其特征在于，所述第一类型离子为P型离子或N型离子；所述P型离子包括硼离子或铟离子；所述N型离子包括磷离子或砷离子。
10.如权利要求1所述半导体结构的形成方法，其特征在于，所述第一外延层的形成工艺包括外延沉积工艺；所述停止层的形成工艺包括外延沉积工艺；所述第二外延层的形成工艺包括外延沉积工艺；所述停止层的厚度为1nm～5nm。
11.如权利要求1所述半导体结构的形成方法，其特征在于，在所述第三开口的侧壁表面形成侧墙；所述侧墙的材料包括氧化硅或氮化硅。
12.如权利要求11所述半导体结构的形成方法，其特征在于，形成所述侧墙的工艺包括原子层沉积工艺、化学气相沉积工艺或物理气相沉积工艺。
13.如权利要求11所述半导体结构的形成方法，其特征在于，所述第三开口底部还延伸入所述第二外延层内，且所述侧墙还位于所述第三开口侧壁暴露出的第二外延层侧壁表面。
14.如权利要求1所述半导体结构的形成方法，其特征在于，所述第四开口的侧壁具有向所述衬底内凹陷的顶角。
15.如权利要求14所述半导体结构的形成方法，其特征在于，所述第四开口的形成工艺包括湿法刻蚀工艺；所述湿法刻蚀工艺的刻蚀液为碱性溶液。
16.如权利要求15所述半导体结构的形成方法，其特征在于，所述碱性溶液包括氨水或四甲基氢氧化铵溶液。
17.如权利要求1所述半导体结构的形成方法，其特征在于，在形成所述第四开口之后，形成所述接触层之前，还包括：对所述第二外延层进行离子注入处理；所述离子注入采用的离子包括硼离子、磷离子或砷离子。
18.如权利要求17所述半导体结构的形成方法，其特征在于，在对所述第二外延层进行离子注入之后，形成所述接触层之前，还包括：对所述第二外延层进行预非晶化处理。
19.如权利要求1所述半导体结构的形成方法，其特征在于，所述接触层的形成方法包括：在所述第四开口内形成初始接触层；对所述初始接触层进行退火处理，形成所述接触层；所述初始接触层的材料为金属。
20.一种如权利要求1至19任一项方法所形成的半导体结构，其特征在于，包括：
衬底，所述衬底具有第一开口；
位于所述第一开口内的第一外延层，所述第一外延层内具有第二开口；
位于所述第二开口侧壁表面和底部表面的停止层、以及位于所述停止层表面的第二外延层；
位于所述衬底上的介质层，所述介质层内具有暴露出所述第二外延层表面的第三开口；
位于所述第二外延层内的第四开口，所述第三开口暴露出所述第四开口；
位于所述第四开口的侧壁表面和底部表面的接触层。
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