CN112864120A - 包括电接触部与布置在电接触部上的金属层的半导体装置 - Google Patents
包括电接触部与布置在电接触部上的金属层的半导体装置 Download PDFInfo
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- CN112864120A CN112864120A CN202011355918.XA CN202011355918A CN112864120A CN 112864120 A CN112864120 A CN 112864120A CN 202011355918 A CN202011355918 A CN 202011355918A CN 112864120 A CN112864120 A CN 112864120A
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Abstract
一种半导体装置包括:半导体裸片;电接触部,其布置在所述半导体裸片的表面上;和金属层,其布置在所述电接触部上,其中,所述金属层包括金属箔、金属片、金属引线框架和金属板中的至少一种的被单个化分割的部分。当沿垂直于所述半导体裸片的所述表面的方向观察时,所述电接触部的覆盖区和所述金属层的覆盖区基本上一致。
Description
技术领域
本公开总体上涉及半导体技术。特别地,本公开涉及包括电接触部与布置在电接触部上的金属层的半导体装置。本公开还涉及用于制造这种半导体装置的方法。
背景技术
用于制造半导体装置的半导体晶片变得越来越薄,使得半导体晶片和由其获得的半导体裸片可能遭受弱的机械稳定性。然而,在半导体晶片加工和半导体裸片附接时,可能发生高的热机械应力。半导体装置的制造商一直在努力改进其产品及其制造方法。期望开发具有提高的机械稳定性的半导体装置以及用于制造这种半导体装置的方法。
发明内容
本公开的一方面涉及一种半导体装置。所述半导体装置包括半导体裸片。所述半导体装置还包括布置在半导体裸片的表面上的电接触部。所述半导体装置还包括布置在电接触部上的金属层,其中,所述金属层包括金属箔、金属片、金属引线框架和金属板中的至少一种的被单个化切割的部分。当沿垂直于半导体裸片的表面的方向观察时,电接触部的覆盖区和金属层的覆盖区基本上一致。
本公开的另一方面涉及一种方法。所述方法包括提供包括多个凹部的金属层。所述方法还包括提供包括多个半导体裸片的半导体晶片,其中,每个半导体裸片均包括布置在半导体晶片的表面上的电接触部。所述方法还包括将金属层的位于相邻的凹部之间的区段与电接触部对正。所述方法还包括将电接触部和金属层的所述区段接合。
附图说明
附图被包括以提供对多个方面的进一步理解,并且附图被并入本说明书中并构成其一部分。附图示出了多个方面,并且与描述一起用于解释各方面的原理。通过参考下面的详细描述,可以更好地理解其它方面以及各方面的许多预期优点。附图的元件不一定相对于彼此成比例。相似的附图标记可以指示相应的相似部件。
图1示意性地示出了根据本公开的半导体装置的侧剖视图。
图2A、图2B、图2C、图2D示意性地示出了根据本公开的用于制造半导体装置的方法的侧剖视图。
图3A、图3B、图3C、图3D、图3E、图3F、图3G、图3H、图3I、图3J、图3K、图3L、图3M、图3N、图3O、图3P示意性地示出了根据本公开的用于制造半导体装置的方法。
图4示意性地示出了根据本公开的半导体装置的侧剖视图。
图5示意性地示出了根据本公开的半导体装置的侧剖视图。
具体实施方式
在下面的详细描述中,参考了附图,在附图中通过图示的方式示出了可以实践本公开的特定方面。在这点上,可以参考所描述的附图的取向来使用诸如“顶”、“底”、“前”、“背”等方向性术语。由于所描述的装置的器件可以以许多不同的取向定位,因此方向术语可以用于说明的目的,而绝不是限制性的。在不脱离本公开的概念的情况下,可以利用其它方面并且可以进行结构或逻辑改变。因此,以下详细描述将不以限制意义来理解,本公开的概念由所附权利要求书限定。
以一般方式示出了图1的半导体装置100,以便定性地指定本公开的多个方面。半导体装置100可包括为简单起见未示出的其它方面。例如,可以通过结合根据本公开的其它半导体装置和方法描述的任何方面来扩展半导体装置100。
半导体装置100可以包括半导体裸片2。电接触部4可以布置在半导体裸片2的表面6上。另外,金属层8可以布置在电接触部4上,其中,金属层8包括金属箔、金属片、金属引线框架和金属板中的至少一种的单个化分离部分。当沿垂直于半导体裸片2的表面6的方向观察时,即,沿y 方向观察时,电接触部4的覆盖区和金属层8的覆盖区可以基本上一致。在这点上,表述“基本上一致”可能不一定意味着覆盖区在理想的几何意义上是一致的,而是当在电接触部4和金属层8的制造中考虑到制造公差时,覆盖区也可能彼此稍微偏离。因此,电接触部4和金属层8的覆盖区可以包括小的非重叠部分。例如,电接触部4的覆盖区可以(特别是完全地)布置在金属层8的覆盖区中,反之亦然。在这里可以使用的术语“覆盖区”类似于术语“轮廓”、“外部轮廓”、“形廓”或“外部型廓”。
通常,半导体裸片2可以包括集成电路、无源电子器件、有源电子器件等。集成电路可以被设计为逻辑集成电路、模拟集成电路、混合信号集成电路、功率集成电路等。在一个示例中,半导体裸片2可以由半导体元素材料(例如,Si)制成。在另一示例中,半导体裸片2可以由宽带隙半导体材料或化合物半导体材料(例如SiC、GaN、SiGe、GaAs)制成。半导体裸片2可以用在任何类型的功率应用中,例如,MOSFET(金属氧化物半导体场效应晶体管,Metal Oxide Semiconductor Field Effect Transistor)、半桥电路、包括栅极驱动器的功率模块等。特别地,半导体裸片2可以包括例如功率MOSFET、LV(低压)功率MOSFET、功率IGBT(绝缘栅双极晶体管,Insulated Gate Bipolar Transistor)、功率二极管、超结功率MOSFET等的功率装置或者可以是功率装置的一部分。
还以一般方式示出了图2A-图2D的方法,以便定性地指定本公开的多个方面。所述方法可以包括为简单起见未示出的其它方面。例如,可以通过结合图3A-图3P的方法描述的任何方面来扩展所述方法。图2A-图2D的方法可以至少部分地用于制造类似于图1的半导体装置。
在图2A中,可以提供包括多个凹部(或沟槽或腔)10的金属层8。在图2A的示例中,为简单起见,仅示出了金属层8的包括三个凹部10的区段。金属层8可以进一步在x方向和z方向上延伸(参见水平虚线),并且因此可以包括任意数量的附加凹部10。
在图2B中,可以提供包括多个半导体裸片2的半导体晶片12。每个半导体裸片2可以包括布置在半导体晶片12的表面14上的一个或多个电接触部4。竖直虚线表示稍后可以将半导体晶片12单个化地分割成多个半导体裸片2的位置。
在图2C中,金属层8的相邻凹部10之间的区段16可以与半导体裸片 2的电接触部4对正。当沿y方向观察时,电接触部4的覆盖区和区段16 的覆盖区可以基本上一致。
在图2D中,半导体裸片2的电接触部4和金属层8的区段16可以接合在一起。示例性的接合技术在下面详细说明,并且可能特别地与电接触部4和金属层8的特定材料相关。
图3A-图3P的方法可以看作是图2A-图2D的方法的更详细的实施方式。下面描述的方法的细节因此可以同样地应用于图2A-图2D的方法。另外,制造的半导体装置300可以看作是图1的半导体装置100的更详细的实施方式。
图3A示出了金属层8的俯视图。金属层8的形状可以类似于用于制造根据本公开的半导体装置的半导体晶片或半导体面板的形状。在图3A的示例中,金属层8的形状可以是圆形的。在另一示例中,金属层8的形状可以是正方形或矩形。稍后可以将半导体晶片单个化分割成多个半导体裸片。可以沿着划线执行单个化分割,划线可以形成如图3A所示的小正方形或矩形的网格。
金属层8可以由金属或金属合金制成或者可以包括金属或金属合金,该金属或金属合金被配置为随后与半导体裸片的电接触部接合。特别地,金属层8可以由铜、铜合金、钼和钼合金中的至少一种制成。金属层8可以由金属箔、金属片、金属引线框架和金属板中的至少一种制成或者以包括金属箔、金属片、金属引线框架和金属板中的至少一种。在这方面,金属层8可以仅由一个金属层或由多个金属层的堆叠形成。
在图3B中,可以通过在金属层8的上表面中制造多个凹部10来结构化金属层8。金属层8可以与半导体晶片分开单独地结构化。凹部10可以通过诸如锯切、切割、施加激光束、铣削、湿蚀刻、等离子蚀刻等的任何合适的技术来制造。凹部10的深宽(深度:宽度)比可以具有例如2:1 的值。在图3B的示例中,凹部10可以具有矩形形状。在另一示例中,根据所选择的制造技术,凹部10可以具有圆形形状、V形形状、多边形形状等。为了简单起见,图3B的示例仅示出了布置在金属层8的上表面中的两个凹部10。如稍后将变得明显的是,金属层8中的凹部10的位置可与半导体晶片的划线和将由半导体晶片制造的半导体裸片的电接触部中的至少一个的位置有关。
金属层8在y方向上的厚度可以大于约20微米、或者大于约30微米、或者大于约40微米、或者大于约50微米。金属层8的最大厚度可以例如与切口宽度有关。例如,当仅在一个表面上结构化金属层8时,约30微米的切口宽度可能使得金属层8的最大厚度在约55微米至约65微米的范围内(见图3B)。在双面结构化的情况下(见图3D),约30微米的切口宽度可能使得金属层8的厚度在约90微米至约130微米的范围内。
在图3C中,可以用电绝缘材料18填充凹部10。在填充操作之后,金属层8的上表面和电绝缘材料18的上表面可以是共面的,即可以位于共同的平面中。电绝缘材料18可以包括抗蚀剂、环氧树脂、酰亚胺和模制化合物中的至少一种。模制化合物可包括以下材料中的至少一种:环氧树脂、被填充的环氧树脂、玻璃纤维填充的环氧树脂、酰亚胺、热塑性塑料、热固性聚合物、聚合物共混物。在图3C的示例中,凹部10可以仅部分地延伸到金属层8中,使得凹部10的底表面可以由金属层8的材料形成。在另一示例中,凹部10可以从金属层8的上表面完全延伸到金属层8的下表面。这里,凹部10可以用电绝缘材料18完全填充。特别地,电绝缘材料18的上表面可以与金属层18的上表面共面,电绝缘材料18的下表面可以与金属层8的下表面共面。
图3D示出了可以在两个表面上都被结构化的金属箔8的一个替代性示例。在制造图3D的金属层8时,可在金属层8的相反侧上形成凹部10。可以在金属层8的表面之一中填充电绝缘材料18。在图3D的示例中,电绝缘材料18可以形成布置在金属层8的下表面中的凹部10的底表面。以下描述的操作基于仅在一个表面上结构化的金属层8(参见图3B),但是可以类似地应用于双面结构化金属层8(参见图3D)。
在图3E中,可以例如通过蚀刻和冲压中的至少一种来制造金属层8中的至少两个开口20。开口20可以被配置为用于使金属层8与半导体晶片对正的对正标记。例如,可以通过从半导体晶片去除半导体裸片来制造开口 20。图3E的金属层8示出了示例性数量的四个开口20。
在图3F中,可以提供半导体晶片12。半导体晶片12可以包括半导体衬底22和布置在半导体衬底22中的装置层24。装置层24可以包括微电子装置,所述微电子装置可以已经通过应用诸如掺杂、离子注入、蚀刻、各种材料的薄膜沉积、光刻图案化等的各种微加工工艺集成在半导体衬底22 中。
在图3F的示例中,装置层24可以示例性地包括位于竖直虚线之间的多个半导体装置。特别地,半导体装置可以是诸如功率晶体管、功率二极管等的功率半导体装置。在示出的示例中,半导体装置可以是功率MOSFET 26,其中,每个集成功率MOSFET 26包括布置在半导体晶片12的上表面上的两个电接触部4A、4B。例如,电接触部4A、4B可以由铜、铜合金、钼和钼合金中的至少一种制成。电接触部4A和4B可以分别对应于功率 MOSFET 26的源极触点和栅极触点,并且可以电耦合到装置层24中的相应电子结构。功率MOSFET 26的漏极触点可以稍后制造。在图3F的示例中,功率MOSFET 26可以具有竖直结构,即功率MOSFET 26可以包括布置在功率MOSFET 26的两个主面之上的电极,使得电流可以基本上在竖直的y方向上流动。在另一示例中,功率MOSFET 26可以具有侧向结构,即功率MOSFET 26可以包括布置在主面中的一个之上的电极,使得电流可以基本上在侧向的x方向上流动。
在图3F中,可以提供金属层8。金属层8可以包括填充有电绝缘材料 18的多个凹部以及布置在填充的凹部之间的区段16。当沿y方向观察时,区段16的覆盖区可以与电接触部4A、4B的覆盖区基本上一致。
金属层8的区段16可以与电接触部4A、4B对正,使得一个区段16 可以相应布置在电接触部4A、4B中的相应的一个之上。因此,填充有电绝缘材料18的凹部可与半导体晶片12的划线28和/或与半导体晶片12的布置在电接触部4A、4B之间的区段对正。通过使用金属层8的开口20作为对正标记,可以提供正确的对正(见图3E)。在对正操作期间,金属层8 可以布置在临时载体(未示出)之上,所述临时载体可以随后被去除。例如,金属层8可以通过胶、夹持环和夹持板中的至少一种固定到临时载体。
在图3G中,电接触部4A、4B和金属层8的区段16可以被使得机械接触并可以接合在一起。更特别地,电接触部4A、4B的上表面可以接合到区段16的下表面。例如,接合操作可以包括扩散结合操作、预烧结操作和烧结操作中的至少一种。可以在电接触部4A、4B与金属层8的相应区段16之间获得金属与金属的接合。根据所选择的接合技术,金属与金属接合部可以包括结合接合部和烧结接合部中的至少一个。例如,金属与金属的接合可以在所接合的金属的晶粒结构中包括不均匀性。也就是说,即使当电接触部4A、4B和金属层8可以由相同或相似的材料制成时,金属与金属的接合仍然可以通过适当的检测技术来检测。
在一个示例中,电接触部4A、4B和金属层8的区段16可以通过施加扩散结合操作来接合。扩散结合操作的温度可以在约100摄氏度至约260 摄氏度的范围内、更特别地在约160摄氏度至约240摄氏度、更特别地约 180摄氏度至约220摄氏度的范围内。扩散结合操作的示例性特定温度值可以为约200摄氏度。扩散结合操作的持续时间可以在约5分钟至约3小时的范围内、更特别地在约15分钟至约2小时、更特别地在约30分钟至约1 小时的范围内。在一个示例中,扩散结合操作可以基于两步法,包括基于上述提到的工艺参数的第一步骤。在第二步骤中,温度可以增加到在约380 摄氏度至约420摄氏度的范围内的更高的值。
在另一示例中,电接触部4A、4B和金属层8的区段16可以通过施加预烧结操作而接合。预烧结操作的温度可以在约160摄氏度至约240摄氏度的范围内、更特别地在约180摄氏度至约220摄氏度的范围内。预烧结操作的示例性特定温度值可以为约200摄氏度。预烧结操作的持续时间可以在约1分钟至约30分钟的范围内、更特别地在约5分钟至约30分钟的范围内。在预烧结操作过程中施加的压力可以特别地与待接合的材料有关,并且可以在约15MPa至约30MPa的范围内。附加的烧结操作可以随后施加。
在图3H中,材料可以从金属层8的上表面去除(参见箭头),直到电绝缘材料18的上表面暴露为止。对于电绝缘材料18已经从金属层8的上表面完全延伸到金属层8的下表面的情况,可以不需要去除材料。例如,去除材料可以包括磨削操作和蚀刻操作中的至少一种。在这方面,电绝缘材料18可以被配置成在材料去除操作期间保护功率MOSFET 26的上部结构。此外,电绝缘材料18可以被配置成在去除材料期间稳定金属层8。去除金属层8的材料可能会导致该配置的上表面平坦化。即,在去除金属层8 的材料之后,金属层8的上表面和电绝缘材料18的上表面可以是共面的,即可以位于共同的平面中。去除导电材料可以消除短路的风险。另外,可以从在随后的单个化分割操作中可以施加激光辐射的区域去除导电材料。
在图3I中,可以去除(牺牲性的)电绝缘材料18。在这方面,电接触部4A、4B之间的距离特别地可以足够大,以允许进行这种去减过程。去除电绝缘材料18的技术可以与相应的材料类型有关。例如,可以通过施加抗蚀剂清洁剂来去除抗蚀剂。在去除电绝缘材料18之后,可以施加进一步的烧结操作。烧结操作的温度可以在约250摄氏度至约400摄氏度的范围内。另外,可以通过将抗蚀剂、模制化合物和环氧树脂中的至少一种施加到半导体晶片12的上表面来执行封装操作(未示出)。
在图3J中,可以将胶30施加到半导体晶片12的上表面。特别地,所施加的胶30可以覆盖电接触部4A、4B的侧表面和上表面。另外,(临时的)载体32可以被布置在所施加的胶30之上。胶30可以是可固化的,例如通过施加紫外线(UV)电磁辐射。据此,载体32在UV范围内可以是透明的,以便允许UV辐射通过其材料。在一个示例中,载体32可以由玻璃材料制成。胶30的材料特性可以对图3A-图3P的制造操作具有限制作用。例如,胶30可以仅在有限的时间内承受最高温度。这种最高温度的示例性值可以是约270摄氏度。在更特定的示例中,胶30仅可承受约200摄氏度的温度约20分钟。特别地,胶30的材料特性可能对烧结过程的温度和/或持续时间具有限制作用。
在图3K中,图3J的布置可以翻转,即,翻转180度(参见箭头)。另外,半导体晶片12的背侧可以例如通过施加磨削操作和蚀刻操作中的至少一种来薄化。通过薄化半导体晶片12,可以去除半导体晶片12的多余的半导体材料。在薄化操作之后,可以至少保留装置层24。薄化后的半导体晶片12沿y方向的厚度可以与集成在半导体材料中的微电子装置的类型有关。例如,厚度可以小于约80微米、或者小于约60微米、或者小于约40微米、或者小于约20微米、或者小于约10微米、或者小于约5微米。包括LV 功率MOSFET的薄化的半导体晶片12的厚度的示例性值甚至可以低至约3 微米。
在图3L中,电接触部4C可以例如通过应用适当的金属化技术在装置层24的上表面上制造。在图3L的示例中,电接触部4C可以在金属化过程之后已经结构化。在另一示例中,可以在装置层24的基本上整个上表面之上制造非结构化的金属化层,并且可以稍后通过单个化分割工艺、例如使用多束纳秒激光形成电接触部4C。
在图3L的示例中,电接触部4C可以对应于功率MOSFET 26的漏极触点,其可以电连接到装置层24中的相应电子结构。类似于电接触部4A、 4B,电接触部4C可以由铜、铜合金、钼和钼合金中的至少一种制成。电接触部4C在y方向上的厚度可以与可用于稍后将电接触部4C接合到金属层上的技术有关。在烧结技术的情况下,电接触部4C在y方向上的厚度可以在约10微米至约100微米的范围内。更特别地,所述厚度可以在约10 微米至约30微米的范围内,或者在约50微米至约100微米的范围内。在扩散结合技术的情况下,电接触部4C在y方向上的厚度可以小于约10微米、更特别地小于约5微米。
在图3L中,可以提供另一金属层8。金属层8可以包括多个凹部10 和布置在它们之间的区段16。当沿y方向观察时,区段16的覆盖区可以与电接触部4C的覆盖区基本上一致。在图3L的示例中,金属层8中的凹部 10可以保持未被填充。在另一示例中,凹部10可以填充有(牺牲性的)电绝缘材料,如结合先前的附图所讨论的。
金属层8的区段16可以与电接触部4C对正,使得一个区段16可以相应地布置在电接触部4C中的一个之上。因此,凹部10可以与半导体晶片 12的划线28对正。可以通过使用金属层8的开口20作为对正标记来获得正确的对正。
在图3M中,类似于图3G,电接触部4C和金属层8的区段16可以被使得机械接触并且可以接合在一起。在接合操作之后,可以从金属层8的上表面去除材料,直到金属层8的区段16彼此分离为止。例如,可以通过施加磨削操作和蚀刻操作中的至少一种来去除材料。去除材料可能会导致该布置的上表面的平坦化。即,在去除金属层8的材料之后,金属层8的分离区段的上表面可以是共面的,即可以位于共同的平面中。
在图3N中,图3M的布置可以翻转(参见箭头)。可以将翻转的布置放置在例如锯切框架的临时载体34上。胶30可以固化,例如通过施加穿过载体32的UV辐射,使得载体32和胶30可以被去除。
在图3O中,可通过去除半导体晶片12的各个功率MOSFET 26之间的半导体材料将布置单个化分割成多个半导体装置300。单个化分割操作可以包括锯切、切割、施加激光束、铣削、蚀刻中的至少一种。单个化分割后的功率MOSFET 26的漏极触点4C可以基本上覆盖半导体装置300的整个下表面。
在图3O的示例中,每个制造的半导体装置300可以分别在每个电接触部4A至4C之上包括金属层8。在另一示例中,所制造的半导体装置可以仅在半导体装置的上表面上的电接触部4A、4B之上包括金属层。在又一示例中,所制造的半导体装置可以仅在半导体装置的下表面上的电接触部 4C之上包括金属层。
在图3P中,可以在裸片附接操作中去除载体34,并且可以将一个或多个半导体装置300布置在引线框架36上。半导体装置300可以被进一步处理,其中,为了简单起见,这里没有明确描述其它可能的处理操作。在示例性的进一步操作中,半导体装置300可以由模制化合物包封并且随后被单个化分割成多个封装的半导体装置。
图4的半导体装置400可以看作是图1的半导体装置100的更详细的实施方式。例如,半导体装置400可以根据图3A-3P的方法来制造。
半导体装置400可以包括半导体裸片2。在图4的示例中,半导体裸片 2可以包括功率MOSFET,所述功率MOSFET具有布置在半导体裸片2的上表面上的两个电接触部4A、4B和布置在半导体裸片2的下表面之上的第三电接触部4C。中间导电层可以布置在半导体裸片2与电接触部4A、 4B之间。电接触部4A和4B可以分别对应于半导体裸片2的源极触点和栅极触点。另外,电接触部4C可以对应于半导体裸片2的漏极触点。金属层8A至8C可以分别布置在电接触部4A至4C之上。金属层8A至8C中的每一个可以包括或可以对应于金属箔、金属片、金属引线框架和金属板中的至少一种的被单个化分割的部分。当沿y方向观察时,电接触部4A至 4C的覆盖区和金属层8A至8C的覆盖区可以分别基本上一致。在另一示例(未示出)中,半导体裸片2可以包括双极晶体管,其中电接触部4A至 4C可以对应于基极、发射极和集电极。
半导体裸片2在y方向上的厚度可以小于约80微米、或者小于约60 微米、或者小于约40微米、或者小于约20微米、或者小于约10微米、或者小于约5微米。LV功率MOSFET的厚度的示例性值甚至可以低至约3 微米。
金属层8A至8C在y方向上的厚度可以在约40微米至约130微米的范围内。
电接触部4A、4B在y方向上的厚度可以小于约15微米、或者小于约 10微米。电接触部4C在y方向上的厚度可以与可能已经用于将电接触部 4C和金属层8C接合的技术有关。在烧结技术的情况下,电接触部4C在y 方向上的厚度可以在约10微米至约100微米的范围内。更特别地,所述厚度可以在约10微米至约30微米的范围内,或者在约50微米至约100微米的范围内。在扩散结合技术的情况下,电接触部4C在y方向上的厚度可以小于约10微米、更特别地小于约5微米。
由于在电接触部4A至4C之上布置了附加的金属层8A至8C,因此与传统半导体装置相比,半导体装置400在y方向上的总厚度可以增加。增加的厚度可以提供增加的机械稳定性,例如在裸片附接时可承受住热机械应力。这例如可以在拾取-放置过程中提高效率。
由于在电接触部4A至4C之上布置附加金属层8A至8C,所以电接触部4A至4C的厚度可以被选择为比常规半导体装置的相应电接触部的厚度小。因此,用于制造电接触部4A至4C的金属化操作可以减少或者甚至完全省略。减少的金属化操作可以节省制造相应的半导体装置的成本。
图5的半导体装置500可以至少部分类似于图4的半导体装置400。与图4相比,半导体装置500可以仅包括一个布置在半导体裸片2的下表面上的电接触部4C之上的金属层8C。在又一个示例(未示出)中,制造的半导体装置可以仅包括布置在半导体裸片2的上表面上的电接触部4A、4B 之上的金属层4A、4B。
示例
在下文中,将借助于示例解释半导体装置及其制造方法。
示例1是一种半导体装置,包括:半导体裸片;电接触部,其布置在半导体裸片的表面上;和金属层,其布置在电接触部上,其中,金属层包括金属箔、金属片、金属引线框架和金属板中的至少一种的被单个化分割的部分,其中,当沿垂直于半导体裸片的所述表面的方向观察时,电接触部的覆盖区和金属层的覆盖区基本上一致。
示例2是根据示例1的半导体装置,其中,所述半导体裸片在垂直于所述半导体裸片的表面的方向上的厚度小于80微米。
示例3是根据示例1或2的半导体装置,其中,所述金属层在垂直于所述半导体裸片的表面的方向上的厚度在40微米至130微米的范围内。
示例4是根据前述示例中任一项的半导体装置,其中,所述电接触部在垂直于所述半导体裸片的表面的方向上的厚度小于15微米。
示例5是根据前述示例中任一项的半导体装置,其中,所述半导体裸片包括功率半导体装置。
示例6是根据前述示例中任一项的半导体装置,其中,所述金属层和所述电接触部中的至少一个由铜、铜合金、钼和钼合金中的至少一种制成。
示例7是根据前述示例中任一项的半导体装置,所述半导体装置还包括:在电接触部与金属层之间的金属与金属接合部,其中,所述金属与金属接合部包括结合接合部和烧结接合部中的至少一个。
示例8是根据前述示例中任一项的半导体装置,其中,所述金属层和所述电接触部中的每一个覆盖半导体裸片的整个表面。
示例9是根据前述示例中任一项的半导体装置,所述半导体装置还包括:布置在半导体裸片的另一表面上的另一电接触部;和布置在所述另一电接触部上的另一金属层,其中,当沿垂直于所述另一表面的方向观察时,所述另一电接触部的覆盖区和所述另一金属层的覆盖区基本上一致。
示例10是一种方法,包括:提供包括多个凹部的金属层;提供包括多个半导体裸片的半导体晶片,其中,每个半导体裸片包括布置在半导体晶片的表面上的电接触部;将金属层的位于相邻的凹部之间的区段与电接触部对正;和将电接触部和金属层的所述区段接合。
示例11是根据示例10的方法,其中,当沿垂直于所述半导体晶片的表面的方向观察时,所述电接触部的覆盖区和所述金属层的所述区段的覆盖区基本上一致。
实施例12是根据实施例10或11的方法,其中,将所述电接触部和所述金属层的所述区段接合包括扩散结合操作、预烧结操作和烧结操作中的至少一个。
示例13是根据示例10-12中任一项的方法,所述方法还包括:将金属层的凹部与半导体晶片的划线对正。
示例14是根据示例10-13中任一项的方法,所述方法还包括:在将电接触部和金属层的所述区段接合之前,用电绝缘材料填充所述凹部。
示例15是根据示例14的方法,其中,所述电绝缘材料包括抗蚀剂、环氧树脂、酰亚胺和模制化合物中的至少一种。
示例16是根据示例14或15的方法,所述方法还包括:在将电接触部和金属层的所述区段接合之后,从金属层的表面上去除材料,直到在金属层的表面上露出电绝缘材料为止;和去除电绝缘材料。
示例17是根据示例10-16中任一项的方法,其中,所述金属层包括金属箔、金属片、金属引线框架和金属板中的至少一种。
示例18为根据示例10-17中任一项的方法,所述方法还包括:在金属层中提供至少两个开口;和基于使用所述开口作为对正标记将金属层与半导体晶片对正。
示例19是根据示例10-18中任一项的方法,所述方法还包括:将金属层和半导体晶片单个化分割成多个半导体装置。
如在本说明书中采用的,术语“连接”、“耦合”、“电连接”和/或“电耦合”可能不一定意味着元件必须直接连接或耦合在一起。可以在“连接”、“耦合”、“电连接”或“电耦合”元件之间设置居间元件。
进一步地,例如在对象的表面“之上”形成或定位材料层中所使用的词语“在...之上”在本文中可以用来表示材料层可以“直接”位于(例如形成、沉积等在)相应表面上,例如与相应表面直接接触。例如在表面“之上”形成或定位的材料层中所使用的词语“在...之上”在本文中也可以用来表示材料层可以“间接”位于(例如形成、沉积等在)相应表面上,例如在相应表面与材料层之间布置一个或多个附加层。
此外,就在详细描述或权利要求书中使用的术语“具有”、“包含”、“包括”、“带有”或其变体而言,意在以类似于术语“包括”的方式表示开放式包括。即,如本文中所使用的,术语“具有”、“包含”、“包括”,“带有”、“包括”等是开放式术语,其指示所陈述的元件或特征的存在,但是不排除其它元件或特征。除非上下文另外明确指出,否则冠词“一个”、“一种”和“所述”旨在包括复数和单数。
此外,词语“示例性”在本文中用来表示用作示例、实例或说明。本文中被描述为“示例性”的任何方面或设计不必被解释为优于其它方面或设计。而是,示例性一词的使用旨在以具体方式呈现概念。如在本申请中使用的,术语“或”旨在表示包括性的“或”而不是排他性的“或”。也就是说,除非另有说明或从上下文可以清楚得知,否则“X使用A或B”旨在表示任何自然的包含性排列。也就是说,如果X使用A;X使用B;或X使用A和B两者,则在任何前述情况下都满足“X使用A或B”。另外,在本申请和所附权利要求书中使用的冠词“一个”和“一种”通常可以被解释为意指“一个或多个”,除非另有说明或从上下文清楚地指向单数形式。另外,A和B等中的至少一个通常是指A或B或者A和B两者。
本文描述了装置和用于制造装置的方法。结合所描述的装置做出的评论对于相应的方法也可以成立,反之亦然。例如,如果描述了装置的特定器件,则用于制造装置的相应方法可以包括以合适的方式提供器件的操作,即使该操作未在图中明确描述或示出。
尽管已经相对于一个或多个实施方式示出和描述了本公开,但是本领域的其它技术人员可至少部分地基于对本说明书和附图的阅读和理解来进行等同的变更和修改。本公开包括所有这样的修改和变更,并且仅由所附权利要求的概念限制。特别是关于由上述器件(例如元件、资源等)执行的各种功能,除非另有说明,否则用于描述这些器件的术语旨在对应于执行所述器件的指定功能(例如,在功能上等效)的任何器件,即使在结构上不等同于在本文中示出的示例性实施方式中执行该功能所公开的结构。另外,尽管可能已经相对于几种实施方式中的仅一种实施方式公开了本公开的特定特征,但这种特征可以与其它实施方式的一个或多个其它特征组合,只要对于任何给定的或特定的应用可能是期望的和有利的。
Claims (11)
1.一种方法,包括:
提供包括多个凹部(10)的金属层(8);
提供包括多个半导体裸片(2)的半导体晶片(12),其中,每个所述半导体裸片(2)包括布置在所述半导体晶片(12)的表面(14)上的电接触部(4);
将所述金属层(8)的位于相邻的凹部(10)之间的区段(16)与所述电接触部(4)对正;
将所述电接触部(4)和所述金属层(8)的所述区段(16)接合;和
在所述接合之后,对半导体晶片(12)的背侧进行薄化。
2.根据权利要求1所述的方法,其中,在对半导体晶片(12)的背侧进行薄化之前,胶(30)施加到所述半导体晶片(12)的所述表面(14),所述胶(30)覆盖所述电接触部(4)的侧表面和上侧。
3.根据权利要求1或2所述的方法,其中,当沿垂直于所述半导体裸片(2)的所述表面(14)的方向观察时,所述电接触部(4)的覆盖区和所述金属层(8)的所述区段(16)的覆盖区一致。
4.根据权利要求1-3中任一项所述的方法,其中,将所述电接触部(4)和所述金属层(8)的所述区段(16)接合包括扩散结合操作、预烧结操作和烧结操作中的至少一个。
5.根据权利要求1-4中任一项所述的方法,其中,所述方法还包括:
将所述金属层(8)的凹部(10)与所述半导体晶片(12)的划线对正。
6.根据权利要求1-5中任一项所述的方法,其中,所述方法还包括:
在将所述电接触部(4)和所述金属层(8)的所述区段(16)接合之前,用电绝缘材料(18)填充所述凹部(10)。
7.根据权利要求6所述的方法,其中,所述电绝缘材料(18)包括抗蚀剂、环氧树脂、酰亚胺和模制化合物中的至少一种。
8.根据权利要求6或7所述的方法,其中,所述方法还包括:
在将所述电接触部(4)和所述金属层(8)的所述区段(16)接合之后,从所述金属层(8)的表面上去除材料,直到在所述金属层(8)的表面处露出所述电绝缘材料(18);和
去除电绝缘材料(18)。
9.根据权利要求1-8中任一项所述的方法,其中,所述金属层(8)包括金属箔、金属片、金属引线框架和金属板中的至少一种。
10.根据权利要求1-9中任一项所述的方法,其中,所述方法还包括:
在所述金属层(8)中提供至少两个开口(20);和
基于使用所述开口(20)作为对正标记将所述金属层(8)与所述半导体晶片(12)对正。
11.根据权利要求1-10中任一项所述的方法,其中,所述方法还包括:
将所述金属层(8)和所述半导体晶片(12)单个化分割成多个半导体装置。
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