CN111952191A - 通过在安装电子部件之后将片材分成载体而进行的封装的批量制造 - Google Patents

通过在安装电子部件之后将片材分成载体而进行的封装的批量制造 Download PDF

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CN111952191A
CN111952191A CN202010406422.4A CN202010406422A CN111952191A CN 111952191 A CN111952191 A CN 111952191A CN 202010406422 A CN202010406422 A CN 202010406422A CN 111952191 A CN111952191 A CN 111952191A
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sheet
electronic component
package
carrier
encapsulant
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Inventor
T·迈尔
T·贝伦斯
A·格拉斯曼
M·格鲁贝尔
T·沙夫
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Infineon Technologies AG
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Infineon Technologies AG
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Abstract

一种制造封装(100)的方法，其中，所述方法包括：提供至少在安装区(103)中连续的导电的片材(102)；将多个电子部件(104)的第一主表面安装在片材(102)的连续的安装区(103)上；形成用于使电子部件(104)的第二主表面与片材(102)电耦合的互连结构(106)，其中，第二主表面与第一主表面相对；以及在所述形成之后对片材(102)进行结构化。

Description

通过在安装电子部件之后将片材分成载体而进行的封装的批 量制造
背景技术
本发明涉及制造封装的方法以及封装。
封装可以包括安装在载体(例如，引线框架)上的电子部件(例如，半导体芯片)。封装可以被体现为安装在载体上的被包封的电子部件，其具有延伸到包封物外并且与电子外围耦合的电连接。
发明内容
可能存在对有效率地制造封装的需求。
根据示例性实施例，提供了一种制造封装的方法，其中，所述方法包括：提供至少在安装区中连续的导电的片材；将多个电子部件的第一主表面安装在片材的连续的安装区上；形成用于使所述电子部件的第二主表面与片材电耦合的互连结构，其中，第二主表面与第一主表面相对；以及在所述形成之后对片材进行结构化。
根据另一个示例性实施例，提供了一种制造封装的方法，其中，所述方法包括：提供导电的基本连续的片材；将在操作期间具有垂直电流流动的多个电子部件安装在片材上；通过包封物至少部分地包封所述电子部件；以及在包封之后，从片材的未包封的背面对片材进行图案化，由此形成用于每一封装的各个载体。
根据又一个示例性实施例，提供了一种封装，其中，所述封装包括：被结构化成通过至少一个缝隙隔开的多个子结构的载体；以其下主表面安装在载体上的至少一个电子部件；使至少一个电子部件的上主表面与载体电耦合的至少一个互连结构；以及以使得至少一个缝隙不被包封的方式至少部分地包封至少一个电子部件并且部分地包封载体的包封物。
根据示例性实施例，提供了一种同时制作多个封装的制造架构，其中，在将片材结构化或图案化成用于各个封装的单独的载体前，使用导电的并且基本上或者完全连续的片材来支撑部件、互连结构和包封物。通过采取这种措施，所述连续的片材可以在制造工艺的很大部分期间充当强机械支撑结构，其简化了对微小电子部件的操纵，并且其也使得互连结构的形成变得简单。只有在制造工艺的非常晚的阶段上，并且特别是在已经形成了使所安装的电子部件的上主表面与片材的上主表面连接的互连结构之后，然后才将片材结构化成单独的、并且特别是不连续的部分。然后这样的部分可以形成用于机械承载并电连接(一个或多个)相应的电子部件的载体。因而，能够获得一种有效的、简单的并且具有失败鲁棒性的制造大量具有高可靠性的封装的方法。
作为所描述的制造工艺的结果，所获得的封装可以具有通过未被包封物材料覆盖的一个或多个缝隙分开的载体部分，因为通过缝隙分开的载体部分只有在包封之后才被制作成片材的图案化的部分。因而，在包封发生时，缝隙先前已经填充有片材材料。
根据示例性实施例，可以通过并行处理，在大幅面地施加包封或壳(例如，通过模制)之后和/或在施加第一级互连之后，将导电的、连续的片材结构化成用于封装的载体(例如，铜引线框架)。这可以允许以低工作量和高灵活性进行面板封装并且允许预封装选项。
其他示例性实施例的描述
在下文中，将解释所述方法和封装的其他示例性实施例。
在本申请的语境下，术语“封装”特别可以指包括安装在载体上并且任选地使用包封物进行封装的一个或多个电子部件的电子器件。此外，任选地，可以在封装中实施一个或多个导电接触元件或互连结构(例如，接合线或夹)，例如以使电子部件与载体耦合。
在本申请的语境下，术语“连续的片材”特别可以指平的层或板状的结构至少在其中央区段中没有通孔，在制造工艺期间将在中央区段中将电子部件安装在该片材上。导电的、连续的片材可以包括导电材料，并且任选额外地包括电绝缘材料，或者可以唯独由导电材料构成。例如，连续的片材可以是铜箔或板。
在本申请的语境下，术语“基本上连续的片材”特别可以指在前一段中被描述为在安装区(特别是片材的中央区，例如，其可以占据片材表面的至少90％)中连续的片材，电子部件将被安装在该安装区中。然而，例如，该片材有可能具有处于其外围部分中(例如，处于安装区外部)的一个或多个对准凹陷。在这样的外围部分中，也可以提供用于简化用户或机器对片材的操纵的操纵构造。然而，这样的对准凹陷、操纵构造等没有用于限定将基于这样的基本上连续的片材而制造的封装的载体。
在本申请的语境下，术语“电子部件”特别可以包含半导体芯片(特别是功率半导体芯片)、有源电子器件(例如，晶体管)、无源电子器件(例如，电容或电感或欧姆电阻)、传感器(例如，麦克风、光传感器或气体传感器)、致动器(例如，扬声器)和微机电系统(MEMS)。特别地，电子部件可以是在其表面部分中具有至少一个集成电路元件(例如，二极管或晶体管)的半导体芯片。电子部件可以是裸的管芯，或者可以是已经封装或包封的。
在本申请的语境下，术语“互连结构”特别可以指电子部件和片材之间的导电连接(其中，片材可以充当相应的载体的预制件)。这些互连结构可以是在所述片材之外额外提供的，即，可以是与所述片材分开的结构。例如，这样的互连结构可以形成第一级互连，并且可以(例如)由夹、接合线和/或接合带构成。
在本申请的语境下，术语“包封物”特别可以指包围(例如，密封地包围)电子部件并且任选包围载体的部分以在操作期间提供机械保护、电绝缘并且任选提供散热贡献的基本上电绝缘并且优选地导热的材料。例如，这样的包封物可以是模制化合物。
在实施例中，导电的、连续的片材也可以是导热的。例如，其可以通过铜和/或铝的片材材料来实现。在基于所述片材形成单独的载体之后，然后还可以同时使用所述片材在封装的操作期间从电子部件去除热量。
在实施例中，所述方法包括在结构化之前通过包封物至少部分地包封电子部件和互连结构。因而，在其期间连续的、导电的片材保持一体结构而不被图案化成载体区段的该制造工艺的部分可以扩展为也包括包封工艺。在这样的实施例中，也可以在包封期间，特别是在模制期间维持连续的片材的机械支撑功能。
在实施例中，所述方法包括对片材进行结构化，由此形成用于每一封装的各个载体。在本申请的语境下，术语“载体”特别可以指用于承载一个或多个电子部件的支撑结构，即，充当一个或多个电子部件的机械支撑。这样的载体也有助于(一个或多个)电子部件与封装的外围之间的电互连，例如，这样的载体可以包括导电连接结构，和/或可以通过相应的互连结构与电子部件的一个或多个焊盘耦合。换言之，载体可以实现机械支撑功能和/或任选的电连接功能。通过这样的结构化或图案化过程分开的每一载体可以被具体分配给专用的封装以及电子部件的至少其中之一。换言之，可以将电子部件中的相应一个安装在载体中的每者上。还有可能将多个电子部件安装在同一载体上。
在实施例中，所述方法包括将结构化之后获得的结构分成单独的封装，每一封装至少包括载体之一、电子部件的至少其中之一、互连结构的至少其中之一和包封物的部分。通过采取这种措施，可以获得多个封装，每一封装包括通过所述互连结构中的相应一个进行电连接并且通过诸如模制化合物的包封物进行包封的处于相应的载体上的至少一个电子部件。因而，在这样的制造过程的末尾，可以获得具有所提及的构造的多个封装或模块。
在实施例中，所述方法包括对片材进行结构化，从而使载体中的每者包括管芯焊盘和多条引线。因而，所述方法可以包括对片材进行结构化，由此形成引线框架结构。换言之，可以通过这样的方式执行图案化或结构化过程，从而限定用于每一后来的封装的单独的引线框架部分。在这样的实施例中，可以将相应的电子部件安装在管芯焊盘上。引线可以在朝外的方向上延伸并且可以与管芯焊盘分开，从而充当用于在包封之后电接触被包封的电子部件的端子。电子部件与引线之间的电耦合可以通过互连结构来完成，该互连结构可以使电子部件的主表面与引线中的相应一条的接触表面电桥接，并且由此耦合。
引线框架因而可以包括一组焊盘，例如，管芯焊盘以及另外的一个或多个接合焊盘。引线框架可以是片材状金属结构，其可以被图案化从而形成在将(一个或多个)电子部件安装在引线框架上时用于安装所述封装的一个或多个电子部件的一个或多个管芯焊盘或安装区段，以及用于将所述封装电连接至电子环境的一个或多个引线区段。在实施例中，引线框架可以是可以(例如)通过蚀刻或激光处理进行图案化的金属板(特别由铜制成)。将芯片载体形成为引线框架是经济有效的，并且是机械和电学方面有利的配置方式，其中，能够使所述至少一个电子部件的低欧姆连接与引线框架的鲁棒支撑能力相结合。此外，作为引线框架的金属材料(特别是铜)的高热导率的结果，引线框架可以有助于封装的热传导，并且可以去除在(一个或多个)电子部件的操作期间生成的热。引线框架可以包括(例如)铝和/或铜。在本申请的语境下，术语“管芯焊盘”特别可以指形状和尺寸被设定为容纳诸如半导体芯片的电子部件的引线框架的部分。对应地，管芯焊盘的表面面积通常是扁平且平面的，并且充分大以将芯片或管芯完全接纳于其上。与此对照，术语“引线”特别可以指引线框架的另一部分，其至少部分地延伸超出包封物(如果存在的话)，并且充当通往封装的电子外围的连接元件。例如，有可能安装在管芯焊盘上的电子部件的一个或多个端子通过(例如)夹、接合线或接合带电连接至引线中的相应一条。例如，有可能管芯焊盘是被包封的，并且引线相对于包封物部分或完全暴露。还有可能管芯焊盘形成引线框架型载体的中央部分，而引线可以形成引线框架的外围部分。管芯焊盘和引线两者可以至少部分地包括金属材料。更一般地，载体可以部分或完全为金属结构。
然而，就不同的实施例而言，可以使用很多不同的载体，并且所描述的引线框架只是有利地可使用的载体的示例。
在实施例中，所述方法包括在将电子部件安装在安装区段中之前，暂时将支撑板连接至片材。例如，这样的支撑板可以由塑料、陶瓷或足够厚的金属制成，从而在电子部件的组装期间以及包封期间适当地支撑连续的片材。在已经履行了这一支撑功能之后，并且在已经完成了包封之后，可以从该结构再次去除该临时的支撑板，因为包封的完成已经使得该结构即使没有临时的支撑板也具有足够的鲁棒性。然后可以重复使用或循环利用该临时的支撑板，以实施另一制造工艺，或者可以将该临时的支撑板废弃。使用某种任选的支撑板还允许使用非常薄的片材，例如，铜箔。这使得所述易于制造的封装紧凑并且轻巧。
在实施例中，所述方法包括在片材中形成盲孔以及随后将电子部件安装在盲孔中。通过形成盲孔(例如，通过对该连续的片材进行半蚀刻)，可以形成用于容纳电子部件的容纳体积。一方面，其简化了电子部件的组装工艺，并且确保了电子部件被组装并且明确保持在希望位置处。另一方面，其还确保了可以以紧凑的方式制造具有非常薄的垂直尺寸的封装。
在替代实施例中，片材的安装电子部件的安装表面可以是平面的，或者非图案化的(而不是具有盲孔)。用片材的这样的平面或非图案化的安装表面，可以将电子部件自由地安装在安装表面的希望的表面区域处而不受任何限制。
在实施例中，所述方法包括使片材的至少部分与成型(profiled)结构连接，并且随后使用所连接的成型结构作为掩模对片材的至少部分进行结构化。优选地，该成型结构可以是引线框架结构(替代地，可以使用芯片框架作为掩模)。特别地，有可能将具有连续厚度的金属片材连接至已经被预制的成型结构，然后再将电子部件安装在这样的具有所附接的成型结构的片材上。于是，在从先前一体的片材-成型结构装置单个化成各个载体期间，有可能对复合的片材进行回蚀或机械研磨，以使得单个化的发生唯独是由成型结构的形状限定的。还有可能在对片材进行图案化之后连接单独的引线框架。
在实施例中，所述方法包括使片材的结构化的部分与成型结构连接。成型结构(特别是引线框架结构)上的距离与片材上的距离未必是等同的。因而，有可能在与成型结构的连接之前将片材划分成单独的预制件或部分。因而，可以使预制件与成型结构电连接，并且可以使用成型结构(特别是引线框架结构)作为掩模对预制件进行图案化。
在实施例中，所述方法包括对在图案化成单独的封装之后获得的结构进行单个化(例如，通过切割、蚀刻或激光处理)，所述单独的封装均包括载体之一、电子部件的至少其中之一、互连结构的至少其中之一和包封物的部分。特别地，所述方法可以包括通过去除包封物的材料而不去除片材的材料对该结构单个化。根据这样的有利实施例，仅通过去除包封物的相对较软的材料而发生分开，而单个化则不需要去除已经图案化的片材的金属材料。这使得将所获得的结构单个化成单独的封装的过程特别地简单并且具有故障鲁棒性。
在实施例中，片材具有处于30μm和3mm之间的范围内，特别处于200μm和500μm之间的范围内的厚度。因而，片材的厚度可以在很宽的范围内变化。其覆盖了(例如)铜箔(其可以任选地在制造工艺的部分期间与支撑板连接以提供额外的支撑)以及刚性铜板(对其而言不需要支撑板，并且因而支撑板完全可以是任选的)。
在实施例中，片材具有恒定的厚度。这样的片材可以具有两个平面的相对的主表面。为片材提供恒定的厚度允许使用非常简单并且廉价的原材料来制造封装，而不折损载体性能。
在另一实施例中，片材具有平面的第一主表面和相对的具有表面轮廓的第二主表面。在这样的实施例中，片材的表面轮廓可以已经限定了以后形成的载体的外形，因为可以简单地使用该表面轮廓作为掩模去除片材的材料。
在实施例中，互连结构选自由夹、接合线和接合带构成的组。夹可以是三维弯曲的板类型的连接元件，其具有将连接至相应的电子部件的上主表面和载体的上主表面的两个平面区段，其中，两个所提及的平面区段通过倾斜或垂直的连接区段互连。作为这样的夹的替代方案，有可能使用是柔性导电线状体或带状体的线接合部或带接合部，所述柔性导电线状体或带状体具有连接至相应的电子部件的上主表面的一个端部部分和电连接至载体的相对的另一个端部部分。
在实施例中，封装的至少两个相对的(特别是所有四个)横向最外侧壁或者横向最外侧壁部分唯独由包封物的材料形成。这是通过在对片材进行对应的图案化之后通过仅切穿包封物材料而将各个封装分开的结果。
在实施例中，所述至少一个电子部件在操作期间经历垂直电流流动。根据示例性实施例的封装架构特别适合高功率应用，在这样的应用中希望垂直电流流动，即，在垂直于电子部件的两个相对主表面的方向上的电流流动，所述两个相对主表面之一用于将该电子部件安装在片材上，并且另一个用于使电子部件与互连结构连接。
在实施例中，所述至少一个电子部件的基本上整个下主表面完全与载体接触，特别是完全与载体电接触。换言之，相应的电子部件的下主表面的整个面积可以完全与片材或载体的上主表面接触(特别是仅通过诸如焊料、粘合剂等的连接介质分开)。这允许电子部件与片材/载体之间的适当的机械或者乃至电耦合。
在实施例中，所述至少一个电子部件包括处于上主表面处的至少一个第一电端子，并且包括处于下主表面处的至少一个第二电端子。例如，所述电端子可以是芯片焊盘。在电子部件是晶体管芯片时，漏极端子可以被布置在下主表面处，并且源极端子和栅极端子可以被布置在上主表面处(或反之亦然)。
在实施例中，包封物包括模制部件或者由模制部件构成。在通过模制进行包封时，例如，可以执行注塑模制或者转移模制。因而，包封物可以包括模制物，特别是塑料模制物。例如，可以通过将一个或多个主体放置于上模制工具和下模制工具之间并向其中注入液态模制材料而提供相应地被包封的主体(特别是电子部件连同载体)。在模制材料凝固之后，完成了包封物的形成。如果希望，可以用改善模制物的特性(例如，其散热特性)的颗粒对模制物进行填充。也可以使用其他包封物材料。
在实施例中，通过由焊料结构、烧结结构或者熔接结构构成的组的至少其中之一将电子部件安装在安装区上。而且，还有可能以粘合方式将电子部件安装在安装区上。
在实施例中，所述至少一个电子部件包括由控制器电路、驱动器电路和功率半导体电路构成的组的至少其中之一。所有这些电路都可以被集成到一个半导体芯片中，或者可以被单独集成到不同的芯片中。例如，对应的功率半导体应用可以通过芯片实现，其中，这样的功率半导体芯片的集成电路元件可以包括至少一个晶体管(特别是MOSFET，金属氧化物半导体场效应晶体管)、至少一个二极管等。特别地，可以制造履行半桥功能、全桥功能等的电路。
作为用于半导体芯片的衬底或晶圆，可以使用半导体衬底，即硅衬底。或者，可以提供氧化硅或者其他绝缘体衬底。还有可能实施锗衬底或者III-V族半导体材料。例如，示例性实施例可以是通过GaN或SiC技术实施的。
本发明的上述和其他目的、特征和优点将从下文联系附图的说明书和所附权利要求中变得显而易见，其中，类似的部分或要素通过类似的附图标记表示。
附图说明
被包括以提供对本发明的示例性实施例的进一步理解并且构成了说明书的部分的附图示出了本发明的示例性实施例。
在附图中：
图1示出了根据示例性实施例的制造封装的方法的框图。
图2示出了根据另一个示例性实施例的制造封装的方法的框图。
图3到图13示出了根据另一个示例性实施例的在执行制造封装的方法期间获得的结构。
图14和图15示出了由根据示例性实施例的方法制造的封装的不同视图。
图16和图17示出了由根据另一个示例性实施例的方法制造的封装的不同视图。
图18和图19示出了由根据又一个示例性实施例的方法制造的封装的不同视图。
图20到图23示出了由根据示例性实施例的方法制造的封装的不同视图。
图24到图26示出了根据另一个示例性实施例的在执行制造封装的方法期间获得的结构。
具体实施方式
附图中的图示只是示意性的并且不是按比例的。
在参考附图更加详细地描述示例性实施例之前，将对示例性实施例的开发所基于的一些一般考虑事项加以总结。
根据示例性实施例，可以执行面板封装，其开始于作为引线框架的非结构化预制件的至少基本上连续并且特别是完全连续的片材。仅在将电子部件安装在连续的片材上之后并且在形成互连结构之后和/或在从正面进行包封之后，可以从背面(即，从与电子部件相对的一侧)对片材进行结构化，由此基于片材形成用于各个封装的单独的载体。
由于大的衬底尺寸与并行处理相结合，因而面板级上的封装允许获得低的封装工作量。而且，面板线的容量可以非常高。为了填充该线，可能希望针对多个封装预制件的封装流程具有高灵活性。
示例性实施例提供了一种实现灵活的基于面板的封装的制造架构。更具体而言，示例性实施例以非结构化片材(例如，由铜制成)开始封装(特别是无引线功率封装或逻辑封装)的制造。这样的片材的厚度可以优选地处于200μm和500μm之间的范围内，但是也可以更大或更小。有利地，也可以在非结构化片材上提供电子部件(特别是管芯附接，例如，通过焊料、粘合剂、烧结膏、扩散焊料等)和/或第一级互连(例如，细接合线、粗接合线和/或夹)的组装。然后，对所获得的具有多个仍然一体连接的封装的预制件进行包封(例如，模制，例如，通过压缩模制)。然后，在施加第一级互连和/或包封或壳(例如，通过模制)之后可以完成对连续的片材的结构化。例如，可以通过蚀刻或者以机械方式(例如，通过研磨和/或铣削)完成对这样的连续的片材的结构化或图案化。
有利地，通过在制造工艺的显著部分之上在面板幅面上处理封装，这样的制造原理使得能够以低工作量实现多个封装的制造。此外，根据示例性实施例的这样的制造工艺不需要定制的引线框架，因为起始点可以是全部导电的片材，例如，铜片材。而且，在一些实施例中，预封装架构也是可能的。所获得的封装可以表现出高稳定性，因为对于SMD(表面安装器件)型附接而言，片材的导电材料(例如，铜)可以从包封物(例如，模制主体)延伸出来。此外，将面板划分成各个封装的快速划片或单个化工艺是可能的，因为只有包封物材料(例如，模制化合物)必须被分开，而对穿过金属片材材料(特别是铜)进行切割或划片则可以是不必要的。例如，对于高功率应用而言，一些实施例还可以与经历垂直电流流动的电子部件兼容。此外，电子部件(特别是电子芯片，例如，裸管芯)与载体(特别是引线框架)的全部面积连接可以是可能的，其可以提供优良的热传导性。而且，用或者不用再分布层形成外围引线都是可能的。
在示例性实施例的制造方法中，可以选择连续的片材(其可以是铜箔或者铜板)的厚度。仅在随后才通过(例如)去除不需要或不希望的铜以减法方式对片材进行结构化。用于结构化的掩模可以是抗蚀剂。
非结构化或者连续的片材可以被分成部分，并且这些部分可以通过(例如)熔接、焊接、胶黏、扩散焊接(特别是用预封装技术)附接至经冲压的引线框架或者其他成型结构。在预封装的附接之后，可以用充当掩模的引线框架或其他成型结构对片材进行蚀刻。通过这种方式，也可以实现非常厚的引线框架封装。可以对具有铜结构的底侧进行包覆印刷或镀覆，从而将所述铜端子嵌入，以实现更好的粘合。而且可以使用焊接停止部。
例如，如果从片材的顶侧对片材进行结构化，那么可以预见铜的锚定结构。例如，可以通过用(一个或多个)管芯底座和引线的半蚀刻(特别是在片材顶侧)对片材进行结构化。可以附接管芯或其他种类的电子部件，并且可以提供第一级互连。在包封(特别是模制)之后，可以对面板的底侧进行研磨，以释放管芯底座和引线的分开。现在这些完全嵌入在模制化合物中。
图1示出了根据示例性实施例的制造封装100的方法的框图。如框200所指示的，所述方法包括提供导电的、连续的片材102。而后，如框210所示，所述方法还包括将多个电子部件104安装在片材102上。随后，形成用于使电子部件104与片材102电耦合的互连结构106(比较框220)。在所述形成之后，对片材102进行结构化，如框230所示。
图2示出了根据另一个示例性实施例的制造封装100的方法的框图。参考框250，所述方法包括提供导电的、连续的片材102。如框260所示，所述方法包括将多个电子部件104安装在片材102上。而后，通过包封物108至少部分地包封电子部件104，比较框270。在包封之后，对片材102进行图案化，由此形成每一封装100的各个载体110(参见框280)。
图3到图13示出了根据另一个示例性实施例的在执行制造封装100的方法期间获得的结构。所述附图示出了可以用作为不同实施例的三种互连选项执行的示例性工艺流程，所述三种互连选项即为三种不同的形成互连结构106的可能性。如果希望，可以将这些选项予以结合。所提及的实施例涉及互连结构106，其被体现为具有细栅极线(其可以用于(例如)功率封装)的粗线、具有夹(夹框架)的封装100或者夹和用于栅极接触部的一个细线接合部(也适用于功率封装)或多条细线(例如，用于VQFN或逻辑封装)。在图3到图13中的一些附图中，示出了不同视图(例如，如图3中的平面图和三维图或者如图7中的概览图和细节图)。
参考图3，示出了在安装电子部件104之前可以暂时连接至下述片材102并且可以在对片材102进行图案化之前从经处理的片材102去除的支撑板116。例如，支撑板116可以由钢、聚合物、合金、铝或银制成。也有可能支撑板116在处理的开始就已经与片材102连接在一起。为了简化操纵，还可以为支撑板116提供柄部(未示出)。在使用之后，可以对支撑板116循环利用，以进行下一批量制造，或者可以将其废弃。图3所示的临时的支撑板116可以被塑形为板状，例如，矩形板，例如，其具有620x620mm2的尺寸。
参考图4，其示出了将安装在任选的支撑板116上的导电的、连续的片材102。替代地，也可以在未附接至支撑板116的情况下如下文所述对片材102进行进一步处理。
如图4中用虚线示意性所示，片材102的中央部分(该中央部分可以对应于(例如)片材102的上主表面的面积的至少90％)用作安装区103，然后将在安装区103上安装电子部件104(比较图6)。至少所述安装区103是连续的，没有通孔。尽管未示出，但是片材102的处于安装区103外的外围部分可以包括用于对准片材102的一个或多个对准特征和/或用于操纵片材102的一个或多个操纵特征。
优选地，可以为片材102提供恒定的厚度d，厚度d处于200μm和500μm的范围内。然而，更一般地，片材102可以配置有100μm、200μm、250μm、1mm或2.54mm的厚度d。例如，片材102可以包括铜或者由铜构成。为了简化操纵，片材102的尺寸可以略微小于临时的支撑板116的尺寸，例如，片材102的尺寸可以是610x610mm2。
从图5可以看出，铜片材102被放置于临时的支撑板116上，从而获得提供强机械支撑的临时复合结构。
参考图6，可以任选地在片材102中形成盲孔118，以限定用于电子部件104的容纳体积。随后，可以将电子部件104安装在盲孔118中。然而，替代地，也有可能将电子部件104直接安装在安装区103中的片材102的平面表面上，即，不提供盲孔118。例如，可以通过焊接、烧结、粘附(优选地用导电粘合剂)或者熔接完成安装。
在所示的实施例中，电子部件104是作为集成电路的具有MOSFET(金属氧化物半导体场效应晶体管)的功率半导体芯片。在操作期间，电子部件104可以经历垂直电流流动，即，沿基本上垂直于片材102的安装电子部件104的主表面的方向的电流流动。这样的电子部件104可以在两个相对主表面上，即在底部主表面(电子部件104在其上与片材102连接)上和在背离片材102的顶部主表面上都具有焊盘或端子。例如，可以在相应的电子部件104的基本上整个下主表面上形成漏极焊盘，并且可以在相应的电子部件104的上主表面上形成栅极焊盘和源极焊盘。鉴于漏极焊盘的大面积，电子部件104的整个下主表面基本上完全与片材102导电接触。
在将电子部件104安装在片材102上之后，可以连接互连结构106，从而在电子部件104的上主表面上的焊盘与片材102的上主表面(该上主表面承载电子部件104)之间建立电耦合。换言之，导电的互连结构106使电子部件104的上主表面与片材102(电子部件104的下主表面安装于其上)电连接。根据图6，互连结构106被配置为接合线。
因而，从图6可以看出，通过适当的管芯附接方法(例如，焊接、胶黏、烧结或扩散焊接)将一个或多个管芯作为电子部件104附接到铜片材102中的盲孔118。可以自由选择相邻的电子部件104之间的距离。在管芯附接之后，可以对电子部件104进行线接合，其中，可以在铜片材102上的可自由定义的位置处连接所述线。替代地，可以执行夹附接。线接合部可以由具有不同粗细的金线、铝线或铜线制成。例如，所述管芯放置指标可以为4.2mmx4.2mm。
图7示出了形成用于使电子部件104与片材102电耦合的互连结构106的替代方式。根据图7，互连结构106中的一些被配置为比图6中的接合线或接合带更粗的接合线或接合带。更确切地来讲，根据图7，可以使用粗线作为功率应用的互连结构106，并且可以将作为其他互连结构106的细线用于栅极接合部。可以将线连接部自由地接合到铜片材102上的自由选择位置上。
图8示出了用于互连结构106的附接的第三种可能实施例，现在互连结构106被体现为夹。在这一实施例中，可以将电子部件104放置到焊料中，可以将焊膏施加到电子部件104上，并且可以通过回流焊接附接并连接作为互连结构106的夹或夹框架。图8示出了具有20.5mmx13.5mm的放置指标的夹框架。其指示了具有作为互连结构106的夹的单个狭槽。还提供了一个用于栅极接触部的线接合部作为另一互连结构106。
参考图9，电子部件104和互连结构106可以部分或完全被包封物108(例如，通过模制形成的模制化合物)包封。包封物108还覆盖片材102的上主表面上的仍然暴露的表面部分。在使模制化合物固化之后，可以去除临时的支撑板116，因为不再需要该临时的支撑板116来取得结构稳定性。
因而，所附接的电子部件104和互连结构106可以嵌入到铜片材102上的作为包封物108的模制化合物中。例如，可以从正面通过包覆模制或者包覆印刷执行包封物106的形成。例如，压缩模制可以用于这一目的。
在包封之前，可以执行粘合促进工艺(如果希望或需要的话，其用于提高模制化合物型包封物108与电子部件104和/或片材102的材料的粘合性)。
参考图10，然后，可以从与所述正面相对的背面对片材102进行结构化或图案化。对片材102的结构化可以是在包封之后并且在去除临时的支撑板116之后完成的，由此形成每一封装100的各个载体110。因而，通过对先前连续的片材102进行图案化而获得了载体110。在图10的实施例中，将片材102结构化成引线框架结构121，以使得载体110中的每者在所示的实施例中包括中央管芯焊盘112以及沿周边围绕管芯焊盘112的多条引线114。通过在先前从正面用包封物108包封之后从背面进行该图案化或结构化，可以因而为每一封装100建立各个引线框架型载体110。换言之，对片材102进行结构化基于先前连续的片材102形成了引线框架结构121。
因而，如图10中所示，可以从临时的支撑板116去除模制后的铜片材102。可以在与正面主表面相对的背面主表面上对片材102进行减法结构化，在正面主表面上已经安装了电子部件104，已经连接了互连结构106，并且已经形成了包封物108。对于图案化而言，可以施加抗蚀剂，可以执行光刻过程(用于打开将在蚀刻工艺中去除的铜的区域)，并且可以在期望没有铜的位置上将铜片材102蚀刻掉。通过这种方式可以建立相应的无引线封装的管芯底座或管芯焊盘112和引线114。
由于仅在包封之后对先前连续的片材102进行图案化或结构化，因而所获得的载体110的子结构可以具有位于其间的未被包封物108填充而是填充有空气的小的缝隙(参见图14到图23和图26)。
参考图11，在将片材102结构化成单独的载体110时，可以实现不同的铜结构(比较图10)。可以依据铜片材102的厚度d选择所施加的设计规则(从而获得希望的纵横比)。根据图11，获得了具有与图10中不同的构造的各个载体110。
图12示出了用于对铜片材102进行结构化以生成所获得的载体110的焊盘引出几何结构的另一个实施例。因而，根据图12，获得了具有与图10和图11中均不同的又一构造的各个载体110。
随后，可以施加焊盘精整等的其他工艺，例如，电镀、无电镀、阻焊剂施加、焊料凸点施加或焊料球施加。
参考图13，在将片材102结构化成单独的载体110之后获得的结构(如图10到图12所示)可以被分成或者单个化成单独的封装100。例如，这可以通过切割锯片160、通过蚀刻或者通过激光处理来完成。每一分开的封装100包括载体110之一、电子部件104中的一者或多者、互连结构106中的一者或多者以及包封物108的部分。
有利地，可以唯独通过去除包封物108的材料而不去除现在已经图案化的片材102的材料或者互连结构106的材料来执行对所述结构进行单个化的工艺。这样做是有利的，因为其允许仅仅切穿可切割材料(例如，模制化合物)而不切穿金属材料(例如，铜)。因此，所获得的封装100的最外侧壁可以唯独由包封物108的材料形成(参见图14到图23以及图26)。
例如，可以通过激光、水切割、铣削、冲压或者硅锯片切块分开工艺来完成将所述结构分成各个封装100的操作。
参考图14到图23，示出了根据示例性实施例的封装100。这些封装100可以是通过作为上文参考图3到图13描述的制造工艺的制造工艺获得的。
图14和图15示出了通过这样的方法制造的封装100的不同视图。
所示出的封装100包括引线框架型载体110，引线框架型载体110是通过上文描述的对片材102进行图案化而获得的，并且被结构化成通过相应的空气缝隙142隔开的多个子结构140。换言之，缝隙142可以填充有空气。获得了没有固态材料、特别是没有包封物材料的空气缝隙142，因为上文描述的将片材102图案化或结构化成单独的载体110从而形成缝隙142的操作是在形成包封物108之后执行的。
一个或多个电子部件104(例如，具有垂直电流流动的功率半导体芯片)可以以下主表面安装在载体110上。一个或多个互连结构106(这里被体现为夹)使电子部件104的上主表面与载体110的上主表面电连接。因而，包封物108包封电子部件104、互连结构106和载体110。载体110的背面主表面以及子结构114之间的缝隙142保持不被包封，并且暴露于封装100的环境。如图14和图15中进一步所示，封装100的相对的横向最外侧壁部分144可以唯独由包封物108的材料形成，而不由铜材料形成。
图14中所示的封装100具有4.1x4.1x0.7mm3的尺寸。图15提供了具有0.1mm的厚度d的引线框架的示例。
图16和图17示出了由根据另一个示例性实施例的方法制造的封装100的不同视图。在图16的实施例中，尺寸为8x8x1.2mm3。在图17的示例中，引线框架厚度d可以为0.2mm。
图18和图19示出了由根据示例性实施例的方法制造的封装100的不同视图。在图18的实施例中，封装100具有20x13x3.5mm3的尺寸。在图19的示例中，引线框架厚度d可以为1mm。
图20、图21、图22和图23示出了由根据示例性实施例的方法制造的封装100的不同视图。封装100的尺寸可以为20x13x2.9mm3。在图20中暴露了封装100的内部的部分。图23中的引线框架厚度可以为1mm。
图24到图26示出了根据另一个示例性实施例的在执行制造封装100的方法期间获得的结构。图24到图26中所示的结构是在多个封装100的批量制造期间同时获得的，并且以相同的连续的片材102、包封物108等为基础。为了简单起见，图24到图26仅示出了一个封装100的构成部分。通过虚线指示了其他封装100及其预制件的存在。
参考图24，其示出了半成品，该半成品包括导电的、连续的片材102(例如，连续的铜板)、被配置为经历垂直电流流动的功率半导体芯片的电子部件104、接合线型互连结构106和模制型包封物108。此外，还示出了单独的成型结构120(例如，引线框架结构，例如，在图10中以附图标记121示出的引线框架结构，例如，其由铜制成)。更具体而言，晶体管芯片型电子部件104包括处于上主表面处的两个第一电端子146(特别是源极焊盘和栅极焊盘)，并且包括处于下主表面处的第二电端子148(特别是漏极端子)。
如图所示，成型结构120仍然与由电子部件104、片材102、互连结构106和包封物108构成的一体主体分开。
参考图25，包括片材102的该一体主体与先前分开的成型结构120连接，从而形成一个公共的一体结构。更具体而言，片材102的未被包封物108覆盖的暴露的表面与成型结构120的对应的主表面连接。因而，可以将成型结构120连接至片材102的下主表面(例如，通过焊接)，从而形成一体结构。如图25所示，由片材102和成型结构120构成的连接的双层具有在其上安装电子部件104的上部的平面的第一主表面，并且具有带有表面轮廓的下部的相对的第二主表面。所述表面轮廓对应于成型结构120的预结构化的形状。
在获得了所述一体结构之后，可以一起对由片材102和成型结构120构成的复合双层进行图案化或结构化。在这一图案化或结构化过程期间，预成形的成型结构120用作掩模，以限定片材102的将在图案化或结构化过程期间被去除的部分。片材102的被预成形的成型结构120覆盖的部分在这一图案化或结构化过程期间将不被去除，而片材102的暴露部分以及成型结构120的暴露部分将被去除。例如，可以通过蚀刻执行这一图案化或结构化，如附图标记150示意性所示。
参考图26，由于所述蚀刻的结果，已经去除了片材102和成型结构120的暴露的材料，从而使得获得了载体110，载体110具有成型结构120的形状，并且至少部分地由片材102的材料制成。
可以沿分开线154将图26的所示结构分成单独的封装100。
应当指出，术语“包括”不排除其他元件或特征，并且不定冠词“一”不排除复数。也可以使联系不同实施例描述的元件相结合。还应当指出，附图标记不应被理解为限制权利要求的范围。此外，无意使本申请的范围局限于说明书中描述的工艺、机器、制造、物质成分、手段、方法和步骤的特定实施例。相应地，所附权利要求意在将这种工艺、机器、制造、物质成分、手段、方法或步骤包括到其范围内。

Claims (20)

1.一种制造封装(100)的方法，其中，所述方法包括：
提供至少在安装区(103)中连续的导电的片材(102)；
将多个电子部件(104)的第一主表面安装在所述片材(102)的所述连续的安装区(103)上；
形成用于使所述电子部件(104)的第二主表面与所述片材(102)电耦合的互连结构(106)，其中，所述第二主表面与所述第一主表面相对；以及
在所述形成之后，对所述片材(102)进行结构化。
2.根据权利要求1所述的方法，其中，所述方法包括在所述结构化之前，通过包封物(108)至少部分地包封所述电子部件(104)和所述互连结构(106)。
3.根据权利要求1或2所述的方法，其中，所述方法包括对所述片材(102)进行结构化，由此形成用于每一封装(100)的各个载体(110)。
4.根据权利要求3所述的方法，其中，所述方法包括将在对所述片材(102)进行结构化之后获得的结构分成单独的封装(100)，所述单独的封装(100)均至少包括所述载体(110)之一、所述电子部件(104)的至少其中之一以及所述互连结构(106)的至少其中之一。
5.根据权利要求1到4中的任何一项所述的方法，其中，所述方法包括对所述片材(102)进行结构化，由此形成引线框架结构(121)。
6.根据权利要求1到5中的任何一项所述的方法，其中，所述方法包括在所述片材(102)中形成盲孔(118)，以及随后将所述电子部件(104)安装在所述盲孔(118)中。
7.根据权利要求1到6中的任何一项所述的方法，其中，所述方法包括使所述片材(102)的至少部分与成型结构(120)连接，以及随后使用所述成型结构(120)作为掩模对所述片材(102)的至少部分进行结构化。
8.根据权利要求1到7中的任何一项所述的方法，其中，所述片材(102)具有处于30μm和3mm之间的范围内的厚度，特别是具有处于200μm和500μm之间的范围内的厚度。
9.一种制造封装(100)的方法，其中，所述方法包括：
提供导电的基本连续的片材(102)；
将在操作期间具有垂直电流流动的多个电子部件(104)安装在所述片材(102)上；
通过包封物(108)至少部分地包封所述电子部件(104)；
在所述包封之后，从所述片材(102)的未包封的背面对所述片材(102)进行图案化，由此形成用于每一封装(100)的各个载体(110)。
10.根据权利要求9所述的方法，其中，所述方法包括在图案化之前，并且特别是在至少部分地包封所述电子部件(104)之前，形成用于使所述电子部件(104)的上主表面与所述片材(102)电耦合的互连结构(106)，所述电子部件(104)的下主表面安装于所述片材(102)上。
11.根据权利要求9或10所述的方法，其中，所述方法包括将在对所述片材(102)进行图案化之后获得的结构单个化成单独的封装(100)，所述单独的封装(100)均至少包括所述载体(110)之一、所述电子部件(104)的至少其中之一以及所述包封物(108)的部分。
12.根据权利要求11所述的方法，其中，所述方法包括通过去除所述包封物(108)的材料而不去除所述片材(102)的材料来对所述结构进行单个化。
13.一种封装(100)，包括：
载体(110)，所述载体(110)被结构化成通过至少一个缝隙(142)隔开的多个子结构(140)；
至少一个电子部件(104)，所述至少一个电子部件(104)以其下主表面安装在所述载体(110)上；
至少一个互连结构(106)，所述至少一个互连结构(106)使所述至少一个电子部件(104)的上主表面与所述载体(110)电耦合；以及
包封物(108)，所述包封物(108)以使得所述至少一个缝隙(142)不被包封的方式至少部分地包封所述至少一个电子部件(104)并且部分地包封所述载体(110)。
14.根据权利要求13所述的封装(100)，其中，所述封装(100)的至少两个相对的、特别是所有的横向最外的侧壁部分(144)唯独由所述包封物(108)的材料形成。
15.根据权利要求13或14所述的封装(100)，其中，所述至少一个电子部件(102)在操作期间经历垂直电流流动。
16.根据权利要求13到15中的任何一项所述的封装(100)，其中，所述至少一个电子部件(102)的基本上整个下主表面完全与所述载体(110)接触，特别是完全与所述载体(110)导电接触。
17.根据权利要求13到16中的任何一项所述的封装(100)，其中，所述至少一个电子部件(102)包括处于所述上主表面处的至少一个第一电端子(146)，并且包括处于所述下主表面处的至少一个第二电端子(148)。
18.根据权利要求13到17中的任何一项所述的封装(100)，其中，所述至少一个互连结构(106)选自由夹、接合线和接合带构成的组。
19.根据权利要求13到18中的任何一项所述的封装(100)，其中，所述至少一个电子部件(104)包括由特别是功率半导体芯片的半导体芯片、有源电子器件、无源电子器件、传感器、致动器和微机电系统所构成的组的至少其中之一。
20.根据权利要求13到19中的任何一项所述的封装(100)，其中，所述至少一个缝隙(142)填充有空气。
CN202010406422.4A 2019-05-15 2020-05-14 通过在安装电子部件之后将片材分成载体而进行的封装的批量制造 Pending CN111952191A (zh)

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