CN112802888A - 半导体功率器件终端结构 - Google Patents

半导体功率器件终端结构 Download PDF

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CN112802888A
CN112802888A CN201911030369.6A CN201911030369A CN112802888A CN 112802888 A CN112802888 A CN 112802888A CN 201911030369 A CN201911030369 A CN 201911030369A CN 112802888 A CN112802888 A CN 112802888A
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power device
semiconductor power
electrode
trench
doped region
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龚轶
刘磊
刘伟
王鑫
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Suzhou Dongwei Semiconductor Co ltd
Suzhou Oriental Semiconductor Co Ltd
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Suzhou Dongwei Semiconductor Co ltd
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Priority to US17/428,151 priority patent/US20220254875A1/en
Priority to PCT/CN2019/121675 priority patent/WO2021082159A1/zh
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Abstract

本发明实施例提供的一种半导体功率器件终端结构，包括：n型外延层以及位于所述n型外延层中的：至少一个沟槽，所述沟槽包括沟槽上部和沟槽下部两部分；位于所述沟槽上部中的第一电极以及至少位于所述沟槽下部中的第二电极，所述第二电极、所述第一电极、所述n型外延层两两之间由绝缘介质层隔离；与所述沟槽相邻的第一p型掺杂区。本发明实施例提高了半导体功率器件的耐压能力和稳定性。

Description

半导体功率器件终端结构
技术领域
本发明属于半导体功率器件技术领域，特别是涉及一种半导体功率器件终端结构。
背景技术
现代高压半导体器件IGBT、VDMOS等作为第三代电力电子产品，由于其工作频率高、开关速度快、控制效率高而在电力电子领域得到越来越广泛的应用，尤其在汽车电子、消费电子、开关电源盒工业控制中得到广泛应用(例如继电器、节能灯电子镇流器、电机变频调速、高频加热、马达驱动、家用电器音响装置、开关稳压电源等)。现代高压功率半导体器件的阻断能力是衡量发展水平的一个非常重要的标志，依据应用，击穿电压的范围可从25V到6500V，但是由于现代半导体工艺采用平面型终端结构，结深较浅，结边缘弯曲使得耐压降低、耐压稳定性差、器件的安全工作区较小，器件容易破坏。因此，为了提高和稳定器件的耐压特性，除了器件体内各参数的配合外，更重要的是对表面终止的pn结进行适当的处理，以改善器件边缘的电场分布，减弱表面电场集中，提高器件的耐压能力和稳定性。
发明内容
有鉴于此，本发明的目的是提供一种半导体功率器件终端结构，以提高半导体功率器件的耐压能力和稳定性。
本发明实施例提供的一种半导体功率器件终端结构，包括：
n型外延层以及位于所述n型外延层中的：
至少一个沟槽，所述沟槽包括沟槽上部和沟槽下部两部分；
位于所述沟槽上部中的第一电极以及至少位于所述沟槽下部中的第二电极，所述第二电极、所述第一电极、所述n型外延层两两之间由绝缘介质层隔离；
与所述沟槽相邻的第一p型掺杂区。
可选的，本发明所述第一p型掺杂区外接源极电压。
可选的，本发明所述第一p型掺杂区的深度大于所述沟槽的深度，所述第一p型掺杂区覆盖包围所有或者部分所述沟槽。
可选的，本发明所述第二电极与所述n型外延层之间的所述绝缘介质层的厚度，大于或等于所述第一电极与所述n型外延层之间的所述绝缘介质层的厚度。
可选的，本发明还包括位于所述第一p型掺杂区中的第二p型掺杂区，所述第二p型掺杂区的掺杂浓度大于所述第一p型掺杂区的掺杂浓度。
可选的，本发明所述沟槽上部的宽度大于所述沟槽下部的宽度。
可选的，本发明所述第二电极向上延伸至所述沟槽上部中。
可选的，本发明所述第二电极在所述沟槽上部内将所述第一电极分割为两部分。
可选的，本发明还包括覆盖所述沟槽的绝缘层以及覆盖所述绝缘层的金属层。
可选的，本发明所述金属层外接源极电压。
本发明实施例的一种半导体功率器件终端结构，可以调节沟槽附近的纵向电场分布，降低沟槽底部(即沟槽下部的底部位置处)的电场，提高半导体功率器件的耐压。同时，第二电极与n型外延层之间的厚氧化层电容可以固定半导体功率器件终端中的可动电荷，提高半导体功率器件的可靠性。
附图说明
为了更加清楚地说明本发明示例性实施例的技术方案，下面对描述实施例中所需要用到的附图做一简单介绍。显然，所介绍的附图只是本发明所要描述的一部分实施例的附图，而不是全部的附图，对于本领域普通技术人员，在不付出创造性劳动的前提下，还可以根据这些附图得到其他的附图。
图1是本发明提供的一种半导体功率器件终端结构的第一个实施例的剖面结构示意图；
图2是本发明提供的一种半导体功率器件终端结构的第二个实施例的剖面结构示意图；
图3是本发明提供的一种半导体功率器件终端结构的第三个实施例的剖面结构示意图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，以下将结合本发明实施例中的附图，通过具体方式，完整地描述本发明的技术方案。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。
应当理解，本发明所使用的诸如“具有”、“包含”以及“包括”等术语并不配出一个或多个其它元件或其组合的存在或添加。同时，为清楚地说明本发明的具体实施方式，说明书附图中所列图形大小并不代表实际尺寸，说明书附图是示意性的，不应限定本发明的范围。说明书中所列实施例不应仅限于说明书附图中所示区域的特定形状，而是包括所得到的形状如制备引起的偏差等。
图1是本发明提供的一种半导体功率器件终端结构的第一个实施例的剖面结构示意图，如图1所示，本发明实施例提供的一种半导体功率器件终端结构，包括n型外延层20，以及位于n型外延层20中的至少一个沟槽40，图1中示例性的示出了4个沟槽40，沟槽40包括沟槽上部41和沟槽下部42，在图1所示的一种半导体功率器件终端结构中沟槽40的沟槽上部41的宽度大于沟槽下部42的宽度。
位于沟槽上部41中的第一电极23以及至少位于沟槽下部42中的第二电极22，第二电极22、第一电极23、n型外延层20两两之间由绝缘介质层24隔离，绝缘介质层24的材质通常为氧化硅，第一电极23和第二电极22的材质通常为多晶硅。基于半导体功率器件的制造工艺的选择，第二电极22与n型外延层20之间的绝缘介质层24的厚度，大于或等于第一电极23与n型外延层20之间的绝缘介质层24的厚度。示例性的，当绝缘介质层24为氧化硅等氧化层时，第二电极22与n型外延层20之间的氧化层的厚度可以大于或等于第一电极23与n型外延层20之间的氧化层的厚度。可选的，第二电极22可以向上延伸至沟槽上部41中，第二电极22向上延伸至沟槽上部41中时，第一电极22可以在沟槽上部41内仍为连接的一部分，第一电极22也可以在沟槽上部41内被第二电极23分割为两部分(如图1所示)。
与沟槽40相邻的第一p型掺杂区21，第一p型掺杂区21的深度大于沟槽40的深度，此时，第一p型掺杂区21可以覆盖包围沟槽40。可选的，第一p型掺杂区21的深度也可以等于或者小于沟槽40的深度(图2是本发明提供的一种半导体功率器件终端结构的第二个实施例的剖面结构示意图，在该实施例中，第一p型掺杂区21的深度小于沟槽40的深度)。
位于第一p型掺杂区21中的第二p型掺杂区25，第二p型掺杂区25的掺杂浓度大于第一p型掺杂区21的掺杂浓度。第二p型掺杂区25通过金属层27外接源极电压。第一p型掺杂区21中也可以不形成第二p型掺杂区25，此时第一p型掺杂区21可以直接通过金属层27外接源极电压。基于半导体功率器件制造工艺的选择，在第二p型掺杂区25中还可以形成有n型掺杂区，在本发明实施例中不在具体展示。
本发明提供的一种半导体功率器件终端结构还可以包括覆盖沟槽40的绝缘层26以及覆盖绝缘层26的金属层27，金属层27外接源极电压。在图1所示的本发明提供的一种半导体功率器件终端结构中，金属层27和绝缘层26同时覆盖了沟槽40和n型外延层20，可选的，绝缘层和金属层可以仅覆盖沟槽40部分，此时金属层可以外接源极电压，也可以浮空不接源极电压。
图3是本发明提供的一种半导体功率器件终端结构的第三个实施例的剖面结构示意图，如图3所示，本发明实施例的一种半导体功率器件终端结构中包含4个沟槽40，第一p型掺杂区21的深度大于沟槽40的深度，此时，第一p型掺杂区21仅覆盖了部分沟槽40。
本发明实施例的一种半导体功率器件终端结构，可以调节沟槽附近的纵向电场分布，使得第一p型掺杂区中的电场分布集中在沟槽上部的底部位置处和沟槽下部的底部位置处，从而可以降低沟槽底部(即沟槽下部的底部位置处)的电场，提高半导体功率器件的耐压，特别是当沟槽全部被第一p型掺杂区覆盖包围时，可以进一步优化第一p型掺杂区内的电场分布。同时，当第二电极与n型外延层之间采用厚的氧化层时，厚的氧化层电容可以固定半导体功率器件终端中的可动电荷，提高半导体功率器件的可靠性；而第一电极与n型外延层之间的薄的氧化层可以缓解半导体功率器件的终端与有源区之间由于沟槽造成的n型外延层表面应力不平衡的问题。
以上具体实施方式及实施例是对本发明提出的一种半导体功率器件终端结构技术思想的具体支持，不能以此限定本发明的保护范围，凡是按照本发明提出的技术思想，在本技术方案基础上所做的任何等同变化或等效的改动，均仍属于本发明技术方案保护的范围。
尽管本发明的实施方案已公开如上，但其并不仅仅限于说明书和实施方式中所列运用，它完全可以被适用于各种适合本发明的领域，对于熟悉本领域的人员而言，可容易地实现另外的修改，因此在不背离权利要求及等同范围所限定的一般概念下，本发明并不限于特定的细节和这里示出与描述的图例。

Claims (10)

1.一种半导体功率器件终端结构，其特征在于，包括：
n型外延层以及位于所述n型外延层中的：
至少一个沟槽，所述沟槽包括沟槽上部和沟槽下部两部分；
位于所述沟槽上部中的第一电极以及至少位于所述沟槽下部中的第二电极，所述第二电极、所述第一电极、所述n型外延层两两之间由绝缘介质层隔离；
与所述沟槽相邻的第一p型掺杂区。
2.如权利要求1所述的一种半导体功率器件终端结构，其特征在于，所述第一p型掺杂区外接源极电压。
3.如权利要求1所述的一种半导体功率器件终端结构，其特征在于，所述第一p型掺杂区的深度大于所述沟槽的深度，所述第一p型掺杂区覆盖包围所有或者部分所述沟槽。
4.如权利要求1所述的一种半导体功率器件终端结构，其特征在于，所述第二电极与所述n型外延层之间的所述绝缘介质层的厚度，大于或等于所述第一电极与所述n型外延层之间的所述绝缘介质层的厚度。
5.如权利要求1所述的一种半导体功率器件终端结构，其特征在于，还包括位于所述第一p型掺杂区中的第二p型掺杂区，所述第二p型掺杂区的掺杂浓度大于所述第一p型掺杂区的掺杂浓度。
6.如权利要求1所述的一种半导体功率器件终端结构，其特征在于，所述沟槽上部的宽度大于所述沟槽下部的宽度。
7.如权利要求1所述的一种半导体功率器件终端结构，其特征在于，所述第二电极向上延伸至所述沟槽上部中。
8.如权利要求7所述的一种半导体功率器件终端结构，其特征在于，所述第二电极在所述沟槽上部内将所述第一电极分割为两部分。
9.如权利要求1所述的一种半导体功率器件终端结构，其特征在于，还包括覆盖所述沟槽的绝缘层以及覆盖所述绝缘层的金属层。
10.如权利要求9所述的一种半导体功率器件终端结构，其特征在于，所述金属层外接源极电压。
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