CN103681797A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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CN103681797A
CN103681797A CN201310073821.3A CN201310073821A CN103681797A CN 103681797 A CN103681797 A CN 103681797A CN 201310073821 A CN201310073821 A CN 201310073821A CN 103681797 A CN103681797 A CN 103681797A
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raceway groove
semiconductor device
semiconductor substrate
layer
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泉泽优
小野昇太郎
大田浩史
山下浩明
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Toshiba Corp
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Abstract

本发明提供一种半导体装置及其制造方法。半导体装置具有形成半导体元件的元件区域以及包围元件区域的终端区域。半导体装置具有半导体基板、沟道、绝缘层以及场板导电层。沟道在终端区域中以包围元件区域的方式形成于半导体基板。场板导电层隔着绝缘层形成于沟道。

Description

半导体装置及其制造方法
（相关申请的交叉引用）
本申请基于2012年9月19日提交的在先的日本专利申请No.2012-206195并要求其为优先权，在此引入其全部内容作为参考。
技术领域
本实施方式涉及一种半导体装置及其制造方法。
背景技术
在包围形成半导体元件的元件区域的终端区域中，使用用于缓和电场集中来保持耐压的各种构造。作为其中之一，已知电阻性场板(RFE：Resistive Field Plate)构造。然而，以往的电阻性场板构造在其形状上有偏差，其尺寸大。
发明内容
本发明的实施方式提供一种缓和了终端区域的电场的集中的半导体装置及其制造方法。
一个方式所涉及的半导体装置具有形成半导体元件的元件区域以及包围元件区域的终端区域。半导体装置具有半导体基板、沟道、绝缘层以及场板导电层。沟道在终端区域中以包围元件区域的方式形成于半导体基板。场板导电层隔着绝缘层形成于沟道。
根据实施方式，能够提供一种缓和了终端区域的电场的集中的半导体装置及其制造方法。
附图说明
图1是表示实施方式所涉及的半导体装置的顶视图。
图2是图1的A-A’剖视图。
图3A～图3C是表示实施方式所涉及的终端区域20的制造工序的剖视图。
图4是表示比较例所涉及的半导体装置的剖视图。
具体实施方式
下面，参照图1和图2来说明实施方式所涉及的半导体装置。图1是表示实施方式所涉及的半导体装置的顶视图，图2是图1的A-A’剖视图。此外，图1仅示出后述的元件区域10、终端区域20、沟道(trench)T、绝缘层28以及场板导电层29，省略了其它结构。
如图1所示，实施方式所涉及的半导体装置包括：形成半导体元件(例如，纵向功率MOSFET)的元件区域10以及包围元件区域10并形成电阻性场板构造的终端区域20。此外，作为一例，设本实施方式中的元件区域10与终端区域20的边界是后述的位于最外端的p型基底层12的中心(图2)。
接着，详细说明元件区域10。如图2所示，元件区域10在n型半导体基板11内具有：形成为在X方向具有规定间距且沿Y方向(图2的纸面垂直方向)延伸的条纹状的p型基底层12、p+型接触层13以及n型源极扩散层14。n型半导体基板11作为MOSFET的漏极扩散区域发挥功能，p型基底层12作为MOSFET的沟道层（channel）发挥功能。p+型接触层13作为连接于MOSFET的源极扩散区域的接点发挥功能，n型源极扩散层14作为MOSFET的源极扩散区域发挥功能。此外，在本说明书中，“p+”表示杂质浓度高于“p”。
p型基底层12形成在n型半导体基板11的表面。p+型接触层13形成在p型基底层12的表面。n型源极扩散层14形成在p+型接触层13的表面。
如图2所示，元件区域10在n型半导体基板11之上隔着栅极绝缘膜15具有栅极电极16。栅极绝缘膜15作为MOSFET的栅极绝缘膜发挥功能，栅极电极16作为MOSFET的栅极电极发挥功能。栅极电极16形成为在X方向之上具有规定间距且沿Y方向延伸的条纹状。栅极电极16共同形成在相邻的两个p型基底层12。
如图2所示，元件区域10具有作为MOSFET的源极和漏极发挥功能的源极电极S和漏极电极D。源极电极S与p+型接触层13的上表面及n型源极扩散层14的上表面相接。漏极电极D与n型半导体基板11的背面相接。
接着，详细说明终端区域20。如图2所示，终端区域20在与元件区域10的边界附近具有栅极绝缘膜21和栅极电极22。这些栅极绝缘膜21和栅极电极22具有与元件区域10的栅极绝缘膜15及栅极电极16相同的形状。
如图2所示，终端区域20在栅极电极22的更外周侧具有p型保护环层23、p+型保护环层24、p-型保护环层25。此外，在本说明书中，“p-”表示杂质浓度低于“p”。
p型保护环层23形成在n型半导体基板11的表面。p+型保护环层24形成在p型保护环层23的表面。p-型保护环层25形成在n型半导体基板11的表面，与p型保护环层23及p+型保护环层24相邻。p+型保护环层24与源极电极S电连接。这些保护环层23～25形成为包围元件区域10的环状，缓和电场集中。
如图2所示，终端区域20在n型半导体基板11的终端具有p型场截止（field stop）层26a、n型场截止层26b以及场截止电极27。p型场截止层26a形成在n型半导体基板11的表面。n型场截止层26b形成在p型场截止层26a的表面。场截止电极27与n型场截止层26b的上表面相接。通过从场截止电极27向上述的p型场截止层26a及n型场截止层26b施加电压来形成的电场，能够抑制耗尽层延伸到n型半导体基板11的终端。
如图2所示，终端区域20具有沟道T、绝缘层28以及场板导电层29。沟道T如图2所示那样挖入n型半导体基板11来形成，如图1所示那样形成为包围元件区域10的涡旋状。此外，涡旋状是一例，沟道T也可以形成为同心圆状。沟道T的深度例如比p型基底层12的下端深，为2μm～6μm。另外，沟道T的宽度例如比p型基底层12的宽度窄，为0.4μm～2.0μm。
绝缘层28形成在沟道T的内壁。例如，绝缘层28由氧化硅(SiO2)构成，具有0.05μm～0.20μm的厚度。场板导电层29隔着绝缘层28填埋沟道T。即，场板导电层29形成为包围元件区域10的涡旋状。此外，涡旋状是一例，场板导电层29也可以与沟道T的形状相应地形成为同心圆状。例如，场板导电层29由多晶硅（polysilicon）、铝等的金属材料中的任一种构成。
通过对上述的场板导电层29施加电压，能够缓和终端区域20的n型半导体基板11的表面的电场的集中。
接着，参照图3A～图3C来说明实施方式所涉及的终端区域20的制造工序。首先，如图3A所示，对n型半导体基板11进行蚀刻来形成从n型半导体基板11的表面起延伸至规定深度的沟道T。接着，如图3B所示，通过化学蒸镀法(CVD)在沟道T的内壁形成规定厚度的绝缘层28。然后，如图3C所示，通过CVD以填埋沟道T的方式形成场板导电层29。
接着，将图4所示的比较例与本实施方式进行比较。图4所示的比较例在终端区域20未形成沟道T。另外，比较例中的绝缘层28和场板导电层29在n型半导体基板11上隔着绝缘层31而形成。仅在上述的方面上，比较例不同于本实施方式。即使是这种比较例，也能够通过场板导电层29与本实施方式同样地缓和电场。
然而，在比较例中，通过CVD在绝缘层31上形成薄膜之后，通过蚀刻对该薄膜进行加工来形成场板导电层29。因而，在制造工序中，在场板导电层29的膜厚及宽度上产生偏差，因此其电阻值也产生偏差。由此，在半导体装置的动作上产生偏差。另外，由于CVD的膜厚的限制、蚀刻的加工尺寸的限制，场板导电层29的宽度不能加工得小。即，在比较例中，难以使终端区域20的尺寸变小。
与此相对，本实施方式如上所述那样在沟道T内具有场板导电层29。因而，在本实施方式中，场板导电层29是不依赖于通过CVD进行的膜厚的控制的构造，因此其电阻值与比较例相比偏差少，本实施方式与比较例相比能够使半导体装置的动作稳定。另外，本实施方式不会如比较例那样受到膜厚的限制、加工尺寸的限制，能够使场板导电层29的宽度小于比较例。即，本实施方式的终端区域20的尺寸能够小于比较例。
[其它]
如上所述的实施方式只是示例性的，并不是限定发明的保护范围。实际上，所述新方法和系统可以进行各种变形，而且在不脱离本发明的宗旨的范围内可以省略、代替或变更所述方法和系统。后述的权利要求书及其均等物均包含在本发明的保护范围内。
例如，在元件区域10中除了MOSFET以外也可以设置IGBT等。

Claims (20)

1.一种半导体装置，具有形成半导体元件的元件区域以及包围所述元件区域的终端区域，该半导体装置的特征在于，具备：
半导体基板；
沟道，在所述终端区域中以包围所述元件区域的方式形成于所述半导体基板；以及
场板导电层，隔着绝缘层形成于所述沟道，
其中，所述绝缘层由氧化硅构成，
所述场板导电层由多晶硅、金属材料中的任一种构成，
所述沟道的宽度是0.4μm～2.0μm，
所述沟道的深度是2μm～6μm。
2.一种半导体装置，具有形成半导体元件的元件区域以及包围所述元件区域的终端区域，该半导体装置的特征在于，具备：
半导体基板；
沟道，在所述终端区域中以包围所述元件区域的方式形成于所述半导体基板；以及
场板导电层，隔着绝缘层形成于所述沟道。
3.根据权利要求2所述的半导体装置，其特征在于，
所述绝缘层由氧化硅构成。
4.根据权利要求3所述的半导体装置，其特征在于，
所述场板导电层由多晶硅、金属材料中的任一种构成。
5.根据权利要求2所述的半导体装置，其特征在于，
所述沟道的宽度是0.4μm～2.0μm。
6.根据权利要求2所述的半导体装置，其特征在于，
所述沟道的深度是2μm～6μm。
7.根据权利要求2所述的半导体装置，其特征在于，
所述沟道和所述场板导电层形成为包围所述元件区域的涡旋状。
8.根据权利要求2所述的半导体装置，其特征在于，
所述沟道和所述场板导电层形成为包围所述元件区域的同心圆状。
9.根据权利要求2所述的半导体装置，其特征在于，
在所述元件区域形成有MOSFET。
10.根据权利要求2所述的半导体装置，其特征在于，
在所述元件区域形成有IGBT。
11.根据权利要求2所述的半导体装置，其特征在于，
所述半导体基板是第一导电类型的半导体基板，
所述半导体装置还具备：
在所述元件区域中形成在所述半导体基板的表面的第二导电类型的基底层；
在所述元件区域中形成在所述基底层的表面并具有高于所述基底层的杂质浓度的第二导电类型的接触层；
在所述元件区域中形成在所述接触层的表面的第一导电类型的源极扩散层；以及
在所述元件区域中隔着栅极绝缘膜形成在所述半导体基板上的栅极电极。
12.根据权利要求2所述的半导体装置，其特征在于，
所述半导体基板是第一导电类型的半导体基板，
所述半导体装置还具备：
在所述终端区域中形成在所述半导体基板的表面的第二导电类型的第一保护环层；
在所述终端区域中形成在所述第一保护环层的表面并具有高于所述第一保护环层的杂质浓度的第二导电类型的第二保护环层；以及
在所述终端区域中形成在所述半导体基板的表面并与所述第一保护环层及所述第二保护环层相邻，具有低于所述第一保护环层的杂质浓度的第二导电类型的第三保护环层，
其中，所述第一保护环层、所述第二保护环层以及所述第三保护环层形成为包围所述元件区域的环状。
13.根据权利要求2所述的半导体装置，其特征在于，还具备：
所述半导体基板是第一导电类型的半导体基板，
所述半导体装置还具备：
在所述终端区域中形成在所述半导体基板的表面的第二导电类型的第一场截止层；以及
在所述终端区域中形成在所述第一场截止层的表面的第一导电类型的第二场截止层，
其中，所述第一场截止层和所述第二场截止层设置在所述半导体基板的终端。
14.一种半导体装置的制造方法，该半导体装置具有形成半导体元件的元件区域以及包围所述元件区域的终端区域，该制造方法的特征在于，
在所述终端区域中以包围所述元件区域的方式在半导体基板中形成沟道，
在所述沟道的内壁形成绝缘层，
在所述沟道中隔着所述绝缘层形成场板导电层。
15.根据权利要求14所述的半导体装置的制造方法，其特征在于，
所述绝缘层由氧化硅构成。
16.根据权利要求15所述的半导体装置的制造方法，其特征在于，
所述场板导电层由多晶硅、金属材料中的任一种构成。
17.根据权利要求14所述的半导体装置的制造方法，其特征在于，
所述沟道的宽度是0.4μm～2.0μm。
18.根据权利要求14所述的半导体装置的制造方法，其特征在于，
所述沟道的深度是2μm～6μm。
19.根据权利要求14所述的半导体装置的制造方法，其特征在于，
所述沟道和所述场板导电层形成为包围所述元件区域的涡旋状。
20.根据权利要求14所述的半导体装置的制造方法，其特征在于，
所述沟道和所述场板导电层形成为包围所述元件区域的同心圆状。
CN201310073821.3A 2012-09-19 2013-03-08 半导体装置及其制造方法 Pending CN103681797A (zh)

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