CN112510087A - p型栅增强型GaN基HEMT器件及其制备方法 - Google Patents
p型栅增强型GaN基HEMT器件及其制备方法 Download PDFInfo
- Publication number
- CN112510087A CN112510087A CN202011378242.6A CN202011378242A CN112510087A CN 112510087 A CN112510087 A CN 112510087A CN 202011378242 A CN202011378242 A CN 202011378242A CN 112510087 A CN112510087 A CN 112510087A
- Authority
- CN
- China
- Prior art keywords
- layer
- type gan
- gan
- ingan
- thickness
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000002360 preparation method Methods 0.000 title claims abstract description 12
- 230000004888 barrier function Effects 0.000 claims abstract description 49
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 238000000034 method Methods 0.000 claims description 11
- 238000001259 photo etching Methods 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 claims 5
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 claims 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims 2
- 229910052799 carbon Inorganic materials 0.000 claims 2
- 229910052742 iron Inorganic materials 0.000 claims 2
- 230000000737 periodic effect Effects 0.000 claims 1
- 238000009792 diffusion process Methods 0.000 abstract description 7
- 239000000463 material Substances 0.000 abstract description 4
- 230000005684 electric field Effects 0.000 abstract description 3
- 230000010287 polarization Effects 0.000 abstract description 3
- 229910002601 GaN Inorganic materials 0.000 description 77
- 229910002704 AlGaN Inorganic materials 0.000 description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000004913 activation Effects 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005034 decoration Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 229910019080 Mg-H Inorganic materials 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 125000004435 hydrogen atom Chemical group [H]* 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000010998 test method Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 230000005533 two-dimensional electron gas Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
本发明提供了一种p型栅增强型GaN基HEMT器件及其制备方法,其中,HEMT器件从下至上依次包括衬底层、缓冲层、耐压层、沟道层及势垒层,还包括形成于势垒层表面的源极和漏极,及形成于势垒层表面的P型GaN/InGaN超晶格层和栅极,其中,P型GaN/InGaN超晶格层中,P型GaN层掺Mg,空穴浓度为5E17‑5E18;InGaN层不掺Mg。其使用p型GaN/InGaN超晶格结构代替传统的p型GaN层,通过GaN/InGaN超晶格的极化电场增加Mg的离化效率,从而降低p型栅中的掺Mg浓度,提高p型栅材料的质量。同时,低浓度掺Mg也减少了Mg向势垒和沟道层中的扩散。
Description
技术领域
本发明涉及半导体技术领域,尤其是一种p型栅增强型GaN基HEMT器件及其制备方法。
背景技术
基于pGaN栅结构的GaN基增强型HEMT有驱动设计简单、失效保护、高频性能突出、与器件一致性较好等特点,已经成为GaN基HEMT器件的主流设计。但是,在pGaN栅HEMT结构中,栅极上的pGaN通常在50nm厚度左右。GaN中Mg杂质的激活能高达120meV-250meV之间(基于不同测试方法),且在GaN生长中Mg和H(氢原子)容易形成Mg-H络合物使得Mg的离化更加困难,导致pGaN中Mg的有效活化率只有实际掺Mg浓度的1%-2%。
为了有效耗尽HEMT异质结沟道二维电子气,pGaN中实际掺Mg浓度一般要求高于5E18cm-3,且栅下AlGaN势垒层厚度需要从通常的25nm左右减薄至10nm-15nm。在GaN中高浓度的Mg原子掺杂可能会导致出现反相畴、点缺陷、表面Mg突起等问题。根据Stockman和Posthuma等人的研究(On the origin of the leakage current in p-gate AlGaN/GaNHEMTs,Arno Stockman et al.,2018IEEE IRPS Conference;Impact of Mg out-diffusion and activation on the p-GaN gate HEMT device performance,N.E.Posthuma et al.,2016 28th ISPSD conference),pGaN高浓度的Mg会向AlGaN势垒层和GaN沟道层扩散,形成载流子陷阱和漏电通道,劣化HEMT器件性能和可靠性。
发明内容
为了克服以上不足,本发明提供了一种p型栅增强型GaN基HEMT器件及其制备方法,有效解决现有HEMT器件中由pGaN高浓度的Mg向AlGaN势垒层和GaN沟道层扩散导致劣化器件性能和可靠性的技术问题。
本发明提供的技术方案为:
一种p型栅增强型GaN基HEMT器件,所述HEMT器件从下至上依次包括衬底层、缓冲层、耐压层、沟道层及势垒层,还包括形成于势垒层表面的源极和漏极,及形成于势垒层表面的P型GaN/InGaN超晶格层和栅极,其中,所述P型GaN/InGaN超晶格层中,P型GaN层掺Mg,空穴浓度为5E17-5E18;InGaN层不掺Mg。
一种p型栅增强型GaN基HEMT器件制备方法,包括:
依次在衬底层表面生长缓冲层、耐压层、沟道层及势垒层;
在所述势垒层表面生长P型GaN/InGaN超晶格层;所述P型GaN/InGaN超晶格层中,P型GaN层掺Mg,空穴浓度为5E17-5E18;InGaN层不掺Mg;
对所述P型GaN/InGaN超晶格层进行光刻,保留栅极区域;
分别在势垒层表面形成源极和漏极,在P型GaN/InGaN超晶格层表面形成栅极,完成HEMT器件的制备。
本发明提供的p型栅增强型GaN基HEMT器件及其制备方法,至少能够带来以下有益效果:
1.使用p型GaN/InGaN超晶格结构代替传统的p型GaN层,通过GaN/InGaN超晶格的极化电场增加Mg的离化效率,从而降低p型栅中的掺Mg浓度,提高p型栅材料的质量。同时,低浓度掺Mg也减少了Mg向势垒和沟道层中的扩散。
2.在势垒层和p型GaN/InGaN超晶格层之间插入1-2nm厚度的薄层uid-AlN层,进一步阻止Mg向势垒层和沟道层中的扩散,减少形成载流子陷阱和漏电通道,提升HEMT器件的性能和可靠性。
附图说明
图1为本发明p型栅增强型GaN基HEMT器件一实施例结构示意图;
图2为本发明p型栅增强型GaN基HEMT器件另一实施例结构示意图。
附图标记:
101/201-衬底层,102/202-缓冲层,103/203-耐压层,104/204-沟道层,105/205-势垒层,106/207-P型GaN/InGaN超晶格层,206-AlN层。
具体实施方式
为了更清楚地说明本发明实施案例或现有技术中的技术方案,下面将对照附图说明本发明的具体实施方式。显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图,并获得其他的实施方式。
本发明的一种实施例,如图1所示,一种p型栅增强型GaN基HEMT器件,从图中可以看出,该HEMT器件从下至上依次包括衬底层、缓冲层、耐压层、沟道层及势垒层,还包括形成于势垒层表面的源极S和漏极D,及形成于势垒层表面的P型GaN/InGaN超晶格层和栅极G,其中,P型GaN/InGaN超晶格层中,P型GaN层掺Mg,空穴浓度为5E17-5E18;InGaN层不掺Mg。
在该HEMT器件器件中,衬底层可以为硅衬底、蓝宝石衬底、SiC衬底等半导体常用衬底。缓冲层中包括GaN、AlN、AlN/AlGaN等结构,以释放应力并过渡到之后的耐压层。耐压层为掺碳(包括内掺和外掺)或掺铁的GaN层,厚度为1000~10000nm。沟道层为非故意掺杂高质量GaN层(uid-GaN层),厚度为100~1000nm。势垒层为AlxGa1-xN层,0.1<x<0.4,且厚度为10~30nm。P型GaN/InGaN超晶格层的厚度为10~100nm,其中,P型GaN层的厚度为0.1~10nm,InGaN层的厚度为0.1~10nm。
在生长过程中,首先依次在衬底层表面生长缓冲层、耐压层、沟道层及势垒层;之后,在势垒层表面生长P型GaN/InGaN超晶格层;接着,对P型GaN/InGaN超晶格层进行光刻,保留栅极区域;最后,分别在势垒层表面形成源极和漏极,在P型GaN/InGaN超晶格层表面形成栅极,完成HEMT器件的制备。应当清楚,本实施例中对各层结构的生长条件和方法不做具体限定,在实际应用中可以采用任意的符合外延生长的环境和条件加以实现,只要能够得到满足上述条件的结构即可。
在该实施例中,在PGaN栅结构中,使用p型GaN/InGaN超晶格结构代替传统的p型GaN层,通过GaN/InGaN超晶格的极化电场增加Mg的离化效率,从而降低p型栅中的掺Mg浓度,提高p型栅材料的质量,同时减少了Mg向势垒和沟道层中的扩散。解决传统PGaN栅结构中pGaN高掺Mg导致pGaN层材料缺陷增加和表面劣化、增加栅漏电风险、加剧阈值电压偏移,及高掺Mg导致Mg杂质向势垒层和沟道层中扩散,导致劣化HEMT器件性能和可靠性等技术问题。
在另一实施例中,如图2所示,该HEMT器件中包括从下至上依次包括衬底层、缓冲层、耐压层、沟道层及势垒层,还包括形成于势垒层表面的源极S和漏极D,及形成于势垒层表面的AlN层、P型GaN/InGaN超晶格层和栅极G,其中,P型GaN/InGaN超晶格层中,P型GaN层掺Mg,空穴浓度为5E17-5E18;InGaN层不掺Mg;AlN层的厚度为1-2nm。
在该HEMT器件器件中,衬底层可以为硅衬底、蓝宝石衬底、SiC衬底等半导体常用衬底。缓冲层中包括GaN、AlN、AlN/AlGaN等结构,以释放应力并过渡到之后的耐压层。耐压层为掺碳(包括内掺和外掺)或掺铁的GaN层,厚度为1000~10000nm。沟道层为非故意掺杂高质量GaN层(uid-GaN层),厚度为100~1000nm。势垒层为AlxGa1-xN层,0.1<x<0.4,且厚度为10~30nm。P型GaN/InGaN超晶格层的厚度为10~100nm,其中,P型GaN层的厚度为0.1~10nm,InGaN层的厚度为0.1~10nm。
在生长过程中,首先依次在衬底层表面生长缓冲层、耐压层、沟道层及势垒层;之后,在势垒层表面生长AlN层,在AlN层表面生长P型GaN/InGaN超晶格层;接着,对AlN层和P型GaN/InGaN超晶格层进行光刻,保留栅极区域;最后,分别在势垒层表面形成源极和漏极,在P型GaN/InGaN超晶格层表面形成栅极,完成HEMT器件的制备。应当清楚,本实施例中对各层结构的生长条件和方法不做具体限定,在实际应用中可以采用任意的符合外延生长的环境和条件加以实现,只要能够得到满足上述条件的结构即可。
在该实施例中,在PGaN栅结构中,使用p型GaN/InGaN超晶格结构代替传统的p型GaN层的同时,在势垒层和p型GaN/InGaN超晶格层之间插入1-2nm厚度的薄层uid-AlN层,进一步阻止Mg向势垒层和沟道层中的扩散,减少形成载流子陷阱和漏电通道,提升HEMT器件的性能和可靠性。
实施例一
通过以下步骤制备如图1所示的p型栅增强型GaN基HEMT器件:
首先,将SiC衬底101放入MOCVD反应室中;之后,在70torr压力、1000℃的温度下生长一层200nm的AlN缓冲层102;改变至75torr压力、1000℃的高阻GaN生长条件,生长3000nm的内掺碳高阻氮化镓耐压薄膜层103;再次改变生长条件至200torr压力、1050℃的GaN生长条件,生长300nm UGaN沟道层104;进一步改变条件至100torr压力、1030℃的AlGaN生长条件,生长15nm的25%Al组分的AlGaN势垒层105;之后,在AlGaN势垒层105上生长p型GaN/InGaN超晶格层106,周期数为15loop,每个周期内p型GaN层和InGaN层的厚度都为2nm,且p型GaN层的空穴浓度为2E18,生长条件为200torr GaN生长气流,温度950℃。最后,通过光刻显影的方法形成源极S、漏极D及栅极G。
实施例二
通过以下步骤制备如图2所示的p型栅增强型GaN基HEMT器件:
首先,将(111)晶向的硅衬底201放入MOCVD反应室中,在70torr压力、1050℃的温度条件下高温H2处理,去除表面氧化物;然后,在70torr压力、1000℃的温度下生长一层1000nm的AlN/AlGaN多层缓冲层202,其中,AlN层的厚度为300nm,AlGaN层的厚度为700nm;改变气氛至70torr压力、1000℃的GaN生长条件,生长3000nm的内掺碳高阻氮化镓耐压薄膜层203;再次改变生长条件至200torr压力、1050℃的GaN生长条件,生长300nm UGaN沟道层204;改变条件至100torr压力、1030℃的AlGaN生长条件,生长15nm的25%Al组分AlGaN势垒层205;进一步改变条件生长至70torr压力、1000℃的温度下生长2nm的AlN层206;之后在AlN层206上面生长p型GaN/InGaN超晶格207,周期数为7loop,每个周期内p型GaN和InGaN都为5nm,且p型GaN的空穴浓度为2E18,生长条件为200torr GaN生长气流,温度950℃。最后,通过光刻显影的方法形成源极S、漏极D,栅极G。
应当说明的是,上述实施例均可根据需要自由组合。以上所述仅是本发明的优选实施方式,应当指出,对于本技术领域的普通技术人员来说,在不脱离本发明原理的前提下,还可以做出若干改进和润饰,这些改进和润饰也应视为本发明的保护范围。
Claims (10)
1.一种p型栅增强型GaN基HEMT器件,其特征在于,所述HEMT器件从下至上依次包括衬底层、缓冲层、耐压层、沟道层及势垒层,还包括形成于势垒层表面的源极和漏极,及形成于势垒层表面的P型GaN/InGaN超晶格层和栅极,其中,所述P型GaN/InGaN超晶格层中,P型GaN层掺Mg,空穴浓度为5E17-5E18;InGaN层不掺Mg。
2.如权利要求1所述的HEMT器件,其特征在于,所述势垒层和P型GaN/InGaN超晶格层之间还包括厚度为1-2nm的AlN层。
3.如权利要求1或2所述的HEMT器件,其特征在于,所述P型GaN/InGaN超晶格层的厚度为10~100nm,其中,P型GaN层的厚度为0.1~10nm,InGaN层的厚度为0.1~10nm。
4.如权利要求1或2所述的HEMT器件,其特征在于,
所述耐压层为掺碳或掺铁的GaN层,厚度为1000~10000nm;和/或,
所述沟道层为非故意掺杂GaN层,厚度为100~1000nm;和/或,
所述势垒层为AlxGa1-xN层,0.1<x<0.4,且厚度为10~30nm。
5.一种p型栅增强型GaN基HEMT器件制备方法,其特征在于,包括:
依次在衬底层表面生长缓冲层、耐压层、沟道层及势垒层;
在所述势垒层表面生长P型GaN/InGaN超晶格层;所述P型GaN/InGaN超晶格层中,P型GaN层掺Mg,空穴浓度为5E17-5E18;InGaN层不掺Mg;
对所述P型GaN/InGaN超晶格层进行光刻,保留栅极区域;
分别在势垒层表面形成源极和漏极,在P型GaN/InGaN超晶格层表面形成栅极,完成HEMT器件的制备。
6.如权利要求5所述的HEMT器件制备方法,其特征在于,在依次在衬底层表面生长缓冲层、耐压层、沟道层及势垒层之后,还包括:
在所述势垒层表面生长AlN层;
在所述势垒层表面生长P型GaN/InGaN超晶格层中,包括:在所述AlN层表面生长P型GaN/InGaN超晶格层;
对所述P型GaN/InGaN超晶格层进行光刻,保留栅极区域中,包括:对所述AlN层和P型GaN/InGaN超晶格层进行光刻,保留栅极区域。
7.如权利要求5或6所述的HEMT器件制备方法,其特征在于,在所述AlN层表面生长P型GaN/InGaN超晶格层中,包括:在所述AlN层表面循环生长预设周期数量的P型GaN层和InGaN层,其中,P型GaN层掺Mg,厚度为0.1~10nm,空穴浓度为5E17-5E18;InGaN层不掺Mg,厚度为0.1~10nm。
8.如权利要求7所述的HEMT器件制备方法,其特征在于,所述P型GaN/InGaN超晶格层的厚度为10~100nm。
9.如权利要求6-8任意一项所述的HEMT器件制备方法,其特征在于,所述AlN层的厚度为1-2nm。
10.如权利要求6-8任意一项所述的HEMT器件制备方法,其特征在于,
所述耐压层为掺碳或掺铁的GaN层,厚度为1000~10000nm;和/或,
所述沟道层为非故意掺杂GaN层,厚度为100~1000nm;和/或,
所述势垒层为AlxGa1-xN层,0.1<x<0.4,且厚度为10~30nm。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202011378242.6A CN112510087B (zh) | 2020-12-01 | 2020-12-01 | p型栅增强型GaN基HEMT器件及其制备方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202011378242.6A CN112510087B (zh) | 2020-12-01 | 2020-12-01 | p型栅增强型GaN基HEMT器件及其制备方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN112510087A true CN112510087A (zh) | 2021-03-16 |
CN112510087B CN112510087B (zh) | 2023-07-11 |
Family
ID=74968780
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202011378242.6A Active CN112510087B (zh) | 2020-12-01 | 2020-12-01 | p型栅增强型GaN基HEMT器件及其制备方法 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN112510087B (zh) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113675269A (zh) * | 2021-08-20 | 2021-11-19 | 电子科技大学 | 一种抑制短沟道效应的p-GaN HEMT器件 |
CN114122107A (zh) * | 2021-10-28 | 2022-03-01 | 华南理工大学 | 一种周期栅结构的p-GaN常闭型功率器件 |
CN114400246A (zh) * | 2021-12-13 | 2022-04-26 | 晶通半导体(深圳)有限公司 | 反向导通高迁移率晶体管 |
Citations (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030136970A1 (en) * | 2002-01-24 | 2003-07-24 | Motonobu Takeya | Semiconductor light emitting device and its manufacturing method |
US20070096077A1 (en) * | 2005-10-31 | 2007-05-03 | Nichia Corporation | Nitride semiconductor device |
JP2012009784A (ja) * | 2010-06-28 | 2012-01-12 | Meijo Univ | 半導体素子、及び半導体素子の転位低減方法 |
CN103855207A (zh) * | 2012-12-04 | 2014-06-11 | 富士通株式会社 | 化合物半导体器件及其制造方法 |
JP2015070252A (ja) * | 2013-10-01 | 2015-04-13 | 富士通株式会社 | 半導体装置、半導体装置の製造方法及びウェハ |
CN104916633A (zh) * | 2014-03-14 | 2015-09-16 | 株式会社东芝 | 半导体装置 |
CN105390541A (zh) * | 2015-10-30 | 2016-03-09 | 江苏能华微电子科技发展有限公司 | Hemt外延结构及其制备方法 |
CN107068746A (zh) * | 2015-11-02 | 2017-08-18 | 英飞凌科技奥地利有限公司 | Iii族氮化物双向器件 |
US20170309736A1 (en) * | 2016-04-26 | 2017-10-26 | Institute of Microelectronics, Chinese Academy of Sciences | Gan-based power electronic device and method for manufacturing the same |
CN107393958A (zh) * | 2017-04-25 | 2017-11-24 | 中国电子科技集团公司第五十五研究所 | 低导通电阻高阈值电压增强型GaN器件的制备方法 |
CN107393956A (zh) * | 2017-07-06 | 2017-11-24 | 中国科学院半导体研究所 | 包含p型超晶格的增强型高电子迁移率晶体管及制备方法 |
CN108461539A (zh) * | 2017-02-20 | 2018-08-28 | 新唐科技股份有限公司 | 晶体管 |
CN110190116A (zh) * | 2019-04-30 | 2019-08-30 | 大连理工大学 | 一种高阈值电压常关型高电子迁移率晶体管及其制备方法 |
CN111477536A (zh) * | 2020-03-31 | 2020-07-31 | 华为技术有限公司 | 一种半导体外延结构及半导体器件 |
-
2020
- 2020-12-01 CN CN202011378242.6A patent/CN112510087B/zh active Active
Patent Citations (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030136970A1 (en) * | 2002-01-24 | 2003-07-24 | Motonobu Takeya | Semiconductor light emitting device and its manufacturing method |
US20070096077A1 (en) * | 2005-10-31 | 2007-05-03 | Nichia Corporation | Nitride semiconductor device |
JP2012009784A (ja) * | 2010-06-28 | 2012-01-12 | Meijo Univ | 半導体素子、及び半導体素子の転位低減方法 |
CN103855207A (zh) * | 2012-12-04 | 2014-06-11 | 富士通株式会社 | 化合物半导体器件及其制造方法 |
JP2015070252A (ja) * | 2013-10-01 | 2015-04-13 | 富士通株式会社 | 半導体装置、半導体装置の製造方法及びウェハ |
CN104916633A (zh) * | 2014-03-14 | 2015-09-16 | 株式会社东芝 | 半导体装置 |
CN105390541A (zh) * | 2015-10-30 | 2016-03-09 | 江苏能华微电子科技发展有限公司 | Hemt外延结构及其制备方法 |
CN107068746A (zh) * | 2015-11-02 | 2017-08-18 | 英飞凌科技奥地利有限公司 | Iii族氮化物双向器件 |
US20170309736A1 (en) * | 2016-04-26 | 2017-10-26 | Institute of Microelectronics, Chinese Academy of Sciences | Gan-based power electronic device and method for manufacturing the same |
CN108461539A (zh) * | 2017-02-20 | 2018-08-28 | 新唐科技股份有限公司 | 晶体管 |
CN107393958A (zh) * | 2017-04-25 | 2017-11-24 | 中国电子科技集团公司第五十五研究所 | 低导通电阻高阈值电压增强型GaN器件的制备方法 |
CN107393956A (zh) * | 2017-07-06 | 2017-11-24 | 中国科学院半导体研究所 | 包含p型超晶格的增强型高电子迁移率晶体管及制备方法 |
CN110190116A (zh) * | 2019-04-30 | 2019-08-30 | 大连理工大学 | 一种高阈值电压常关型高电子迁移率晶体管及其制备方法 |
CN111477536A (zh) * | 2020-03-31 | 2020-07-31 | 华为技术有限公司 | 一种半导体外延结构及半导体器件 |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113675269A (zh) * | 2021-08-20 | 2021-11-19 | 电子科技大学 | 一种抑制短沟道效应的p-GaN HEMT器件 |
CN114122107A (zh) * | 2021-10-28 | 2022-03-01 | 华南理工大学 | 一种周期栅结构的p-GaN常闭型功率器件 |
CN114400246A (zh) * | 2021-12-13 | 2022-04-26 | 晶通半导体(深圳)有限公司 | 反向导通高迁移率晶体管 |
Also Published As
Publication number | Publication date |
---|---|
CN112510087B (zh) | 2023-07-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9548376B2 (en) | Method of manufacturing a semiconductor device including a barrier structure | |
JP5813279B2 (ja) | 窒化物ベースのトランジスタのための窒化アルミニウムを含むキャップ層およびその作製方法 | |
KR101124937B1 (ko) | 질화물계 트랜지스터를 위한 캡층 및/또는 패시베이션층,트랜지스터 구조 및 그 제조방법 | |
CN112510087B (zh) | p型栅增强型GaN基HEMT器件及其制备方法 | |
CN112701160B (zh) | 氮化镓基高电子迁移率晶体管外延片及其制备方法 | |
JP2007165431A (ja) | 電界効果型トランジスタおよびその製造方法 | |
TW201436008A (zh) | 異質接面電晶體及其製造方法 | |
JP6392498B2 (ja) | 化合物半導体装置及びその製造方法 | |
TW201513342A (zh) | 半導體裝置及其製造方法 | |
JP2005085852A (ja) | 半導体電子デバイス | |
CN111406306B (zh) | 半导体装置的制造方法、半导体装置 | |
US20160079370A1 (en) | Semiconductor device, semiconductor wafer, and semiconductor device manufacturing method | |
US8994032B2 (en) | III-N material grown on ErAIN buffer on Si substrate | |
WO2023024550A1 (zh) | 增强型GaN基HEMT器件、器件外延及其制备方法 | |
US11430875B2 (en) | Method for manufacturing transistor | |
CN112133749A (zh) | 一种p型帽层增强型hemt器件及其制备方法 | |
US20230238446A1 (en) | Semiconductor structure and manufacturing method thereof | |
JP2021500747A (ja) | 窒化ホウ素合金中間層を有する高電子移動度トランジスタ及び製造方法 | |
CN111009468A (zh) | 一种半导体异质结构制备方法及其用途 | |
CN112510088A (zh) | 沟槽栅增强型GaN基HEMT器件及其制备方法 | |
CN212542443U (zh) | 一种氮化镓晶体管结构及氮化镓基外延结构 | |
JP2009246307A (ja) | 半導体装置及びその製造方法 | |
CN114551594A (zh) | 一种外延片、外延片生长方法及高电子迁移率晶体管 | |
KR20130137774A (ko) | 헤테로 구조 반도체 소자 | |
JP2012227227A (ja) | 半導体デバイス |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
CB02 | Change of applicant information |
Address after: 330096 No. 699, Aixi Hubei Road, Nanchang High-tech Development Zone, Jiangxi Province Applicant after: Jingneng optoelectronics Co.,Ltd. Address before: 330096 No. 699, Aixi Hubei Road, Nanchang High-tech Development Zone, Jiangxi Province Applicant before: LATTICE POWER (JIANGXI) Corp. |
|
CB02 | Change of applicant information | ||
GR01 | Patent grant | ||
GR01 | Patent grant |