CN112490286A - 半导体装置及其制作方法 - Google Patents

半导体装置及其制作方法 Download PDF

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CN112490286A
CN112490286A CN201910862797.9A CN201910862797A CN112490286A CN 112490286 A CN112490286 A CN 112490286A CN 201910862797 A CN201910862797 A CN 201910862797A CN 112490286 A CN112490286 A CN 112490286A
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layer
semiconductor device
gate
patterned structure
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CN112490286B (zh
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张峻铭
廖文荣
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United Microelectronics Corp
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Abstract

本发明公开一种半导体装置及其制作方法，其中该半导体装置包括具有主动区域和绝缘区域的增强型高电子迁移率晶体管。增强型高电子迁移率晶体管包括基板、III‑V族主体层、III‑V族阻障层、III‑V族栅极结构以及III‑V族图案化结构。III‑V族主体层及III‑V族阻障层会分别设置于基板之上。III‑V族栅极结构会被设置于主动区域内的III‑V族阻障层之上。III‑V族图案化结构会被设置于绝缘区域内的III‑V族阻障层之上，其中III‑V族图案化结构的组成和III‑V族栅极结构的组成相同。

Description

半导体装置及其制作方法
技术领域
本发明涉及高电子迁移率晶体管的领域，特别是涉及一种增强型高电子迁移率晶体管。
背景技术
在半导体技术中，III-V族的半导体化合物可用于形成各种集成电路装置，例如：高功率场效晶体管、高频晶体管或高电子迁移率晶体管(high electron mobilitytransistor,HEMT)。HEMT是属于具有二维电子气(two dimensional electron gas,2DEG)层的一种场效晶体管，其2DEG层会邻近于带隙不同的两种材料之间的接合面(亦即，异质接合面)。由于HEMT并非使用掺杂区域作为晶体管的载流子通道，而是使用2-DEG层作为晶体管的载流子通道，因此相较于现有的金属氧化物半导体场效晶体管(MOSFET)，HEMT具有多种吸引人的特性，例如：高电子迁移率及以高频率传输信号的能力。然而，在现有的HEMT的制作工艺中，需利用多道光刻及蚀刻制作工艺，以定义出HEMT的源/漏极区域和两相邻HEMT间的绝缘区域，此增加了制作工艺的复杂程度。此外，两相邻HEMT间的绝缘区域会较周遭区域更为凹陷，此也影响了绝缘区域中的内连线的平整度。因此，有必要对上述缺陷加以改善。
发明内容
有鉴于此，有必要提出一种改良的高电子迁移率晶体管，以改善现有高电子迁移率晶体管所存在的缺失。
本发明的一实施例揭露了一种半导体装置，其包括具有主动(有源)区域和绝缘区域的增强型高电子迁移率晶体管。增强型高电子迁移率晶体管包括基板、III-V族主体层、III-V族阻障层、III-V族栅极结构以及III-V族图案化结构。III-V族主体层及III-V族阻障层会分别设置于基板之上。III-V族栅极结构会被设置于主动区域内的III-V族阻障层之上。III-V族图案化结构会被设置于绝缘区域内的III-V族阻障层之上，其中III-V族图案化结构的组成和III-V族栅极结构的组成相同。
本发明的另一实施例揭露了一种半导体装置的制作方法，半导体装置包括主动区域和绝源区域，而且制作方法包括下列步骤：提供基板，其上设置有III-V族主体层、III-V族阻障层及III-V族栅极层；以及图案化III-V族栅极层，以于主动区域内形成III-V族栅极结构以及于绝缘区域内形成III-V族图案化结构。
为让本发明的上述目的、特征及优点能更明显易懂，下文特举优选实施方式，并配合所附的附图，作详细说明如下。然而如下的优选实施方式与附图仅供参考与说明用，并非用来对本发明加以限制者。
附图说明
图1是本发明一实施例所绘示的半导体装置的俯视示意图；
图2是本发明一实施例所绘示的半导体装置的剖面示意图；
图3是本发明一实施例所绘示的基板上设置有主体层、阻障层、栅极层和蚀刻掩模层的半导体装置的剖面示意图；
图4是本发明一实施例所绘示的图案化蚀刻掩模层后的半导体装置的剖面示意图；
图5是本发明一实施例所绘示的图案化III-V族栅极层后的半导体装置的剖面示意图；
图6是本发明一实施例所绘示的沉积钝化层后的半导体装置的剖面示意图；
图7是本发明一实施例所绘示的在钝化层中形成接触洞后的半导体装置的剖面示意图；
图8是本发明一实施例所绘示的在接触洞中形成导电结构后的半导体装置的剖面示意图；
图9是本发明一实施例的半导体装置的制作方法流程图；
图10是本发明一实施例的增强型高电子迁移率晶体管的俯视示意图；
图11是本发明一实施例的增强型高电子迁移率晶体管的俯视示意图。
主要元件符号说明
10半导体装置
100-1第一高电子迁移率晶体管
100-2第二高电子迁移率晶体管
102A主动区域
102B绝缘区域
104、106源/漏极区域
108栅极区域
110、112源/漏极电极
114栅极电极
120基板
122缓冲层
124III-V族主体层
126III-V族阻障层
128蚀刻停止层
133III-V族栅极层
134-1III-V族栅极结构
134-2III-V族图案化结构
135、136蚀刻掩模层
138钝化层
140二维电子气区域
142二维电子气截断区域
144接触洞
150、150-1、150-2、150-3内连线
200方法
202、204、206步骤
具体实施方式
通过参考下文中的详细说明并同时结合附图，本技术领域的技术人员可理解本发明的内容。需注意的是，考虑到附图的简洁性，并为了使本技术领域的技术人员能容易了解，附图中的特定元件并非依照实际比例绘制。此外，附图中各元件的数量及尺寸仅作为示意，并非用来限制本发明的范围。
本发明说明书与附上的权利要求中会使用某些词汇来指称特定元件。本领域的技术人员应理解，半导体元件制造商可能会以不同的名称来指称相同的元件。本文并不意在区分那些功能相同但名称不同的元件。在权利要求书与下文说明书中，「包含」、「包括」及「具有」等词为开放式用语，因此其应被解释为「含有但不限定为…」的意思。
说明书与权利要求中所使用的序数例如「第一」、「第二」等的用词，以修饰权利要求的元件，其本身并不代表该元件有任何之前的序数，也不代表某一元件与另一元件的顺序、或是制造方法上的顺序，该些序数的使用仅用来使具有某命名的一请求元件得以和另一具有相同命名的请求元件能作出清楚区分。
在说明书及与权利要求中当中所提及的「耦接」、「耦合」一词包含任何直接及间接的电气连接手段。举例而言，若文中描述一第一元件耦接于一第二元件，则代表该第一元件可直接电气连接于该第二元件，或通过其他元件或连接手段间接地电气连接至该第二元件。
另外，针对本发明中所提及的空间相关的叙述词汇，例如：「在...之下」，「低」，「下」，「上方」，「之上」，「下」，「顶」，「底」和类似词汇时，为便于叙述，其用法均在于描述附图中一个元件或特征与另一个(或多个)元件或特征的相对关系。除了附图中所显示的摆向外，这些空间相关词汇也用来描述半导体装置在使用中以及操作时的可能摆向。随着半导体装置的摆向的不同(旋转90度或其它方位)，用以描述其摆向的空间相关叙述也应通过类似的方式予以解释。
尽管本发明的所描述的数值范围与参数为约略值，在具体实施例中所描述的数值尽可能的精准描述。然而，由于测量过程必然会产生些许测量偏差，因此通过这些测量过程所获得的数值本质上必然会包括些许误差。此外，在下文中，术语「约」通常指在给定数值或范围的10％、5％、1％或0.5％内。或者，术语「约」指在所属技术领域中具有通常技术者可接受的平均的标准偏差内。本文所揭露的所有的数值范围、数量、值、与百分比，其可用于描述例如材料的重量、期间、温度、操作条件、数量比例及其类似的描述，且应被理解为受到术语「约」的修饰。据此，除非有相反的指示，本发明所阐述的数值参数是约略数，其可视需要而变化，或至少应根据所揭露的有意义的位数数字并且使用通常的进位方式，以解读各个数值参数。下文中，范围可表示为从一端点至另一端点，或是在两个端点之间。除非特别声明，否则本发明中的所有范围都包含端点。
在不脱离本发明的精神下，下文所描述的不同实施例中的技术特征彼此间可以被置换、重组、混合，以构成其他的实施例。
本发明有关于一种半导体装置，其包括高电子迁移率晶体管(HEMT)。HEMT可以作为电压转换器应用的功率切换晶体管。相较于硅功率晶体管，由于III-V HEMT具有较宽的能带间隙，因此具有低导通电阻(on-state resistance)与低切换损失的特征。在本发明中，「III-V族半导体(group III-V semiconductor)」是指包含至少一III族元素与至少一V族元素的化合物半导体，其中，III族元素可以是硼(B)、铝(Al)、镓(Ga)或铟(In)，而V族元素可以是氮(N)、磷(P)、砷(As)或锑(Sb)。进一步而言，「III-V族半导体」可以包括：氮化镓(GaN)、磷化铟(InP)、砷化铝(AlAs)、砷化镓(GaAs)、氮化铝镓(AlGaN)、氮化铟铝镓(InAlGaN)、氮化铟镓(InGaN)、其类似物或上述化合物的组合，但不限于此。此外，「III族-氮化物半导体」是指包含氮与至少一III族元素的化合物半导体，例如：GaN、氮化铝(AlN)、氮化铟(InN)、AlGaN、InGaN、InAlGaN、其类似物或上述化合物的组合，但不限于此。
图1是根据本发明一实施例所绘示的半导体装置的俯视示意图。参考图1，半导体装置10中可以包括多个高电子迁移率晶体管，例如第一高电子迁移率晶体管100-1和第二高电子迁移率晶体管100-2。其中，各高电子迁移率晶体管可具有相同的结构，因此各高电子迁移率晶体管可以被视为是半导体装置10中的重复单元。以第一高电子迁移率晶体管100-1为例，其可以包括主动区域102A和绝缘区域102B。主动区域102A中可以设置有源/漏极区域114、116和栅极区域108，因此可用于实现电流传导及/或开关的功能。而绝缘区域102B会围绕主动区域102A而设置，其可用于避免两相邻的主动区域102A发生不必要的电耦合。根据一实施例，源/漏极区域114会被设置于主动区域102A的中间区域，因此栅极区域108会环绕住源/漏极区域104，且源/漏极区域106会环绕住栅极区域108。此外，为了降低接触电阻，可以在源/漏极区域104、栅极区域108和源/漏极区域106的表面上分别设置低电阻的导电电极，例如源/漏极电极110、栅极电极114和源/漏极电极112。根据一实施例，栅极电极114可以环绕源/漏极区域104，然而根据另一实施例，栅极电极114可以仅设置在源/漏极区域104的某一侧或某两侧，但不限定于此。
图2是根据本发明一实施例所绘示的半导体装置的剖面示意图，其大致对应于图1中的剖线A-A’。同时参考图1和图2，半导体装置10会至少包括基板120、III-V族主体层124、III-V族阻障层126、III-V族栅极结构134-1以及III-V族图案化结构134-2。其中，III-V族主体层124和III-V族阻障层126会被设置于基板120之上。III-V族栅极结构134-1以及III-V族图案化结构134-2会被设置于III-V族阻障层126之上，且彼此间会互相分离，使得III-V族栅极结构134-1会被设置于主动区域102A内，而III-V族图案化结构134-2会被设置于绝缘区域102B内。此外，III-V族栅极结构134-1以及III-V族图案化结构134-2的底面可以互相切齐。III-V族栅极结构134-1以及III-V族图案化结构134-2可具有相同的组成，例如P型GaN或P型AlGaN，且其组成会不同于下方的III-V族阻障层126。根据一实施例，未被III-V族栅极结构134-1和III-V族图案化结构134-2覆盖的区域可以对应至源/漏极区域104、106，其对应的III-V族主体层124中会产生二维电子气，而成为二维电子气区域140。相较之下，被III-V族栅极结构134-1和III-V族图案化结构134-2覆盖的区域可以对应至栅极区域108或绝缘区域102B，其对应的III-V族主体层124中则不会产生二维电子气，因而成为二维电子气截断区域142。对于此二维电子气截断区域142，其电阻值会远大于二维电子气区域140，因此可以被视为是电性绝缘区域。根据本发明，通过在特定区域内的III-V族阻障层126之上设置III-V族栅极结构134-1或III-V族图案化结构134-2，可以使得二维电子气只形成在特定的区域中，例如仅形成在源/漏极区域104、106中。
此外，III-V族阻障层126上方另可以设置钝化层138，以降低存在于III-V族阻障层126表面的缺陷。根据一实施例，钝化层138会覆盖住III-V族栅极结构134-1和III-V族图案化结构134-2的顶面和侧面。由于III-V族栅极结构134-1和III-V族图案化结构134-2的厚度不会大于150纳米，因此位于主动区域102A内的钝化层138可以具有一平坦的顶面，致使后续形成于钝化层138上方的内连线可以连续分布，而不会发生断裂的情形。
III-V族主体层124可包含一层或多层III-V族半导体层，III-V族半导体层的成份可以是GaN、AlGaN、InGaN或InAlGaN，但不限定于此。此外，III-V族主体层124也可以是被掺杂的一层或多层III-V族半导体层，例如是p型的III-V族半导体层。对于p型的III-V族半导体层而言，其掺质可以是C、Fe、Mg或Zn，或不限定于此。上述III-V族阻障层126可包含一层或多层III-V族半导体层，且其组成会不同于III-V族主体层124的III-V族半导体。举例来说，III-V族阻障层126可包含AlN、AlyGa(1-y)N(0＜y＜1)或其组合。根据一实施例，III-V族主体层124可以是未经掺杂的GaN层，而III-V族阻障层126可以是本质上为n型的AlGaN层。由于III-V族主体层124和III-V族阻障层126间具有不连续的带隙，通过将III-V族主体层124和III-V族阻障层126互相堆叠设置，电子会因压电效应(piezoelectric effect)而被聚集于III-V族主体层124和III-V族阻障层126之间的异质接面，因而产生高电子迁移率的薄层，亦即二维电子气。上述钝化层138的组成可包括氮化铝、氧化铝或氮化硅，但不限定于此。
根据一实施例，基板120和III-V族主体层124之间另可包括缓冲层122，其可以用于降低存在于基板120和III-V族主体层124之间的应力或晶格不匹配的程度。此外，III-V族阻障层126和III-V族栅极结构134-1及III-V族图案化结构134-2之间可以另外设置有蚀刻停止层128，例如AlN，其可用于保护III-V族阻障层126，避免III-V族阻障层126在形成III-V族栅极结构134-1和III-V族图案化结构134-2的制作工艺中被蚀除。
根据一实施例，III-V族阻障层126和钝化层138之间可以另外设置有蚀刻掩模层136。在形成III-V族栅极结构134-1和III-V族图案化结构134-2的蚀刻过程中，蚀刻掩模层136会覆盖住部分的III-V栅极层(图未示)，以定义出III-V族栅极结构134-1和III-V族图案化结构134-2的位置。蚀刻掩模层136的组成可包括氮化硅或氧化硅。
根据一实施例，源/漏极电极110、112和栅极电极114会被设置于主动区域102A内。其中，源/漏极电极110、112会直接接触III-V族阻障层126，使得源/漏极电极110、112电耦合至相应的III-V族阻障层126，而栅极电极114则会直接接触III-V族栅极结构134-1，使得栅极电极114电耦合至相应的III-V族栅极结构134-1。通过对源/漏极电极110、112施予适当的偏压，可以让电流流入或流出源/漏极区域104、106。此外，通过对栅极电极114施予适当的偏压，可以控制通道区域的导通程度，而让电流得以在源/漏极区域104、106之间流通。上述源/漏极电极110、112和栅极电极114可以是单层或多层结构，且其组成可以包括Al、Cu、W、Au、Pt、Ti、多晶硅等低阻值的半导体、金属或合金，但不限定于此。
为了使本技术领域中的通常知识者可据以实现本发明中所述的发明，以下进一步具体描述本发明的半导体装置的制作方法。
图3是根据本发明一实施例所绘示的基板上设置有主体层、阻障层、栅极层和蚀刻掩模层的半导体装置的剖面示意图。如图3所示，半导体装置10的基板120可以被划分成交替设置的主动区域102A和绝缘区域102B，基板120上可依序堆叠有缓冲层122、III-V族主体层124、III-V族阻障层126、蚀刻停止层128、III-V族栅极层133及蚀刻掩模层135。其中，上述基板120可以是块硅基板、碳化硅(SiC)基板、蓝宝石(sapphire)基板、绝缘层上覆硅(silicon on insulator，SOI)基板或绝缘层上覆锗(germanium on insulator，GOI)基板，但不限定于此，且可以通过任何合适的方式形成基板120上的各堆叠层，例如可通过分子束外延(molecular-beam epitaxy,MBE)、金属有机化学气相沉积(metal organic chemicalvapor deposition,MOCVD)、氢化物气相外延(hydride vapor phase epitaxy,HVPE)、原子层沉积(atomic layer deposition,ALD)或其他合适的方式。其中，缓冲层122可能包括多个子半导体，且其整体的电阻值会高于基板120上其他层的电阻值。具体而言，缓冲层122中的部分元素的比例，例如金属元素，会由基板120往III-V族主体层124的方向逐渐改变。举例而言，对于基板120和III-V族主体层124分别为硅基板和GaN层的情形，缓冲层122可以是组成比例渐变的氮化铝镓(AlxGa(1-x)N)，且顺着基板120往III-V族主体层124的方向，所述X值会以连续或阶梯变化方式自0.9降低至0.15；或者缓冲层122也可为多层超晶格(superlattice)结构。设置于III-V族阻障层126上方的III-V族栅极层133可包含一层或多层III-V族半导体层，且III-V族半导体层的成份可以是GaN、AlGaN、InGaN或InAlGaN，但不限定于此。此外，III-V族栅极层133也可以是被掺杂的一层或多层III-V族半导体层，例如是P型的III-V族半导体层。对于P型的III-V族半导体层而言，其掺质可以是C、Fe、Mg或Zn，但不限定于此。根据一实施例，III-V族栅极层133可以是P型的GaN层。
图4是根据本发明一实施例所绘示的图案化蚀刻掩模层后的半导体装置的剖面示意图。在图3所示的制作工艺步骤之后，接着可以利用适当的光刻和蚀刻制作工艺，以图案化位于III-V族栅极层133上方的蚀刻掩模层135，而形成图案化的蚀刻掩模层136。由于部分的III-V族栅极层133不会被蚀刻掩模层136覆盖，因此在后续的蚀刻制作工艺中，未被蚀刻掩模层136覆盖的III-V族栅极层133至少会被部分蚀除，致使III-V族栅极层133被图案化。
图5是根据本发明一实施例所绘示的图案化III-V族栅极层后的半导体装置的剖面示意图。在图4所示的制作工艺步骤之后，接着可以利用蚀刻掩模层136作为蚀刻掩模，施行适当蚀刻制作工艺，以蚀刻未被蚀刻掩模层136覆盖的III-V族栅极层133，而形成III-V族栅极结构134-1和III-V族图案化结构134-2。通过此蚀刻制作工艺，可以同时于主动区域102A内形成III-V族栅极结构134-1，并且于绝缘区域102B内形成III-V族图案化结构134-2。此外，通过移除部分的III-V族栅极层133，可以使得二维电子气区域140被产生于未被III-V族栅极结构134-1和III-V族图案化结构134-2覆盖的区域。
图6是根据本发明一实施例所绘示的沉积钝化层后的半导体装置的剖面示意图。在图5所示的制作工艺步骤之后，接着可以全面性的沉积钝化层138，使得钝化层138覆盖住III-V族栅极结构134-1和III-V族图案化结构134-2，并且填满III-V族栅极结构134-1和III-V族图案化结构134-2之间的空隙。其中，钝化层138的组成包括氮化铝、氧化铝或氮化硅，但不限定于此，其可用于消除或减少存在于III-V族阻障层126的表面缺陷，进而提升二维电子气区域140的电子迁移率。
图7是根据本发明一实施例所绘示的在钝化层中形成接触洞后的半导体装置的剖面示意图。在图6所示的制作工艺步骤之后，接着可以施行适当的光刻和蚀刻制作工艺，以于钝化层138内形成接触洞144。根据一实施例，接触洞144只会被形成于主动区域102A内，而不会被形成于绝缘区域102B内。此外，接触洞144除了会贯穿钝化层138，部分的接触洞144也会进一步贯穿蚀刻掩模层136或蚀刻停止层128，致使III-V族栅极结构134-1及III-V族阻障层126可以部分暴露出于接触洞144的底部。
图8是根据本发明一实施例所绘示的在接触洞中形成导电结构后的半导体装置的剖面示意图。在图7所示的制作工艺步骤之后，之后再经由合适的沉积和蚀刻制作工艺，以形成填满接触洞144的导电结构，例如是源/漏极电极110、源/漏极电极112和栅极电极114。源/漏极电极110和源/漏极电极112可以分别电耦合至主动区域102A中的源/漏极区域，而栅极电极114则会电耦合至III-V族栅极结构134-1。根据一实施例，源/漏极电极110、源/漏极电极112和栅极电极114只会被设置于主动区域102A，而不会被设置于绝缘区域102B中。换句话说，源/漏极电极110、源/漏极电极112和栅极电极114会分离于III-V族图案化结构134-2。
接着，仍如图8所示，可以施行适当的沉积和蚀刻制作工艺，以于钝化层138的表面上形成多个导电内连线150。其中，内连线150可以各自电耦合至下方的源/漏极电极110、源/漏极电极112和栅极电极114。由于III-V族栅极结构134-1和其上方蚀刻掩模层136的整体厚度总和(或是III-V族图案化结构134-2和其上方蚀刻掩模层136的整体厚度总和)不会大于150纳米，因此位于主动区域102A和绝缘区域102B内的钝化层138可以具有一平坦的顶面，致使形成于钝化层138上方的内连线150可以连续分布，而不会发生断裂的情形。此外，钝化层138和内连线150之间另可以设置有其他的层间介电层或蚀刻停止层，但不限定于此。
根据本发明，半导体装置10可以包括至少二增强型高电子迁移率晶体管100-1、100-2，分别设置于主动区域102A中，且两相邻的增强型高电子迁移率晶体管可以具有共用绝缘区域102B。其中，主动区域102A和绝缘区域102B中的III-V族栅极结构134-1和III-V族图案化结构134-2可以利用同一道光刻和蚀刻制作工艺而同时形成，因此可以简化制作工艺。换言之，根据本案一实施例，可利用同一道光罩以定义出主动区域102A和绝缘区域102B，而不需额外利用另一光罩以定义出平台(mesa)区域。此外，两相邻高电子迁移率晶体管100-1、100-2间的绝缘区域102B的深度也不会太深，例如低于150纳米，因此绝缘区域102B中的内连线150可以具有较佳的平整度。
图9是本发明一实施例的半导体装置的制作方法流程图。根据本发明的一实施例，制作高电子迁移率晶体管的方法200可以包括：步骤202：提供半导体基板，其上设置有III-V族主体层、III-V族阻障层和III-V族栅极层；步骤204：图案化III-V族栅极层，以于主动区域中形成III-V族栅极结构和于绝缘区域中形成III-V族图案化结构；步骤206：在III-V族栅极结构和III-V族图案化结构上沉积钝化层。
图10是本发明一实施例的增强型高电子迁移率晶体管的俯视示意图。图10所示的半导体装置10大致类似于图1所示的半导体装置10，然而两者的差异主要在于源/漏极区域104、106和栅极区域108设计布局。具体而言，图10所示的半导体装置10至少包括一高电子迁移率晶体管100-1，其源/漏极区域104设置于中间区域，且其俯视外观呈现圆形，栅极区域108和源/漏极区域106会依序绕住源/漏极区域104。因此，通过对栅极区域108施予特定的偏压，可以让电流在源/漏极区域104和源/漏极区域106间流通。此外，源/漏极区域104、106和栅极区域108的表面上可以设置有导电电极，例如源/漏极电极110、112和栅极电极114。源/漏极电极110的面积会小于源/漏极区域104的面积，且其可以电耦合至内连线150-1。源/漏极电极112的面积会小于源/漏极区域106的面积，且电耦合至内连线150-2。栅极电极114可以环绕住源/漏极区域104，且栅极电极114的面积会小于栅极区域108的面积，且电耦合至内连线150-3。
图11是本发明一实施例的增强型高电子迁移率晶体管的俯视示意图。图11所示的半导体装置10大致类似于图10所示的半导体装置10，然而两者的差异主要在于源/漏极区域104、106和栅极区域108设计布局。具体而言，图11所示的半导体装置10的源/漏极区域104设置于中间区域，且其俯视外观呈现矩形，栅极区域108和源/漏极区域106会依序绕住源/漏极区域104，且两者也具有矩形的俯视外观。图11所示的半导体装置10也可具有导电电极和内连线，其结构大致类似于图10所示的结构，为了简洁起见，在此不再赘述。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (20)

1.一种半导体装置，其特征在于，包括：
增强型高电子迁移率晶体管，包括主动区域和绝缘区域，该增强型高电子迁移率晶体管包括：
基板；
III-V族主体层以及III-V族阻障层，分别设置于该基板之上；
III-V族栅极结构，设置于该主动区域内的该III-V族阻障层之上；以及
III-V族图案化结构，设置于该绝缘区域内的该III-V族阻障层之上，其中该III-V族图案化结构的组成和该III-V族栅极结构的组成相同。
2.根据权利要求1所述的半导体装置，其特征在于，该III-V族栅极结构的底面会切齐于该III-V族图案化结构的底面。
3.根据权利要求1所述的半导体装置，其特征在于，该III-V族栅极结构的组成和该III-V族图案化结构的组成为P型GaN或P型AlGaN。
4.根据权利要求1所述的半导体装置，其特征在于，该半导体装置还包括蚀刻停止层，设置于该III-V族图案化结构和该III-V族阻障层之间。
5.根据权利要求1所述的半导体装置，其特征在于，该半导体装置还包括蚀刻掩模层，设置于该III-V族栅极结构和该III-V族图案化结构的顶面。
6.根据权利要求5所述的半导体装置，其特征在于，该蚀刻掩模层的组成包括氮化硅或氧化硅。
7.根据权利要求1所述的半导体装置，其特征在于，该半导体装置还包括钝化层，设置于该III-V族栅极结构和该III-V族图案化结构之上。
8.根据权利要求7所述的半导体装置，其特征在于，该半导体装置还包括蚀刻掩模层，设置于该钝化层和该III-V族图案化结构之间。
9.根据权利要求7所述的半导体装置，其特征在于，该钝化层的组成包括氮化铝、氧化铝或氮化硅。
10.根据权利要求1所述的半导体装置，其特征在于，该半导体装置还包括设置于该增强型高电子迁移率晶体管一侧的另一增强型高电子迁移率晶体管，其中部分该III-V族图案化结构会连续地被设置于该些增强型高电子迁移率晶体管之间。
11.一种半导体装置的制作方法，该半导体装置包括主动区域和绝源区域，其特征在于，该制作方法包括：
提供基板，其上设置有III-V族主体层、III-V族阻障层及III-V族栅极层；以及
图案化该III-V族栅极层，以于该主动区域内形成III-V族栅极结构以及于该绝缘区域内形成III-V族图案化结构。
12.根据权利要求11所述的半导体装置的制作方法，其特征在于，该III-V族栅极结构以及该III-V族图案化结构会同时形成。
13.根据权利要求11所述的半导体装置的制作方法，其特征在于，该制作方法还包括：
在该III-V族栅极层之上形成一图案化蚀刻掩模层；以及
利用该图案化蚀刻掩模层作为蚀刻掩模，以蚀刻该III-V族栅极层。
14.根据权利要求13所述的半导体装置的制作方法，其特征在于，该制作方法还包括沉积一钝化层于该III-V族栅极结构及该III-V族图案化结构之上。
15.根据权利要求14所述的半导体装置的制作方法，其特征在于，该钝化层的组成包括氮化铝、氧化铝或氮化硅。
16.根据权利要求14所述的半导体装置的制作方法，其特征在于，该蚀刻掩模层会设置于该钝化层和该III-V族图案化结构之间。
17.根据权利要求14所述的半导体装置的制作方法，其特征在于，该制作方法还包括形成栅极电极及至少二个源/漏极电极，分别穿透该钝化层，其中该些电极会分离于该III-V族图案化结构。
18.根据权利要求11所述的半导体装置的制作方法，其特征在于，该III-V族栅极结构的底面会切齐于该III-V族图案化结构的底面。
19.根据权利要求11所述的半导体装置的制作方法，其特征在于，该III-V族栅极结构的组成和该III-V族图案化结构的组成为P型GaN或P型AlGaN。
20.根据权利要求11所述的半导体装置的制作方法，其特征在于，该基板之上另设置有蚀刻停止层，且该蚀刻停止层会被设置于该III-V族阻障层及该III-V族栅极层之间。
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