WO2023197088A1 - 半导体元件及其制作方法 - Google Patents

半导体元件及其制作方法 Download PDF

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Publication number
WO2023197088A1
WO2023197088A1 PCT/CN2022/000065 CN2022000065W WO2023197088A1 WO 2023197088 A1 WO2023197088 A1 WO 2023197088A1 CN 2022000065 W CN2022000065 W CN 2022000065W WO 2023197088 A1 WO2023197088 A1 WO 2023197088A1
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insulating layer
opening
layer
semiconductor
semiconductor device
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PCT/CN2022/000065
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English (en)
French (fr)
Inventor
陈志濠
沈依如
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嘉和半导体股份有限公司
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Priority to PCT/CN2022/000065 priority Critical patent/WO2023197088A1/zh
Publication of WO2023197088A1 publication Critical patent/WO2023197088A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched

Definitions

  • the present invention relates to a semiconductor element, in particular to a semiconductor element including a field plate and a manufacturing method thereof.
  • III-V compound semiconductors such as gallium nitride (GaN) have material properties of low on-resistance and high breakdown voltage.
  • High electron mobility transistors made of III-V compound semiconductor materials can be used to form various integrated circuit devices, such as high-power field effect transistors or high-frequency transistors.
  • HEMT includes compound semiconductor layers with different energy gaps stacked on each other, such as a high energy gap semiconductor layer and a low energy gap semiconductor layer, to have a heterojunction. This heterojunction with discontinuous energy levels will cause two-dimensional electron gas (2-DEG) to form near the heterojunction, thereby transporting carriers in the HEMT.
  • 2-DEG two-dimensional electron gas
  • HEMT Since HEMT does not use a doped region as the carrier channel of the transistor, but uses 2-DEG as the carrier channel of the transistor, compared with the existing metal oxide semi-field effect transistor (MOSFET), HEMT has many attractive features. Characteristics, such as high electron mobility and the ability to transmit high-frequency signals.
  • a field plate is generally used to control the electric field distribution and/or the size of the electric field peak in the compound semiconductor layer to prevent electrical collapse of the HEMT during operation.
  • the structure of the compound semiconductor layer is often damaged, thereby degrading the electrical properties of the compound semiconductor layer, thereby affecting the electrical performance of the corresponding HEMT.
  • a semiconductor component which includes a substrate, a semiconductor stack, an insulating structure, and an electrode.
  • the semiconductor stack is disposed on the substrate and includes a two-dimensional electron gas region.
  • the insulation structure is disposed on the semiconductor stack and includes a first insulation layer and a second insulation layer.
  • the first insulation layer includes a first opening, and the first opening exposes a first inner wall of the first insulation layer.
  • the second insulating layer is disposed on the first insulating layer and covers the first inner wall of the first insulating layer.
  • the second insulating layer includes a second opening located within the first opening and exposing the second inner wall of the second insulating layer.
  • the second insulation layer includes a stepped profile, and an edge of the stepped profile coincides with the second inner wall.
  • the electrode is disposed on the insulating structure and located in the second opening.
  • a method of manufacturing a semiconductor device including the following steps.
  • a substrate is provided; a semiconductor stack is provided on the substrate, and the semiconductor stack includes a two-dimensional electron gas region; a first insulating layer is provided on the semiconductor stack; the first insulating layer is etched to form a first opening; and a second insulation is provided Layer on the first insulating layer and fill the first opening; etch the second insulating layer to form a second opening, the second opening is located in the first opening; and dispose at least one metal material on the second insulating layer to form electrode.
  • FIG. 1 is a schematic cross-sectional view of a semiconductor element according to an embodiment of the present invention, wherein the semiconductor element includes two insulating layers.
  • FIG. 2 is a schematic cross-sectional view of a partial region of a semiconductor device according to an embodiment of the present invention.
  • FIG 3 is a schematic cross-sectional view of a semiconductor device according to a modified embodiment of the present invention, wherein the semiconductor device includes three insulating layers.
  • FIG. 4 is a schematic cross-sectional view of a semiconductor element according to a modified embodiment of the present invention, in which the electrodes in the semiconductor element penetrate the protective layer.
  • FIG. 5 is a schematic cross-sectional view of a semiconductor element according to a modified embodiment of the present invention, in which the insulating structure in the semiconductor element directly contacts the semiconductor layer.
  • 6 to 9 are schematic cross-sectional views of semiconductor device fabrication according to embodiments of the present invention.
  • FIG. 10 is a schematic cross-sectional view of a semiconductor device fabricated according to a modified embodiment of the present invention.
  • the invention provides several different embodiments for implementing different features of the invention.
  • examples of specific components and arrangements are also described herein. These examples are provided for illustrative purposes only and are not intended to be limiting in any way.
  • the following description of "the first feature is formed on or above the second feature” may mean “the first feature is in direct contact with the second feature” or "the first feature is in direct contact with the second feature”. There are other features between the features", so that the first feature and the second feature are not in direct contact.
  • various embodiments of the present invention may use repeated reference symbols and/or textual notations. These repeated reference symbols and notations are used to make the description more concise and clear, but are not used to indicate the correlation between different embodiments and/or configurations.
  • first, second, third, etc. terms to describe various elements, components, regions, layers and/or sections
  • these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer and/or block from another element, component, region, layer and/or block and do not in themselves mean that the element has any prefix. Ordinal numbers do not represent the arrangement order between one component and another component or the order in the manufacturing method. Therefore, a first element, component, region, layer or block discussed below can also be termed a second element, component, region, layer or block without departing from the scope of the specific embodiments of the invention.
  • III-V semiconductor refers to a compound semiconductor containing at least one Group III element and at least one Group V element.
  • group III elements can be boron (B), aluminum (Al), gallium (Ga) or indium (In), while group V elements can be nitrogen (N), phosphorus (P), arsenic (As) or antimony ( Sb).
  • the "III-V semiconductor” may be a binary compound semiconductor, a ternary compound semiconductor, a quaternary compound semiconductor, a quaternary or higher compound semiconductor, or a combination thereof, but is not limited thereto.
  • the III-V semiconductor may also include dopants and have a specific conductivity type, such as N-type or P-type.
  • the present invention relates to a semiconductor device, such as a high electron mobility transistor (HEMT) including a field plate.
  • a semiconductor device such as a high electron mobility transistor (HEMT) including a field plate.
  • HEMT high electron mobility transistor
  • FIG. 1 is a schematic cross-sectional view of a semiconductor element according to an embodiment of the present invention, wherein the semiconductor element includes two insulating layers.
  • FIG. 2 is a schematic cross-sectional view of a partial region of a semiconductor device according to an embodiment of the present invention.
  • a semiconductor device 100 such as a high electron mobility transistor or other high-voltage power transistor device, includes a substrate 102 , a semiconductor stack 104 , an insulating structure 120 , and an electrode 130 that are stacked in sequence.
  • the semiconductor stack 104 is disposed on the substrate 102 and includes a two-dimensional electron gas region 106 .
  • the insulating structure 120 is disposed on the semiconductor stack 104 , and the insulating structure 120 may be a stacked structure, for example, including a first insulating layer 122 and a second insulating layer 124 .
  • the first insulating layer 122 includes a first opening 150 , and the first opening 150 exposes the first inner sidewall 160 of the first insulating layer 122 .
  • the second insulating layer 124 is disposed on the first insulating layer 122 and covers the first inner side wall 160 of the first insulating layer 122 .
  • the second insulating layer 124 includes a second opening 152 , and the second opening 152 is located in the first opening.
  • the second insulating layer 124 includes a stepped profile 170 , and as shown in FIG. 2 , the edge 172 of the stepped profile overlaps the second inner sidewall 162 of the second insulating layer 124 .
  • the electrode 130 is disposed on the insulation structure 120 and located in the second opening 152 .
  • the second insulating layer 124 in the semiconductor element 100 covers the first inner sidewall 160 of the first insulating layer 122 , and the second insulating layer 124 has a The two openings 152 are disposed in the first opening 150 of the first insulating layer 122. Therefore, when the electrode 130 is disposed on the insulating structure 120, the bottom surface of the electrode 130 will be stepped up in a certain direction, including different Bottom height.
  • the electrodes 130 with bottom surfaces at different heights will generate different electric field intensities to the corresponding semiconductor stacks 104 below, thereby effectively redistributing the electric field distribution in the semiconductor stacks 104, thereby improving the semiconductor The voltage resistance of component 100.
  • the semiconductor device 100 may further include other optional components and layers. Each component and layer in the semiconductor device 100 is further described below.
  • a semiconductor device 100 includes a substrate 102 including a surface S, such as the topmost surface.
  • the substrate 102 may be an epitaxial substrate (eg, a bulk silicon substrate, a silicon carbide (SiC) substrate, an aluminum nitride (AlN) substrate), or a sapphire (sapphire) substrate), a ceramic substrate, or a semiconductor substrate with an insulating layer on it (eg, an insulating layer A silicon on insulator (SOI) substrate or an insulating layer on a germanium on insulator (GOI) substrate), but is not limited to this.
  • SOI silicon on insulator
  • GOI germanium on insulator
  • the thickness of the substrate 102 is 500 ⁇ m to 2 mm, for example, 670 ⁇ m to 1000 ⁇ m, but is not limited thereto.
  • the entirety or surface of the substrate 102 may be electrically insulating, thereby further avoiding unnecessary electrical connections between structures respectively disposed above and below the substrate 102 .
  • the substrate 102 may also be conductive and is not limited to an insulating substrate.
  • the semiconductor stack 104 is disposed on the surface S of the substrate 102 and includes multiple III-V semiconductor layers.
  • the semiconductor stack 104 includes a base layer 108, a buffer layer 110, a high resistance layer 112, a channel layer 114 and a barrier layer 116 in order from bottom to top.
  • the base layer 108 is a III-V semiconductor layer, such as a nitride semiconductor layer such as AlN, which allows the semiconductor layer disposed above the base layer 108 to have better crystallinity.
  • the buffer layer 110 can be used to reduce the degree of stress or lattice mismatch that exists between the substrate 102 and the semiconductor stack 104.
  • the buffer layer 110 can include a plurality of III-V sub-semiconductors, and the plurality of sub-semiconductor layers can constitute a composition.
  • Composition ratio gradient layers or super lattice structure means that the composition ratio of adjacent sub-semiconductor layers will continue to change along a certain direction, such as aluminum gallium nitride (Al x Ga (1-x) N) with a gradient composition ratio, and the composition ratio will change continuously along a certain direction. Moving away from the substrate 102 , the X value decreases from 0.9 to 0.15 in a continuous or stepwise manner.
  • the superlattice structure contains alternately stacked sub-semiconductor layers with slightly different composition ratios.
  • These sub-semiconductor layers are adjacent to each other and appear in pairs (for example, pairs of Al x1 Ga (1-x1) N and Al x2 Ga (1- x2) N, 0.1>X1-X2>0.01), as the smallest repeating unit in the superlattice structure.
  • the high resistance layer 112 will be disposed on the substrate 102, for example, on the buffer layer 110.
  • the high-resistance layer 112 has a higher resistivity than other layers, so leakage current can be avoided between the semiconductor layer disposed on the high-resistance layer 112 and the substrate 102 .
  • the high-resistance layer 112 may be a III-V semiconductor layer with doping, such as carbon-doped gallium nitride (c-GaN), but is not limited thereto.
  • the channel layer 114 will be disposed on the substrate 102, for example, on the high resistance layer 112.
  • the channel layer 114 may include one or more III-V semiconductor layers, and the composition of the III-V semiconductor layer may be GaN, AlGaN, InGaN or InAlGaN, but is not limited thereto.
  • the channel layer 114 is an undoped III-V semiconductor, such as undoped GaN (undoped-GaN, u-GaN).
  • the barrier layer 116 will be disposed on the channel layer 114 .
  • Barrier layer 116 may include one or more III-V semiconductor layers, and its composition may be different from that of the III-V semiconductor of channel layer 114 .
  • the material of the barrier layer 116 may include a material with an energy gap larger than that of the channel layer 114 , such as AlN, Al x Ga (1-x) N (0 ⁇ x ⁇ 1), or a combination thereof.
  • the barrier layer 116 may be an N-type III-V semiconductor, such as an AlGaN layer that is N-type in nature, but is not limited thereto.
  • the arrangement order of the base layer 108, the buffer layer 110 and the high resistance layer 112 in the semiconductor stack 104 can be adjusted without being limited to the above, and at least a part of the plurality of layers can be repeated, omitted or replaced. into other semiconductor layers.
  • Other III-V semiconductor layers may also be included in the semiconductor stack 104 .
  • the channel layer 114 and the barrier layer 116 can be grown as a single crystal on the substrate 102 with few or almost no lattice defects.
  • the protective layer 118 will be disposed on the semiconductor stack 104 and is located between the insulating structure 120 and the semiconductor stack 104. It can be used to eliminate or reduce surface defects existing on the top surface of the barrier layer 116, thereby improving the two-dimensional electrons. electron mobility in the gas region 106.
  • the protective layer 118 can also be used to protect the underlying semiconductor stack 104 to prevent the semiconductor stack 104 from being damaged during the etching process.
  • the conductivity of the protective layer 118 will be lower than that of the barrier layer 116 , and the material of the protective layer 118 is different from the material of the insulating structure 120 , for example, it may be an insulating layer or a III-V semiconductor layer.
  • the insulating layer includes silicon nitride (SiN), and the III-V semiconductor layer includes gallium nitride.
  • the insulation structure 120 will be disposed on the protective layer 118 .
  • the insulation structure 120 includes openings to expose the underlying protective layer 118 .
  • the electrode 130 will fill the opening of the insulating structure 120 and directly contact the protective layer 118 .
  • the second opening 152 of the second insulating layer 124 exposes the underlying protective layer 118, and the electrode 130 fills the second opening 152 and contacts the protective layer 118.
  • the drain electrode 134 and the source electrode 136 will be disposed on both sides of the electrode 130 respectively, and both will be covered by the insulating structure 120.
  • the first insulating layer 122 and the second insulating layer 124 respectively include two openings to expose the underlying surfaces. drain electrode 134 and source electrode 136 .
  • the protective layer 118 includes two openings.
  • the drain electrode 134 and the source electrode 136 are respectively electrically connected to the underlying semiconductor layer, such as the channel layer 114 and/or the barrier layer 116, through the two openings, and generate Ohmic contact.
  • the two openings of the first insulating layer 122 and the two openings of the second insulating layer 124 may be formed in different processes, or formed at one time in the same process.
  • a plurality of interlayer dielectric layers are disposed on the insulating structure 120 .
  • the interlayer dielectric layers may have the same or different compositions, such as SiN, AIN, Al 2 O 3 , SiON or SiO 2 , but are not limited thereto.
  • the first interlayer dielectric layer 126 covers the electrode 130 (including the gate electrode and the field plate), and includes two openings to respectively expose the drain electrode 134 and the source electrode 136 below.
  • At least two bonding pad structures 132 will be disposed on the drain electrode 134 and the source electrode 136 respectively, and respectively pass through the two openings of the first interlayer dielectric layer 126 and the two openings of the second insulating layer 124 Electrically connected to drain electrode 134 and source electrode 136 .
  • the two openings of the second insulating layer 124 and the two openings of the first interlayer dielectric layer 126 may be formed in different processes, or formed at one time in the same process.
  • the second interlayer dielectric layer 128 covers the first interlayer dielectric layer 126 , the sidewalls of the semiconductor stack 104 and the two pad structures 132 .
  • the second interlayer dielectric layer 128 includes two openings, exposing the top surface of the bonding pad structure 132 as an area for electrical connection between the semiconductor device 100 and external components.
  • the semiconductor device 100 may also include another bonding pad structure (not shown) electrically connected to the electrode 130 .
  • FIG. 2 is a schematic cross-sectional view of a partial region of a semiconductor element according to an embodiment of the present invention, for example, an enlarged schematic view of region A in FIG. 1 .
  • the insulation structure 120 includes a first insulation layer 122 and a second insulation layer 124 disposed on the protective layer 118 .
  • the first insulating layer 122 includes a first opening 150 , and the bottom surface of the first opening 150 has a first width W1 .
  • the first opening 150 exposes the first inner sidewall 160 of the first insulating layer 122 .
  • the second insulating layer 124 will be disposed on the surface of the first insulating layer 122 , so that a part of the second insulating layer 124 will be disposed in the first opening 150 , and other parts of the second insulating layer 124 will be disposed in the first opening 150 . disposed outside the first opening 150 .
  • the second insulation layer 124 also includes a third opening 154 disposed above the second opening 152 , and the third opening 154 is disposed above the first opening 150 .
  • the bottom surface of the second opening 152 has a second width W2, and the second opening 152 exposes the second inner sidewall 162 of the second insulating layer 124.
  • the angle ⁇ 2 between the two may also be less than 45 degrees.
  • the bottom surface of the third opening 154 has a third width W3, and the third opening 154 exposes the third inner wall 164 of the second insulating layer 124.
  • ⁇ 3 there will be a third included angle ⁇ 3 between the third inner wall 164 and the surface of the protective layer 118 (or the surface of the substrate), for example, an acute angle of no more than 70 degrees and/or no less than 45 degrees, and according to different requirements, the third angle ⁇ 3 may also be less than 45 degrees.
  • the second inner wall 162 and the third inner wall 164 are arranged sequentially from bottom to top, so that the steps edges 172 and 174 of the stepped profile displayed by the second insulating layer 124 overlap the second inner wall 162 and the third inner wall respectively. 164.
  • the third width W3 of the third opening 154 is between the first width W1 of the first opening 150 and the second width W2 of the second opening 152 .
  • the three angles are all acute angles, respectively 20 degrees-60 degrees, 20 degrees-65 degrees, and 20 degrees-70 degrees, and the first The included angle ⁇ 1 will be less than or equal to the third included angle ⁇ 3, and the second included angle ⁇ 2 will be less than or equal to the third included angle ⁇ 3.
  • the first insulation layer 122 has a first thickness t21, for example, 150 nm to 500 nm, and the second insulation layer 124 has a second thickness t22, for example, 100 nm to 400 nm.
  • the first thickness t21 of the first insulating layer 122 is greater than the second thickness t22 of the second insulating layer 124
  • the first thickness t21 is greater than the thickness t11 of the protective layer 118 .
  • the first insulation layer 122 adjacent to the second opening 152 and located within the first opening 150 will exhibit a first-level thickness T1
  • the first insulation layer 122 and the second insulation layer stacked on each other 124 will show the second-level thickness T2, making the second-level thickness T2 greater than the first-level thickness T1.
  • the electrode 130 will fill the second opening 152 and extend outward from the second opening 152, for example, at least toward the direction of the drain electrode (not shown).
  • the electrode 130 includes a main body 140, a first extension 142 and a second extension 144.
  • the main body part 140 serves as the gate electrode of the semiconductor element 100.
  • a predetermined bias voltage is applied to the main body part 140, the concentration of the two-dimensional electron gas 106 in the channel layer 114 directly below the main body part 140 can be adjusted, thereby making the semiconductor element A current of 100 is turned on or off.
  • the first extension part 142 will be disposed on the second insulation layer 124 , and the bottom surface of the first extension part 142 will be lifted along the direction away from the second opening 152 .
  • the first extension 142 serves as a field plate of the semiconductor device 100 to control the electric field distribution and/or the electric field peak size of the underlying semiconductor stack 104 . Since some of the first extension portions 142 will be closer to the semiconductor stack 104 and other portions of the first extension portions 142 will be farther away from the semiconductor stack 104 , when a predetermined bias voltage is applied to the first extension portion 142 , there will be an impact on the first extension portion 142 .
  • the corresponding semiconductor stack 104 below generates different electric field intensities, which can effectively redistribute the electric field distribution in the semiconductor stack 104, thereby improving the voltage withstand capability of the semiconductor device 100.
  • the second extension portion 144 is disposed on the second insulating layer 124 to ensure that the electrode 130 still fills the second opening 152 even in the case of alignment errors.
  • the first extension portion 142 disposed above the second insulating layer 124 is not only It will generate a longitudinal electric field on the semiconductor stack 104 below, and it can also generate a transverse electric field, so that the electric field distribution in the semiconductor stack 104 can be more effectively controlled, so that the peak electric field is farther away from the bottom edge of the main body 140, thereby preventing the semiconductor Component 100 undergoes electrical collapse.
  • the electrode 130 located in the second opening 152, the protective layer 118 directly below the second opening 152, and the channel layer 114 directly below the second opening 152 form Metal-insulator-semiconductor (MIS) capacitor structure.
  • MIS Metal-insulator-semiconductor
  • the electrode 130 located in the second opening 152 and the protective layer 118 directly below the second opening 152 form a Schottky contact structure. In this case, when the semiconductor device 100 is operated, current cannot easily flow through the electrode 130 due to the energy barrier of the Schottky contact structure, thereby preventing leakage current from being generated.
  • the semiconductor device of the present invention may also have other implementation forms, which are not limited to the above. Variations of the semiconductor element will be further described below. In order to simplify the description, the following description mainly describes the differences between the embodiments in detail, and will not repeat the same details. In addition, various embodiments of the present invention may use repeated reference symbols and/or textual notations. These repeated reference symbols and notations are used to make the description more concise and clear, but are not used to indicate the correlation between different embodiments and/or configurations.
  • FIG. 3 is a schematic cross-sectional view of a semiconductor device according to a modified embodiment of the present invention, wherein the semiconductor device includes three insulating layers.
  • the structure of the semiconductor element 200 of FIG. 3 is similar to the structure of the semiconductor element 100 of FIG. 1 .
  • the main difference between the two is that the insulation structure 120 of the semiconductor element 200 of FIG.
  • it further includes a third insulating layer 180 disposed on the second insulating layer 124 and partially filled in the second opening 152.
  • the third insulation layer 180 has a third thickness t23, and the third thickness t23 may be smaller than the second thickness t22 of the second insulation layer 124.
  • the third insulating layer 180 includes a fourth opening 156 , and the fourth opening 156 exposes the fourth inner sidewall 166 of the third insulating layer 180 .
  • the bottom surface of the fourth opening 156 has a fourth width W4, and the fourth width W4 is smaller than the second width W2 of the second opening 152.
  • the electrode 130 will be disposed on the third insulating layer 180 , so that the bottom surface of the electrode 130 will be stepped up in a direction away from the fourth opening 156 .
  • the insulating structure 120 will have a step-like increasing thickness (for example, the third-level thickness T3, the fourth-level thickness T4, and the fifth-level thickness T5), so that the main body portion 140 of the electrode 130 also has Different heights, and thus the effect of field plates, will allow the electrodes 130 (that is, the electrodes 130 corresponding to the electrodes 130 directly above the third insulating layer 180) to have three levels of unequal heights, which can more effectively control the electric field distribution in the semiconductor stack 104. .
  • a step-like increasing thickness for example, the third-level thickness T3, the fourth-level thickness T4, and the fifth-level thickness T5
  • FIG. 4 is a schematic cross-sectional view of a semiconductor element according to a modified embodiment of the present invention, in which the electrodes in the semiconductor element penetrate the protective layer.
  • the structure of the semiconductor element 300 of FIG. 4 is similar to the structure of the semiconductor element 100 of FIG. 1 .
  • the main difference between the two is that the protective layer 118 of the semiconductor element 300 of FIG. 4 has a fifth opening 158 .
  • the underlying semiconductor stack 104 eg, barrier layer 116
  • the fifth inner sidewall 168 of the protective layer 118 is exposed.
  • the electrode 130 By arranging the fifth opening 158 in the protective layer 118 , the electrode 130 will fill the fifth opening 158 and directly contact the underlying barrier layer 116 , so that a Schottky contact is generated between the electrode 130 and the barrier layer 116 .
  • the main body portion 140 of the electrode 130 also has different heights, thereby functioning as a field plate, allowing the electrode 130 (ie, corresponding to the areas directly above the protective layer 118 and the second insulating layer, respectively).
  • the electrode 130) directly above 124 has three levels of unequal height, which can more effectively control the electric field distribution in the semiconductor stack 104.
  • There is a fifth included angle between the fifth inner wall 168 and the semiconductor stack 104 wherein the fifth included angle is greater than the first included angle, the second included angle, the third included angle or the fourth included angle.
  • FIG. 5 is a schematic cross-sectional view of a semiconductor element according to a modified embodiment of the present invention, in which the insulating structure in the semiconductor element directly contacts the semiconductor layer.
  • the structure of the semiconductor element 400 of FIG. 5 is similar to the structure of the semiconductor element 100 of FIG. 1 .
  • the main difference between the two is that the semiconductor element 400 of FIG. 5 does not have a protective layer 118 , so the insulation structure 120 And electrode 130 may directly contact semiconductor stack 104 .
  • each semiconductor layer in the semiconductor stack 104 will be sequentially formed on the surface S of the substrate 102 through an epitaxial or deposition process.
  • MBE molecular beam epitaxy
  • MOCVD metal-organic chemical vapor deposition
  • HVPE hydride vapor phase epitaxy
  • ALD Atomic layer deposition
  • a protective material layer (protective layer 118 ) is formed on the semiconductor stack 104 , for example, by performing an epitaxial process or a deposition process, and a subsequent etching process to form the protective layer 118 .
  • the protective layer 118 will serve as an etching stop layer.
  • the protective layer 118 can also serve as a passivation layer to protect the underlying semiconductor stack 104 .
  • the material of the protective layer 118 includes nitride (such as silicon nitride (SiN), aluminum nitride (AlN), or gallium nitride (GaN)), oxide (such as aluminum oxide (Al 2 O 3 ) or Silicon oxide (SiO x )), or oxynitride (such as silicon oxynitride (SiON)), but is not limited thereto.
  • nitride such as silicon nitride (SiN), aluminum nitride (AlN), or gallium nitride (GaN)
  • oxide such as aluminum oxide (Al 2 O 3 ) or Silicon oxide (SiO x )
  • oxynitride such as silicon oxynitride (SiON)
  • an etching process will be performed to remove part of the protective material layer (protective layer 118) and part of the semiconductor layer (semiconductor stack 104) to form a raised mesa area (mesa
  • part of the protective material layer (protective layer 118 ) will be etched through to expose the underlying barrier layer 116 , or the barrier layer 116 will be further etched through to expose the channel layer 114 to form an opening of the protective layer 118 .
  • the drain electrode 134 and the source electrode 136 are formed to fill the opening in the protective layer 118 .
  • a suitable heat treatment process such as a heat treatment process with a temperature higher than 300° C., may be performed to allow the drain electrode 134 and the source electrode 136 to create ohmic contact with at least one of the underlying barrier layer 116 and the channel layer 114 .
  • the materials of the drain electrode 134 and the source electrode 136 include metals, alloys or stacked layers thereof. The stacked layers are, for example, Ti/Al, Ti/Al/Ti/TiN, Ti/Al/Ti/Au, Ti/Al/Ni/ Au or Ti/Al/Mo/Au, but not limited to this.
  • first insulating layer 122 a first insulating material layer covering the semiconductor stack 104 and the protective layer 118.
  • the first insulating layer 122 is then formed by a subsequent etching process.
  • the material of the first insulating layer 122 may be different from the material of the protective layer 118.
  • the material of the first insulating layer 122 includes nitride, such as silicon nitride (SiN) or aluminum nitride (AlN), oxide, such as Aluminum oxide (Al 2 O 3 ) or silicon oxide (SiO x ), or oxynitride, such as silicon oxynitride (SiON), but is not limited thereto.
  • nitride such as silicon nitride (SiN) or aluminum nitride (AlN)
  • oxide such as Aluminum oxide (Al 2 O 3 ) or silicon oxide (SiO x )
  • oxynitride such as silicon oxynitride (SiON)
  • the first insulating layer 122 is not limited to a single-layer structure, and may also be a multi-layer stacked structure.
  • photolithography and etching processes are then performed as shown in cross-section 604 in FIG. 7 to form the first opening 150 in the first insulating material layer to form the first insulating layer. 122, the first opening 150 exposes the underlying protective layer 118.
  • the etching process is, for example, a dry etching or wet etching process.
  • the first inner sidewall 160 of the first insulating layer 122 formed by etching will be inclined rather than vertical. Therefore, the first inner sidewall 160 will be in contact with the underlying protective layer 118 (or The surface of the substrate) has a first included angle ⁇ 1, and the first included angle ⁇ 1 is an acute angle.
  • the first insulating layer 122 can be etched to form the inclined first inner sidewall 160 through the lateral etching characteristics of the wet etching process.
  • the protective layer 118 will act as an etching barrier, that is, the etching rate of the protective layer 118 by the etchant will be less than the etching rate of the first insulating layer 122 by the etchant, so that the protective layer 118
  • the etching selection ratio between the first insulating layer 122 and the first insulating layer 122 is less than 1, for example, 0.95, 0.65, 0.35, 0.05, 0.01, 0.005 or any value therein.
  • buffered oxide etch may be used to perform the first The first opening 150 is formed in the insulating layer 122 without forming an opening or depression in the protective layer 118 .
  • a deposition process such as a vapor deposition process, is performed to form a second insulating material layer that covers the first insulating layer 122 , and a subsequent etching process is used to form the second insulating layer 124 .
  • the second insulating layer 124 will have a third inner sidewall 164 adjacent to the first inner sidewall 160 of the first insulating layer 122 .
  • the materials of the second insulating layer 122 and the first insulating layer 122 may be the same or different, and the material of the second insulating layer 124 may be different from the material of the protective layer 118 .
  • the material of the second insulating layer 124 includes nitride, such as silicon nitride (SiN) or aluminum nitride (AlN), oxide, such as aluminum oxide (Al 2 O 3 ) or silicon oxide (SiO x ), Or oxynitride, such as silicon oxynitride (SiON), but is not limited thereto.
  • the second insulating layer 124 is not limited to a single-layer structure, and may also be a multi-layer stacked structure.
  • a photolithography and etching process is performed to form a second opening 152 in the second insulating material layer, thereby exposing the underlying protective layer 118 , thereby completing the process of the second insulating material layer.
  • the second opening 152 will be disposed in the first opening 150 , and the second width W2 of the second opening 152 will be smaller than the first width W1 of the first opening 150 .
  • the etching process is, for example, dry etching or wet etching.
  • the etching method for forming the second opening 152 of the second insulating layer 124 may be the same as or different from the etching method for the first opening 150 of the first insulating layer 122 .
  • the second inner sidewall 162 of the second insulating layer 124 will be inclined rather than vertical, so the second inner sidewall 162 will be in contact with the protective layer 118 below. (or the surface of the substrate) has a second included angle ⁇ 2, where the second included angle ⁇ 2 is an acute angle.
  • the protective layer 118 will act as an etching barrier, that is, the etching rate of the protective layer 118 by the etchant will be less than the etching rate of the second insulating layer 124 by the etchant, so that the protective layer 118
  • the etching selection ratio between the second insulating layer 124 and the second insulating layer 124 is less than 1, for example, 0.95, 0.65, 0.35, 0.05, 0.01, 0.005 or any value therein.
  • buffered oxide etching may be used to form a second insulating layer 124 in the second insulating layer 124 . Opening 152 without forming an opening or depression in the protective layer 118 .
  • the second insulating layer 124 will exhibit a stepped profile 170 , and the edges 172 and 174 of the stepped profile 170 will respectively overlap the second inner sidewall 162 and the second insulating layer 124 .
  • the third inner wall 164 is
  • At least one metal material is disposed on the second insulating layer 124 , and a suitable patterning process is performed to form the electrode 130 .
  • the electrode 130 will fill the second opening 152 of the second insulating layer 124 .
  • the electrode 130 extends outward from the second opening 152 and has an asymmetric cross-sectional structure.
  • the material of the electrode 130 may include metal, alloy, semiconductor material, or stacked layers thereof.
  • the electrode 130 may include gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum ( Al), copper (Cu), molybdenum (Mo) and other suitable conductive materials or combinations of the above. Subsequently, photolithography and etching processes will be performed to remove each layer in a specific area and expose part of the surface of the substrate 102 .
  • At least two interlayer dielectric layers and at least two bonding pad structures can be formed on the electrode 130 and the second insulating layer 124, so that the bonding pad structures are electrically connected to the underlying structures.
  • the drain electrode 134 and the source electrode 136 are connected to obtain the semiconductor device 100 as shown in FIG. 1 .
  • FIG. 10 is a schematic cross-sectional view of a semiconductor device fabricated according to a modified embodiment of the present invention. As shown in cross-section 702 of FIG. 10 , the process of FIG. 10 is similar to the process of FIG. 8 . The main difference is that after forming the second opening 152 of the second insulating layer 124 , photolithography and etching processes are further performed to form the second opening 152 of the second insulating layer 124 . A fifth opening 158 is formed in the protective layer 118 to expose the underlying semiconductor stack 104 and the fifth inner sidewall 168 . The bottom surface of the fifth opening 158 has a fifth width W5, and the fifth width W5 is smaller than the second width W2 of the second insulation layer 124.

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Abstract

本发明公开一种半导体元件及其制作方法，其中半导体元件包含基板、半导体叠层、绝缘结构以及电极。半导体叠层设置于基板之上，且包含二维电子气区域。绝缘结构设置于半导体叠层之上，且包含第一绝缘层和第二绝缘层。第一绝缘层包含第一开口，第一开口暴露出第一绝缘层的第一内侧壁。第二绝缘层设置于第一绝缘层之上，且覆盖住第一绝缘层的第一内侧壁。第二绝缘层包含第二开口，位于第一开口内且暴露出第二绝缘层的第二内侧壁。第二绝缘层包含阶梯轮廓，且阶梯轮廓的梯缘重合第二内侧壁。电极设置于绝缘结构之上，且位于第二开口内。

Description

半导体元件及其制作方法 技术领域
本发明有关于一种半导体元件，特别是一种包含场板的半导体元件及其制作方法。
背景技术
在半导体技术中，III-V族的化合物半导体，例如氮化镓(GaN)，具备低导通电阻和高崩溃电压的材料特性，利用III-V族的化合物半导体材料制作的高电子迁移率晶体管(high electron mobility transistor，HEMT)，可用于形成各种集成电路装置，例如：高功率场效晶体管或高频晶体管。HEMT包括彼此堆叠的能隙不同的化合物半导体层，例如高能隙半导体层和低能隙半导体层，而具有异质接面。此能阶不连续的异质接面会使得二维电子气(two dimensional electron gas，2-DEG)形成于异质接面的附近，而得以传输HEMT中的载子。由于HEMT并非使用掺杂区域作为晶体管的载子通道，而是使用2-DEG作为晶体管的载子通道，因此相较于现有的金氧半场效晶体管(MOSFET)，HEMT具有多种吸引人的特性，例如：高电子迁移率及以传输高频信号的能力。
对于现有的HEMT，一般会使用场板(field plate)以调控化合物半导体层中的电场分布及/或电场波峰大小，以避免HEMT在操作时产生电性崩溃。然而，在制作场板的过程中，常会破坏化合物半导体层的结构，而劣化化合物半导体层的电性，进而影响了对应的HEMT的电性表现。
发明内容
有鉴于此，有必要提出一种改良的半导体元件，以改善现有半导体元件所存在的缺失。
根据本发明的一些实施例，提供一种半导体元件，其包含基板、半导体叠层、绝缘结构以及电极。半导体叠层设置于基板之上，且包含二维电子气区域。绝缘结构设置于半导体叠层之上，且包含第一绝缘层和第二绝缘层。第一绝缘层包含第一开口，第一开口暴露出第一绝缘层的第一内侧壁。第二绝缘层设置于第一绝缘层之上，且覆盖住第一绝缘层的第一内侧壁。第二绝缘层包含第二开口，位于第一开口 内且暴露出第二绝缘层的第二内侧壁。第二绝缘层包含阶梯轮廓，且阶梯轮廓的梯缘重合第二内侧壁。电极设置于绝缘结构之上，且位于第二开口内。
根据本发明的一些实施例，提供一种制作半导体元件的方法，包含下述步骤。提供基板；设置半导体叠层于基板之上，且半导体叠层包含二维电子气区域；设置第一绝缘层于半导体叠层之上；蚀刻第一绝缘层以形成第一开口；设置第二绝缘层于第一绝缘层上，并填入第一开口；蚀刻第二绝缘层以形成一第二开口，第二开口位于第一开口中；以及设置至少一金属材料于第二绝缘层上以形成电极。
为了对本发明的上述及其他方面有更佳的了解，下文特举实施例，并配合所附图式详细说明如下。
附图说明
为了使下文更容易被理解，在阅读本发明时可同时参考图式及其详细文字说明。通过本文中的具体实施例并参考相对应的图式，以详细解说本发明的具体实施例，并用以阐述本发明的具体实施例的作用原理。此外，为了清楚起见，图式中的各特征可能未按照实际的比例绘制，因此某些图式中的部分特征的尺寸可能被刻意放大或缩小。
图1是本发明实施例的半导体元件的剖面示意图，其中半导体元件包含两层绝缘层。
图2是本发明实施例的半导体元件的局部区域的剖面示意图。
图3是本发明变化型实施例的半导体元件的剖面示意图，其中半导体元件包含三层绝缘层。
图4是本发明变化型实施例的半导体元件的剖面示意图，其中半导体元件中的电极贯穿保护层。
图5是本发明变化型实施例的半导体元件的剖面示意图，其中半导体元件中的绝缘结构直接接触半导体层。
图6至图9是本发明实施例的制作半导体元件的剖面示意图。
图10是本发明变化型实施例的制作半导体元件的剖面示意图。
附图标记说明：100-半导体元件；200-半导体元件；300-半导体元件；400-半导体元件；102-基板；104-半导体叠层；106-二维电子气区域；108-基层；110-缓冲层；112-高电阻层；114-通道层；116-阻障层；118-保护层；120-绝缘结构；122-第一绝缘层；124-第二绝缘层；126-第一层间介电层；128-第二层间介电层；130-电极；132- 焊垫结构；134-汲极电极；136-源极电极；140-主体部；142-第一延伸部；144-第二延伸部；150-第一开口；152-第二开口；154-第三开口；156-第四开口；158-第五开口；160-第一内侧壁；162-第二内侧壁；164-第三内侧壁；166-第四内侧壁；168-第五内侧壁；170-阶梯轮廓；172-梯缘；174-梯缘；180-第三绝缘层；602-剖面图；604-剖面图；606-剖面图；608-剖面图；702-剖面图；A-区域；S-表面；t11-厚度；t21-第一厚度；t22-第二厚度；t23-第三厚度；T1-第一阶厚度；T2-第二阶厚度；T3-第三阶厚度；T4-第四阶厚度；T5-第五阶厚度；W1-第一宽度；W2-第二宽度；W3-第三宽度；W4-第四宽度；W5-第五宽度；θ1-第一夹角；θ2-第二夹角；θ3-第三夹角。
具体实施方式
本发明提供了数个不同的实施例，可用于实现本发明的不同特征。为简化说明起见，本发明也同时描述了特定构件与布置的范例。提供这些实施例的目的仅在于示意，而非予以任何限制。举例而言，下文中针对“第一特征形成在第二特征上或上方”的叙述，其可以是指“第一特征与第二特征直接接触”，也可以是指“第一特征与第二特征间另存在有其他特征”，致使第一特征与第二特征并不直接接触。此外，本发明中的各种实施例可能使用重复的参考符号和/或文字注记。使用这些重复的参考符号与注记是为了使叙述更简洁和明确，而非用以指示不同的实施例及/或配置之间的关联性。
另外，针对本发明中所提及的空间相关的叙述词汇，例如：“在…之下”，“低”，“下”，“上方”，“之上”，“下”，“顶”，“底”和类似词汇时，为便于叙述，其用法均在于描述图式中一个元件或特征与另一个元件或特征的相对关系。除了图式中所显示的摆向外，这些空间相关词汇也用来描述半导体元件在使用中以及操作时的可能摆向。随着半导体元件的摆向的不同(旋转90度或其它方位)，用以描述其摆向的空间相关叙述亦应通过类似的方式予以解释。
虽然本发明使用第一、第二、第三等用语以叙述各种元件、部件、区域、层及/或区块(section)，但应了解这些元件、部件、区域、层及/或区块不应被该些用语所限制。该些用语仅是用以区分某一元件、部件、区域、层及/或区块与另一个元件、部件、区域、层及/或区块，其本身并不代表该元件有任何前置的序数，也不代表某一元件与另一元件之间的排列顺序或是制造方法上的顺序。因此，在不背离本发明的具体实施例的范畴下，下列所论述的第一元件、部件、区域、层或区块亦可以第 二元件、部件、区域、层或区块的用语称之。
本发明中所提及的“约”或“实质上”的用语通常表示在一给定值或范围的20％之内，较佳是10％之内，且更佳是5％之内，或3％之内，或2％之内，或1％之内，或0.5％之内。应注意的是，说明书中所提供的数量为大约的数量，亦即在没有特定说明“约”或“实质上”的情况下，仍可隐含“约”或“实质上”的含义。
在本发明中，“III-V族半导体”指包含至少一III族元素与至少一V族元素的化合物半导体。其中，III族元素可以是硼(B)、铝(Al)、镓(Ga)或铟(In)，而V族元素可以是氮(N)、磷(P)、砷(As)或锑(Sb)。进一步而言，“III-V族半导体”可以是二元化合物半导体、三元化合物半导体、四元化合物半导体、四元以上的化合物半导体或上述组合，但不限定于此，例如是氮化铝(AlN)、氮化镓(GaN)、磷化铟(InP)、砷化铝(AlAs)、砷化镓(GaAs)等二元化合物半导体；氮化铝镓(AlGaN)、氮化铟镓(InGaN)、磷化镓铟(GaInP)、砷化铝镓(AlGaAs)、砷化铝铟(InAlAs)、砷化镓铟(InGaAs)等三元半导体化合物；或氮化铟铝镓(InAlGaN)或其他的四元化合物半导体。端视需求，III-V族半导体亦可包括掺质，而具有特定导电型，例如N型或P型。
虽然下文通过具体实施例以描述本发明，然而本发明的发明原理亦可应用至其他的实施例。此外，为了不致使本发明的精神晦涩难懂，特定的细节会被予以省略，该些被省略的细节属于所属技术领域中具有通常知识者的知识范围。
本发明有关于一种半导体元件，例如是一种包含场板(field plate)的高电子迁移率晶体管(HEMT)。
图1是本发明实施例的半导体元件的剖面示意图，其中半导体元件包含两层绝缘层。图2是本发明实施例的半导体元件的局部区域的剖面示意图。如图1所示，半导体元件100，例如是高电子迁移率晶体管或是其他高压功率晶体管元件，包含依序堆叠的基板102、半导体叠层104、绝缘结构120、及电极130。半导体叠层104设置于基板上102，且包含二维电子气区域106。绝缘结构120设置在半导体叠层104之上，且绝缘结构120可以是堆叠结构，例如包含第一绝缘层122及第二绝缘层124。如图2所示，图2是图1的局部区域A的放大示意图，第一绝缘层122包含第一开口150，第一开口150暴露出第一绝缘层122的第一内侧壁160。第二绝缘层124设置在第一绝缘层122之上，且覆盖住第一绝缘层122的第一内侧壁160，其中第二绝缘层124包含第二开口152，第二开口152位于第一开口150内且暴露出第二绝缘层124的第二内侧壁162。如图1所示，第二绝缘层124包含阶梯轮廓170，且如图2所示，阶梯轮廓的梯缘172重合第二绝缘层124的第二内侧壁162。 电极130设置于绝缘结构120之上且位于第二开口152内。
如图1和图2所示，根据本发明的一些实施例，由于半导体元件100中的第二绝缘层124覆盖住第一绝缘层122的第一内侧壁160，且第二绝缘层124的第二开口152设置于第一绝缘层122的第一开口150内，因此当电极130设置于绝缘结构120之上时，会使得电极130的底面沿着某一方向被阶梯状抬升，而包含不同的底面高度。当施加预定的偏压至电极130时，底面位于不同高度的电极130会对下方对应的半导体叠层104产生不同的电场强度，因而能有效重新分布半导体叠层104中的电场分布，进而提升半导体元件100的耐压能力。
除了上述的各部件及层之外，半导体元件100可进一步包含其他选择性的部件和层。以下就半导体元件100中的各部件及层进一步描述。
参照图1，半导体元件100包含基板102，基板102包含表面S，例如是最顶表面。基板102可以是磊晶基板(例如块硅基板、碳化硅(SiC)基板、氮化铝(AlN)基板)、或蓝宝石(sapphire)基板)、陶瓷基板或绝缘层上覆半导体基板(例如绝缘层上覆硅(silicon on insulator，SOI)基板或绝缘层上覆锗(germanium on insulator，GOI)基板)，但不限定于此。基板102的厚度为500μm至2mm，例如为670μm至1000μm，但不限定于此。根据本发明一些实施例，基板102的整体或是表面可具有电绝缘性，因而得以进一步避免分别设置于基板102之上和之下的结构产生不必要的电连接。然而，根据本发明一些实施例，基板102亦可以具有导电性，而不局限于绝缘基板。
半导体叠层104会设置于基板102的表面S之上，且包含多层的III-V族半导体层。举例而言，半导体叠层104由下至上依序包含基层108、缓冲层110、高电阻层112、通道层114及阻障层116。基层108是III-V族半导体层，例如AlN等氮化物半导体层，其可让设置于基层108上方的半导体层具有较佳的结晶性。缓冲层110可以用于降低存在于基板102和半导体叠层104之间的应力或晶格不匹配的程度，缓冲层110可包括复数个III-V族子半导体，该复数个子半导体层可以构成组成比例渐变层(composition ratio gradient layers)或是超晶格结构(supper lattice structure)。其中，组成渐变层是指彼此相邻的子半导体层的组成比例会沿着某一方向持续变化，例如是组成比例渐变的氮化铝镓(Al xGa (1-x)N)，且沿着远离基板102的方向，所述X值会以连续或阶梯变化方式自0.9降低至0.15。超晶格结构包含组成比例略有差异且交替堆叠的子半导体层，这些子半导体层彼此相邻且成对出现(例如成对的Al x1Ga (1-x1)N及Al x2Ga (1-x2)N，0.1＞X1-X2＞0.01)，以作为超晶格结构中的最小重复单元。
高电阻层112会被设置于基板102之上，例如是被设置于缓冲层110之上。高电阻层112相较于其他的层具有较高的电阻率，因此可避免设置于高电阻层112上的半导体层和基板102间产生漏电流。举例而言，高电阻层112可以是具有掺质的III-V半导体层，例如碳掺杂氮化镓(c-GaN)，但不限定于此。
通道层114会被设置于基板102之上，例如是被设置于高电阻层112之上。通道层114可包含一层或多层III-V族半导体层，且III-V族半导体层的成份可以是GaN、AlGaN、InGaN或InAlGaN，但不限定于此。举例而言，通道层114为未掺杂的III-V族半导体，例如是未掺杂的GaN(undoped-GaN，u-GaN)。
阻障层116会被设置于通道层114上。阻障层116可包含一层或多层III-V族半导体层，且其组成会不同于通道层114的III-V族半导体。举例来说，阻障层116的材料可包含能隙大于通道层114的材料能隙，例如AlN、Al xGa (1-x)N(0＜x＜1)或其组合。根据一实施例，阻障层116可以是N型III-V族半导体，例如是本质上为N型的AlGaN层，但不限定于此。
由于通道层114和阻障层116间具有不连续的能隙，通过将通道层114和阻障层116互相堆叠设置，于通道层114中靠近其和阻障层116的异质接面形成一位能井，电子会因压电效应(piezoelectric effect)而被聚集于位能井，因而产生高电子迁移率的薄层，亦即二维电子气(2-DEG)区域106。
根据不同的需求，半导体叠层104内的基层108、缓冲层110及高电阻层112的排列顺序可以被予以调整而不限于上述，且该复数个层的至少一部分可以被予以重复、省略或置换成其他半导体层。半导体叠层104内亦可包含其他的III-V族半导体层。以此，以使得通道层114和阻障层116可以单晶成长于基板102之上，而仅具有较少或几乎不存在晶格缺陷。
保护层118会被设置于半导体叠层104之上，且位于绝缘结构120与半导体叠层104之间，其可用于消除或减少存在于阻障层116顶面的表面缺陷，进而提升二维电子气区域106的电子迁移率。保护层118亦可用于保护下方的半导体叠层104，以避免半导体叠层104在蚀刻过程中被损伤。保护层118的导电率会低于阻障层116的导电率，且保护层118的材料与绝缘结构120的材料不同，例如可以是绝缘层或III-V族半导体层。其中，绝缘层包含氮化硅(SiN)，III-V族半导体层包含氮化镓。
绝缘结构120会被设置于保护层118之上。绝缘结构120中包含开口，以暴露出下方的保护层118。电极130会填入绝缘结构120的开口中，而直接接触保护层118。根据本发明的一些实施例，第二绝缘层124的第二开口152暴露出下方的保 护层118，电极130填入第二开口152中，并接触保护层118。汲极电极134及源极电极136会分别设置于电极130的两侧，并且均被绝缘结构120覆盖，其中，第一绝缘层122及第二绝缘层124分别包含两个开口以分别暴露出下方的汲极电极134及源极电极136。于一些实施例中，保护层118包含两个开口，汲极电极134及源极电极136会分别经由两个开口电连接下方的半导体层，例如通道层114及/或阻障层116，并产生欧姆接触(ohmic contact)。第一绝缘层122的两开口及第二绝缘层124的两开口可于不同制程下形成，或于同一制程下一次形成。
多个层间介电层，例如第一层间介电层126及第二层间介电层128，会被设置于绝缘结构120之上。层间介电层彼此间可以具有相同或不同的组成，例如是SiN、AlN、Al 2O 3、SiON或SiO 2，但不限定于此。第一层间介电层126会覆盖住电极130(包含闸极电极和场板)，且其中包含两开口以分别暴露出下方的汲极电极134及源极电极136。至少两个焊垫结构132会分别被设置于汲极电极134及源极电极136之上，且分别经由第一层间介电层126的两个开口，以及第二绝缘层124的两个开口电连接至汲极电极134及源极电极136。第二绝缘层124的两个开口与第一层间介电层126的两个开口可于不同制程下形成，或于同一制程下一次形成。第二层间介电层128会覆盖住第一层间介电层126、半导体叠层104的侧壁及两个焊垫结构132。第二层间介电层128包含两个开口，暴露出焊垫结构132的顶面，以作为半导体元件100和外部元件产生电连接的区域。半导体元件100亦可以包含另一焊垫结构(图未示)，电连接至电极130。
下文就图1的区域A内的各部件进一步予以描述。图2是本发明实施例的半导体元件局部区域的剖面示意图，例如是图1的区域A的放大示意图。如图2所示，绝缘结构120包含设置于保护层118之上的第一绝缘层122及第二绝缘层124。第一绝缘层122中包含第一开口150，且第一开口150的底面具有第一宽度W1。第一开口150会暴露出第一绝缘层122的第一内侧壁160。第一内侧壁160和保护层118的表面(或是基板的表面)之间会具有第一夹角θ1，例如是不大于70度的锐角。
第二绝缘层124会顺向性的设置于第一绝缘层122的表面，使得第二绝缘层124的一部分会被设置于第一开口150内，而第二绝缘层124的其他部分则会被设置于第一开口150之外。第二绝缘层124除了包含第二开口152之外，还会包含设置于第二开口152之上的第三开口154，且第三开口154会被设置于第一开口150之上。第二开口152的底面具有第二宽度W2，且第二开口152会暴露出第二绝缘层124的第二内侧壁162。第二内侧壁162和保护层118的表面(或是基板的表面)之间会具 有第二夹角θ2，例如是不大于70度及/或不小于45度的锐角，且根据不同需求，第二夹角θ2亦可能小于45度。第三开口154的底面具有第三宽度W3，第三开口154会暴露出第二绝缘层124的第三内侧壁164。第三内侧壁164和保护层118的表面(或是基板的表面)之间会具有第三夹角θ3，例如是不大于70度及/或不小于45度的锐角，且根据不同需求，第三夹角θ3亦可能小于45度。第二内侧壁162及第三内侧壁164会由下往上依序设置，使得第二绝缘层124展现出的阶梯轮廓的梯缘172、174会分别重合第二内侧壁162及第三内侧壁164。此外，第三开口154的第三宽度W3会介于该第一开口150的第一宽度W1及第二开口152的第二宽度W2之间。
针对第一夹角θ1、第二夹角θ2、第三夹角θ3，三者的角度均为锐角，分别为20度-60度、20度-65度、20度-70度，且第一夹角θ1会小于或等于第三夹角θ3，第二夹角θ2会小于或等于第三夹角θ3。
第一绝缘层122具有第一厚度t21，例如为150nm至500nm，而第二绝缘层124具有第二厚度t22，例如为100nm至400nm。第一绝缘层122的第一厚度t21大于第二绝缘层124的第二厚度t22，且第一厚度t21大于保护层118的厚度t11。就绝缘结构120的整体而言，邻接第二开口152且位于第一开口150内的第一绝缘层122会展现出第一阶厚度T1，而相互堆叠的第一绝缘层122及第二绝缘层124则会展现出第二阶厚度T2，使得第二阶厚度T2大于第一阶厚度T1。
电极130会填入第二开口152，且自第二开口152向外延伸，例如是至少往汲极电极(图未示)的方向延伸。电极130会包含主体部140、第一延伸部142及第二延伸部144。主体部140作为半导体元件100的闸极电极，当对主体部140施予预定的偏压时，便可调控主体部140正下方通道层114中的二维电子气106的浓度，进而使得半导体元件100的电流导通或截止。第一延伸部142会被设置于第二绝缘层124之上，且沿着远离第二开口152的方向，第一延伸部142的底面会被抬升。第一延伸部142作为半导体元件100的场板，以调控下方的半导体叠层104的电场分布及/或电场峰值大小。由于部分的第一延伸部142会较靠近半导体叠层104，而其他部分的第一延伸部142会较远离半导体叠层104，因此当施加预定的偏压至第一延伸部142时，会对下方对应的半导体叠层104产生不同的电场强度，因而能有效重新分布半导体叠层104中的电场分布，进而提升半导体元件100的耐压能力。第二延伸部144会被设置于第二绝缘层124之上，其用于确保即使在对位误差的情况下，电极130仍会填满第二开口152。
针对绝缘结构120中的第二绝缘层124，由于第二绝缘层124的第二夹角θ2及第三夹角θ3均为锐角，因此设置于第二绝缘层124上方的第一延伸部142不仅会对下方的半导体叠层104产生纵向的电场，还可以产生横向的电场，因而能更有效的调控半导体叠层104中的电场分布，使得峰值电场较远离主体部140的底缘，进而避免半导体元件100产生电性崩溃。
根据本发明的一些实施例，当保护层118为绝缘层时，位于第二开口152内的电极130、第二开口152正下方的保护层118及第二开口152正下方的通道层114会构成金属-绝缘层-半导体层(metal-insulator-semiconductor，MIS)的电容结构。在此情况下，在操作半导体元件100时，电流可以受到保护层118的阻挡，而不会在电极130及通道层114之间流通，避免漏电流产生。根据本发明的一些实施例，当保护层118为半导体层时，位于第二开口152内的电极130及第二开口152正下方的保护层118会构成萧基接触结构。在此情况下，在操作半导体元件100时，电流因萧基接触结构的能障，便不易流经电极130，避免漏电流产生。
除了上述实施例之外，本发明的半导体元件亦可能有其它的实施态样，而不限于前述。下文将进一步针对半导体元件的变化型进行说明。为简化说明，以下说明主要针对各实施例不同之处进行详述，而不再对相同之处作重复赘述。此外，本发明中的各种实施例可能使用重复的参考符号和/或文字注记。使用这些重复的参考符号与注记是为了使叙述更简洁和明确，而非用以指示不同的实施例及/或配置之间的关联性。
图3是本发明变化型实施例的半导体元件的剖面示意图，其中半导体元件包含三层绝缘层。如图3所示，图3的半导体元件200的结构类似于图1的半导体元件100的结构，两者之间的主要差异在于，图3的半导体元件200中的绝缘结构120除了包含第一绝缘层122及第二绝缘层124之外，还进一步包含顺向性设置于第二绝缘层124之上的第三绝缘层180，并部分填入于第二开口152中。第三绝缘层180具有第三厚度t23，此第三厚度t23可小于第二绝缘层124的第二厚度t22。第三绝缘层180包含第四开口156，且第四开口156会暴露出第三绝缘层180的第四内侧壁166。第四开口156的底面具有第四宽度W4，此第四宽度W4小于第二开口152的第二宽度W2。电极130会被设置于第三绝缘层180之上，使得电极130的底面会沿着远离第四开口156的方向而被阶梯状抬升。通过设置第三绝缘层180，会使得绝缘结构120具有阶梯状增加的厚度(例如第三阶厚度T3、第四阶厚度T4、第五阶厚度T5)，而使得电极130的主体部140也具有不同高度，进而有场板的功效， 会让电极130(即对应至第三绝缘层180正上方的电极130)具有三阶的不等高度，而更能有效调控半导体叠层104中的电场分布。
图4是本发明变化型实施例的半导体元件的剖面示意图，其中半导体元件中的电极贯穿保护层。如图4所示，图4的半导体元件300的结构类似于图1的半导体元件100的结构，两者之间的主要差异在于，图4的半导体元件300的保护层118具有第五开口158，而暴露出下方的半导体叠层104(例如阻障层116)，并暴露出保护层118的第五内侧壁168。通过在保护层118中设置第五开口158，电极130会填入第五开口158，并直接接触下方的阻障层116，使得电极130和阻障层116之间产生萧基接触。通过在保护层118中设置第五开口158，使得电极130的主体部140也具有不同高度，进而有场板的功效，会让电极130(即分别对应至保护层118正上方和第二绝缘层124正上方的电极130)具有三阶的不等高度，而更能有效调控半导体叠层104中的电场分布。第五内侧壁168与半导体叠层104之间具有一第五夹角，其中第五夹角大于第一夹角、第二夹角、第三夹角或第四夹角。
图5是本发明变化型实施例的半导体元件的剖面示意图，其中半导体元件中的绝缘结构直接接触半导体层。如图5所示，图5的半导体元件400的结构类似于图1的半导体元件100的结构，两者之间的主要差异在于，图5的半导体元件400未设置保护层118，因此绝缘结构120及电极130会直接接触半导体叠层104。
为了使本技术领域中具有通常知识者可据以实现本发明，以下进一步具体描述本发明的半导体元件的制作方法。
图6至图9是本发明实施例的制作半导体元件的剖面示意图。如图6所示的剖面602，在此制程阶段，半导体叠层104中的各半导体层会经由磊晶或沉积制程而被依序形成于基板102的表面S之上。举例而言，可通过施行分子束磊晶(molecular-beam epitaxy，MBE)、有机金属化学气相沉积(metal-organic chemical vapor deposition，MOCVD)、氢化物气相磊晶(hydride vapor phase epitaxy，HVPE)、原子层沉积(atomic layer deposition，ALD)或其他合适的方式，以形成半导体叠层104中的各半导体层。在形成半导体叠层104之后，会形成一保护材料层(保护层118)于半导体叠层104之上，例如通过施行磊晶制程或沉积制程，再搭配后续蚀刻制程后形成保护层118。在后续的蚀刻制程中，保护层118会作为蚀刻停止层。此外，保护层118亦可作为钝化层，以保护下方的半导体叠层104。举例而言，保护层118的材料包括氮化物(例如氮化硅(SiN)、氮化铝(AlN)、或氮化镓(GaN))、氧化物(例如氧化铝(Al 2O 3)或氧化硅(SiO x))、或氮氧化物(例如氮氧化硅(SiON))，但不限定于此。接 着，会施行蚀刻制程，以移除部分的保护材料层(保护层118)及部分的半导体层(半导体叠层104)，以形成凸出的平台区(mesa)，此平台区会被用以容纳半导体元件的电极，例如闸极、源极及汲极。后续会蚀穿保护材料层(保护层118)的部分区域，以暴露出下方的阻障层116，或进一步蚀穿阻障层116，以暴露出通道层114，形成保护层118的开口。
继以形成汲极电极134及源极电极136，以填入保护层118中的开口。此外，可施行合适的热处理制程，例如是温度高于300℃的热处理制程，以让汲极电极134及源极电极136和下方的阻障层116及通道层114的至少其中之一产生欧姆接触。汲极电极134及源极电极136的材料包括金属、合金或其堆叠层，堆叠层例如是Ti/Al、Ti/Al/Ti/TiN、Ti/Al/Ti/Au、Ti/Al/Ni/Au或Ti/Al/Mo/Au，但不限定于此。
接着，施行沉积制程，例如气相沉积制程，以形成覆盖半导体叠层104及保护层118的第一绝缘材料层(第一绝缘层122)，再搭配后续蚀刻制程后形成第一绝缘层122。第一绝缘层122的材料会不同于保护层118的材料，举例而言，第一绝缘层122的材料包含氮化物，例如氮化硅(SiN)或氮化铝(AlN)，氧化物，例如氧化铝(Al 2O 3)或氧化硅(SiO x)，或氮氧化物，例如氮氧化硅(SiON)，但不限定于此。此外，第一绝缘层122不限于是单层结构，其亦可以是多层堆叠结构。
在完成如图6所示的制程阶段后，接着如图7所示的剖面604所示，施行光微影及蚀刻制程，于第一绝缘材料层中形成第一开口150以形成第一绝缘层122，第一开口150暴露出下方的保护层118。蚀刻制程例如是干蚀刻或湿蚀刻制程，蚀刻形成的第一绝缘层122的第一内侧壁160会呈现倾斜状而非垂直状，因而第一内侧壁160会和下方的保护层118(或是基板的表面)具有第一夹角θ1，第一夹角θ1为锐角。于本发明的一些实施例中，可通过湿蚀刻制程的侧向蚀刻特性，蚀刻第一绝缘层122形成倾斜的第一内侧壁160。此外，在选定的湿蚀刻条件下，保护层118会作为蚀刻阻挡层，亦即蚀刻剂对于保护层118的蚀刻速率会小于蚀刻剂对于第一绝缘层122的蚀刻速率，而使得保护层118和第一绝缘层122之间的蚀刻选择比值小于1，例如为0.95、0.65、0.35、0.05、0.01、0.005或其中的任何数值。根据本发明的一些实施例，当第一绝缘层122的材料为氧化硅，且保护层118的材料为氮化硅时，可以采用缓冲氧化物蚀刻(buffered oxide etch，BOE)，以于第一绝缘层122中形成第一开口150，且不会在保护层118中形成开口或是凹陷。
接着如图8的剖面606所示，施行沉积制程，例如气相沉积制程，以形成顺向性覆盖第一绝缘层122的第二绝缘材料层，再搭配后续蚀刻制程以形成第二绝缘层 124。第二绝缘层124会具有第三内侧壁164，邻近于第一绝缘层122的第一内侧壁160。第三内侧壁164和保护层118的表面(或是基板的表面)的间会具有第三夹角θ3，且第三夹角θ3是锐角。第二绝缘层122及第一绝缘层122的材料可以相同或相异，且第二绝缘层124的材料会不同于保护层118的材料。举例而言，第二绝缘层124的材料包含氮化物，例如氮化硅(SiN)或氮化铝(AlN)，氧化物，例如氧化铝(Al 2O 3)或氧化硅(SiO x)，或氮氧化物，例如氮氧化硅(SiON)，但不限定于此。此外，第二绝缘层124不限于是单层结构，其亦可以是多层堆叠结构。
接着，施行光微影及蚀刻制程，于第二绝缘材料层中形成第二开口152，而暴露出下方的保护层118，完成第二绝缘材料层的制程。第二开口152会被设置于第一开口150之中，且第二开口152的第二宽度W2会小于第一开口150的第一宽度W1。蚀刻制程例如是干蚀刻或湿蚀刻制程。形成第二绝缘层124第二开口152的蚀刻方式可以和第一绝缘层122第一开口150的蚀刻方式相同或不同。以湿蚀刻制程为例，通过湿蚀刻制程的侧向蚀刻特性，第二绝缘层124的第二内侧壁162会呈现倾斜状而非垂直状，因而第二内侧壁162会和下方的保护层118(或是基板的表面)具有第二夹角θ2，其中第二夹角θ2为锐角。此外，在选定的湿蚀刻条件下，保护层118会作为蚀刻阻挡层，亦即蚀刻剂对于保护层118的蚀刻速率会小于蚀刻剂对于第二绝缘层124的蚀刻速率，而使得保护层118和第二绝缘层124之间的蚀刻选择比值小于1，例如为0.95、0.65、0.35、0.05、0.01、0.005或其中的任何数值。根据本发明的一些实施例，当第二绝缘层124的材料为氧化硅，且保护层118的材料为氮化硅时，可以采用缓冲氧化物蚀刻，以于第二绝缘层124中形成第二开口152，且不会在保护层118中形成开口或是凹陷。
当完成对第二绝缘层124的蚀刻制程之后，第二绝缘层124会展现出阶梯轮廓170，且阶梯轮廓170的梯缘172、174会分别重合第二绝缘层124的第二内侧壁162及第三内侧壁164。
接着如图9的剖面608所示，设置至少一金属材料于第二绝缘层124之上，并通过施行合适的图案化制程，以形成电极130。电极130会填入第二绝缘层124的第二开口152。电极130会自第二开口152往外延伸，且具有不对称的剖面结构。电极130的材料可包含金属、合金、半导体材料或其堆叠层。举例而言，电极130可包含金(Au)、镍(Ni)、铂(Pt)、钯(Pd)、铱(Ir)、钛(Ti)、铬(Cr)、钨(W)、铝(Al)、铜(Cu)、钼(Mo)等其它合适的导电材料或前述的组合。后续会进行光微影和蚀刻制程，以去除特定区域内的各层，而暴露出部分基板102的表面。
在完成图9的制程阶段之后，接着可在电极130及第二绝缘层124之上形成至少两个层间介电层及至少两个焊垫结构，使得焊垫结构分别电连接至其下方的汲极电极134及源极电极136，而获得如图1所示的半导体元件100。
图10是本发明变化型实施例的制作半导体元件的剖面示意图。如图10的剖面702所示，图10的制程类似于图8的制程，主要差异在于，在形成第二绝缘层124的第二开口152之后，会进一步施行光微影和蚀刻制程，以于保护层118中形成第五开口158，而暴露出下方的半导体叠层104，以及第五内侧壁168。其中，第五开口158的底面具有第五宽度W5，且第五宽度W5小于第二绝缘层124的第二宽度W2。
以上所述仅为本发明的较佳实施例，凡依本发明权利要求所做的均等变化与修饰，皆应属本发明的涵盖范围。

Claims (20)

  1. 一种半导体元件，其特征在于，包含：
    一基板，包含一表面；
    一半导体叠层，设置于该基板之上，包含一二维电子气区域；
    一绝缘结构，设置于该半导体叠层之上，包含：
    一第一绝缘层，包含一第一开口，该第一开口暴露出该第一绝缘层的一第一内侧壁；以及
    一第二绝缘层，设置于该第一绝缘层之上，且覆盖住该第一绝缘层的该第一内侧壁，其中该第二绝缘层包含一第二开口，位于该第一开口内且暴露出该第二绝缘层的一第二内侧壁，其中该第二绝缘层包含一阶梯轮廓，且该阶梯轮廓的一梯缘重合该第二内侧壁；以及
    一电极，设置于该绝缘结构之上，且位于该第二开口内。
  2. 如权利要求1所述的半导体元件，其特征在于，部分该第二绝缘层位于该第一开口内。
  3. 如权利要求1所述的半导体元件，其特征在于，该第二绝缘层还包含一第三内侧壁，设置于该第二内侧壁之上。
  4. 如权利要求3所述的半导体元件，其特征在于，该第二绝缘层的该阶梯轮廓包含另一梯缘，该另一梯缘重合该第三内侧壁。
  5. 如权利要求3所述的半导体元件，其特征在于，该第一内侧壁、该第二内侧壁及该第三内侧壁分别与该表面构成一第一夹角、一第二夹角及一第三夹角，其中该第二夹角不等于该第三夹角。
  6. 如权利要求5所述的半导体元件，其特征在于，该第二夹角小于该第三夹角。
  7. 如权利要求5所述的半导体元件，其特征在于，该第一夹角、该第二夹角及该第三夹角为锐角。
  8. 如权利要求7所述的半导体元件，其特征在于，该第一夹角、该第二夹角及该第三夹角为均不大于70度。
  9. 如权利要求1所述的半导体元件，其特征在于，该第一绝缘层的材料与该第二绝缘层的材料相同。
  10. 如权利要求1所述的半导体元件，其特征在于，该第一绝缘层的厚度大于该 第二绝缘层的厚度，且该第一绝缘层及该第二绝缘层的厚度均大于100nm。
  11. 如权利要求1所述的半导体元件，其特征在于，该第二绝缘层还包括一第三开口，设置于该第一开口及该第二开口之上。
  12. 如权利要求11所述的半导体元件，其特征在于，该第三开口的宽度介于该第一开口的宽度及该第二开口的宽度之间。
  13. 如权利要求1所述的半导体元件，其特征在于，还包含一保护层，位于该绝缘结构与该半导体叠层之间，该保护层的材料与该绝缘结构的材料不同。
  14. 如权利要求13所述的半导体元件，其特征在于，该保护层还包含一开口，暴露出该半导体叠层。
  15. 一种制作半导体元件的方法，其特征在于，包含：
    提供一基板；
    设置一半导体叠层于该基板之上，该半导体叠层包含一二维电子气区域；
    设置一第一绝缘层于该半导体叠层之上；
    蚀刻该第一绝缘层以形成一第一开口；
    设置一第二绝缘层于该第一绝缘层上，并填入该第一开口；
    蚀刻该第二绝缘层以形成一第二开口，该第二开口位于该第一开口中；以及
    设置至少一金属材料于该第二绝缘层上以形成一电极。
  16. 如权利要求15所述的制作半导体元件的方法，其特征在于，设置该第一绝缘层及该第二绝缘层的步骤包含气相沉积制程。
  17. 如权利要求15所述的制作半导体元件的方法，其特征在于，该第一绝缘层与该第二绝缘层包含氧化硅。
  18. 如权利要求15所述的制作半导体元件的方法，其特征在于，蚀刻该第一绝缘层及该第二绝缘层的步骤包含湿蚀刻。
  19. 如权利要求18所述的制作半导体元件的方法，其特征在于，于设置该第一绝缘层前，还包含设置一保护层于该半导体叠层上，该保护层的材料与该第一绝缘层的材料不同。
  20. 如权利要求19所述的制作半导体元件的方法，其特征在于，在蚀刻该第一绝缘层及该第二绝缘层时，该保护层作为蚀刻阻挡层。
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JP2018006481A (ja) * 2016-06-29 2018-01-11 サンケン電気株式会社 半導体装置及びその製造方法
CN207303109U (zh) * 2016-06-14 2018-05-01 半导体元件工业有限责任公司 电子器件
US20180204915A1 (en) * 2017-01-19 2018-07-19 Infineon Technologies Austria Ag Sloped Field Plate and Contact Structures for Semiconductor Devices and Methods of Manufacturing Thereof
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Publication number Priority date Publication date Assignee Title
CN207303109U (zh) * 2016-06-14 2018-05-01 半导体元件工业有限责任公司 电子器件
JP2018006481A (ja) * 2016-06-29 2018-01-11 サンケン電気株式会社 半導体装置及びその製造方法
US20180204915A1 (en) * 2017-01-19 2018-07-19 Infineon Technologies Austria Ag Sloped Field Plate and Contact Structures for Semiconductor Devices and Methods of Manufacturing Thereof
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