CN112262468A - 包括气隙上方的结构的装置 - Google Patents
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- CN112262468A CN112262468A CN201980039175.4A CN201980039175A CN112262468A CN 112262468 A CN112262468 A CN 112262468A CN 201980039175 A CN201980039175 A CN 201980039175A CN 112262468 A CN112262468 A CN 112262468A
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Abstract
一种装置,包括:衬底、衬底上方的牺牲材料层、牺牲层上方的第一固态材料层、固态材料层上方的介电层、以及介电层上方的第二固态材料层。牺牲材料层可具有气隙,固态材料层可以包括气隙上方的结构并且可通过槽与第一材料层的主体部分分隔开,其中,槽延伸到气隙。
Description
背景技术
异质外延(也称为单片集成)是一种用于在相同的衬底上集成不同的材料、用于特定的功能或增强的装置性能的强大技术。异质外延通常被用来生成由在其他情况下不易获取晶体的材料制成的结晶膜并制造由不同材料制成的集成结晶层。异质外延可用来在电子和光子装置中生成装置材料。
附图说明
参考附图,在下面的详细描述中描述一些示例,附图如下:
图1示出了示例的装置;
图2A和图2B示出了包括在第一固态材料层和第二固态材料层之间的多个介电层和交接层的示例的装置;
图3示出了装置包括第二固态材料层上方的台面;
图4示出了包括脊型波导的示例的装置;
图5A示出了示例的制造工艺流程;以及
图5B示出了该流的程步骤后的组件的俯视图。
具体实施方式
异质外延是一种用于制造用在光子和电子计算应用中的各种装置的有用的技术。但是,诸如不同的晶格常数或热膨胀系数(CTE)的材料特性不兼容性可能导致异质外延生长的材料中的缺陷。这些缺陷可能会对微电子装置和光子装置具有不利的影响。这些挑战对使用在硅片上异质外延生长的直接带隙化合物半导体制造高性能可靠的装置造成困难。
因此,已经耗费努力来开发最小化缺陷形成和传播方法。已经提出使用中间层、侧生法、以及量子点有源区。但是,这些解决方案不足以消除异质外延交接处的缺陷形成,并且它们不能产生具有足够可靠性的装置。另一解决方案包括将功能层限制在临界厚度内,在该临界厚度以下最大程度地减轻缺陷形成。但是,很多功能层厚度在相应的临界厚度以上。晶片结合(bonding)是通常用来接合装置层的技术。但是,晶片结合会产生额外的制造成本,并且与衬底的尺寸错配可能会影响装置总产量。
所描述的技术的实现方式提供了用于异质外延生长装置的平台。该平台包括在一种结构下方创建的气隙。例如,可以从绝缘体上硅(SOI)衬底移除隐埋氧化物(BOX)层的区域以创建气隙,该结构被蚀刻到SOI衬底的上硅层中。介电层可被用来提供用于晶片结合第二固态材料薄层的交接,该第二固态材料薄层于是用作为用于其他固态材料的外延生长的基层。另外,介电层和固态材料层可被用来形成电容器。
图1示出了示例的装置。该装置包括衬底101。衬底101可以是晶片或固体物质,其他物质粘附到其上。衬底101可用作为微电机(MEM)装置和光子装置的基础,并且可以是沉积电子装置和光子装置的基底。在一些示例中,衬底101可以是材料薄片,其可包括诸如硅和锗的半导体、诸如砷化镓(GaAs)和磷化铟(InP)的化合物半导体、或者诸如氧化硅和氧化铝的介电绝缘体。在一些示例中,衬底101可包括多种材料,包括但不限于以上列出的示例。另外,在一些示例中,衬底101可包括多个层,每个层具有不同的材料。在示例的实现方式中,衬底101是SOI衬底的基层。
该装置包括衬底上方的牺牲材料层102。例如,牺牲材料层102可包括诸如二氧化硅(SiO2)、氧化铝(Al2O3)、氮化硅(SiNx)或其他绝缘体的绝缘材料。例如,牺牲材料层102可以是SOI衬底的隐埋氧化物(BOX)层。作为另一个示例,牺牲材料层102可以是可被选择性地移除以创建气隙的另一种材料。例如,牺牲材料层102可包括GaAs/AlAs/GaAs衬底的砷化铝(AlAs)层。在这种情况下,可使用HF有选择地移除AlAs,该HF蚀刻AlAs比蚀刻GaAs更快。
层102包括气隙105。气隙105可通过有选择地移除层102的牺牲材料的一部分形成。在所示出的示例中,气隙105具有延伸通过整个牺牲材料层102的高度。换言之,在气隙105中移除层102中的所有牺牲材料,并且气隙105的底部与衬底层101的顶部重合。在其他实现方式中,气隙105可部分地延伸通过牺牲层102。例如,气隙105上方可存在一部分牺牲材料,气隙105下方可存在一部分牺牲材料,或者气隙105上方和下方都存在部分牺牲材料。
该装置进一步包括牺牲材料层102上方的第一固态材料层103。在一些实施方式中,第一固态材料层103可包括半导体材料,诸如直接或间接带隙半导体。例如,层103可包括硅、锗或诸如GaAs、InP、AlGaAs、AlAs、SiC、SiGe、SiGeC、InAs的化合物、或其他III-V或II-VI化合物半导体。层103可以是SOI衬底的上硅层或者绝缘体上硅锗(SGOI)衬底的上硅锗层。在各种实施方式中,层103可以是轻或重n或p型掺杂半导体。在其他实施方式中,层103是未掺杂的。
第一固态材料层103进一步包括通过槽108与层103的主体部分109(bulkportion)分隔开的结构104。例如,结构104可包括波导、光栅、光子晶体、反射器、或其他无源或有源光子装置。在所示出的示例中,结构104是完全从层103蚀刻出的。在其他示例中,该结构可包括附加组件,诸如调制器、金属化、有源光子组件或电子组件、或包括其他材料的附加层/结构。
结构104布置在气隙105上方。换言之,结构104的底面形成气隙105的顶部的至少一部分。槽108延伸通过层103进入气隙105。例如,在制造过程期间,槽108可被用作为用于移除层102的选择性下层蚀刻工艺期间的窗口。例如,槽108可允许诸如HF的化学蚀刻剂进入层102。另外,槽108将结构104与层103的主体部分109分开。这可将结构104与在层103和更高层(例如下面将描述的层107)之间的热膨胀系数差导致的应变隔离开。
该装置进一步包括固态材料层103上方的介电层106。在一些实施方式中,介电层106可包括二氧化硅、高k电介质(即,具有比二氧化硅更高的介电常数的电介质)、或低k电介质(即,具有比二氧化硅更低的介电常数的电介质)。例如,介电层106可包括多种材料,诸如铪、镐、钛、铝、硅等的氧化物以及硅酸盐、铝酸盐、钛酸盐、氮化物、以及包括多层布置的组合。另外,聚合物材料可用于介电层106,诸如聚甲基苯乙烯、聚环氧丙烷、和聚甲基丙烯酸甲酯。这些材料还可包括用于定制介电特性的两种或两种以上聚合物的共聚合(例如,使用聚酰亚胺和聚硅氧烷的共聚物)。可使用聚酰亚胺-陶瓷化合物,诸如,结合到聚合物基质中的氧化铝(Al2O3)、钛酸钡(BaTiO3)、二氧化钛(TiO2)、或二氧化锆(ZrO2)。介电层106可包括两个或两个以上不同的介电材料层。
介电层106的期望的厚度可取决于该层材料的类型(例如,该材料是高k还是低k电介质)和装置的目标应用(例如,电容器或光波导)。例如,当介电材料被用来实现高电容时,可能期望较薄(例如,数纳米级)的层,但是也不希望该层薄到产生不期望的大电容泄露电流的程度。在一些示例的实施方式中,层可具有0.5纳米(nm)-50nm级的厚度,或者可具有更大的厚度(从亚纳米厚度到数百纳米厚度)。给定层的厚度可用来偏置或补充用来形成该层的材料的材料特性。例如,当使用高k材料时,可使用相对较大的层厚度来实现与(相对较薄层厚度处)使用低k电介质相似的电容效应。可使用增大的层厚度来避免高泄露电流或补偿其他材料特性。通过减少层厚度和/或通过将多个薄层组合在一起,也可使用非常薄的层来实现各种特性。
该装置进一步包括介电层107上方的第二固态材料层107。在一些实施方式中,第二固态材料层107可包括与层103相同或不同的材料。例如,层107可包括Si、Ge、或诸如GaAs、InP、AlGaAs、AlAs、SiC、SiGe、SiGeC、InAs的化合物、或其他III-V或II-VI化合物半导体。在一些实施方式中,第二层107可包括晶片结合到包括层103-101的组件的下层和外延生长在下层上的上部。在一些此类情况中,上部可以是不同于下层的材料,并且可使用异质外延生长工艺生成。在各种实施方式中,层107可以是轻或重n型或p型掺杂半导体。在其他实施方式中,层107是未掺杂的。
图2A和图2B示出了包括在第一固态材料层和第二固态材料层之间的多个介电层和交接层的示例的装置。
该装置包括衬底201、包括气隙205的牺牲材料层202、包括槽208和结构204的第一固态材料层203、以及第二固态材料层207。这些元件可以是分别如本文针对衬底101、包括气隙105的牺牲材料层102、包括槽108和结构104的第一固态材料层103、以及第二固态材料层107所描述的那样。在本示例中,结构204包括脊型波导。但是,在其他示例中,结构204可以是本文描述的任何其他结构。
该装置进一步包括第一介电层206a和第一介电层206a上的第二介电层206b。例如,在制造期间,第一介电层206a可布置在第一层203上方,并且第二介电层206b可布置在第二层207上方。在制造期间,第二层207可被翻转,并且第二介电层206b可结合到第一介电层206a。第一介电层206a和第二介电层206b可包括相同或不同的介电材料。例如,介电材料可为针对电介质106描述的类型的材料。
图2B示出了在第一固态材料层203和第二固态材料层207之间的接合的特写视图。所示出的示例包括在第一介电层206a和第一固态材料层203之间的第一交接层206c。例如,基于提供低交接状态密度、同时增大介电层206a的表面光滑度和结合表面能量,交接层206c可用来提供在电介质206a和其它层之间的增强。
层206c可包括在介电层206a和第一固态材料层203之间的至少一个第一交接层、至少一个第二交接层等。多个这样的交接层206c可均匀分布在介电层206a下方。例如,交接层206c可被提供作为介电层,以制备非常光滑的表面。可选择这样的交接层206c,用来提供给定的期望特性(例如,提供机械平滑、悬空键钝化),而不需要满足电特性。随后,介电层206a可被沉积在交接层206c上,以在享受由交接层206c提供的改进的机械结合效应的同时提供期望的电学特性(例如,高k)和/或光学特性(例如,低光学损失)。另外,多个层的积累效应可以是协同的。例如,由于交接层206c可提供非常光滑的表面,所以沉积在交接层206c上的介电层206a也呈现光滑配置,从而使得介电层206a、206b本身在装置中不可与交接层206c接触的层-层交接处提供改进的键合性能。类似地,交接层206d可提供在电介质206b和其他层之间的增强。交接层206d可以是与交接层206c相同或不同的成分和结构。
交接层206c、206d从而在可能的材料选择的组合方面为其他层(诸如,第一固态层203和/或第二固态层207和介电层206a、206b)提供了大的灵活性。例如,当介电层206a、206b被直接沉积到半导体第一/第二层203、207上时,用于介电层206a、206b的一些材料可能会与半导体反应,从而在交接处产生气体副产物和/或自生氧化物,如果仅使用该材料的话,这会导致粗沉积和相应的不良结合。交接层206c、206d的使用可例如通过充当种子层以实现不同的材料用于它们期望的特性来防止这种不良结构,同时实现不同的材料的均匀一致性和的光滑沉积。交接层206c、206d还可钝化沉积有交接层(例如,第一层203和第二层207)的层的表面悬空键,从而保护这些层以防负面相互作用(例如,在大气中形成自生氧化物)并且提供高的交接质量和容易的结合。另外,交接层206c、206d可用作为种子层用于实现介电层206a、206b到其对应的交接层206c、206d上的均匀沉积。另外,交接层206c、206d可为其对应的固态材料层203、207提供悬空键钝化。
介电材料/层的不同组合实现了否则可能导致不良结合和/或性能的材料的使用,这些不良结合和/或性能会阻碍这些材料在其他情况中的给定应用(例如,光子学应用)中的使用。多功能的电介质堆叠实现了优化诸如不同材料之间的交接、光滑结合表面、高k介电材料的使用等方面的广泛选项。由于一个或多个交接层的使用,介电材料和半导体材料之间的交接可受益于高质量电介质、低交接缺陷、以及低交接状态密度。类似地,两个介电层(或介电层和半导体层)(例如,一个或多个介电层中的两个子层之间的)光滑结合表面实现在中等结合后退火温度处的高结合表面能量。包括实现相对低的交接状态密度的交接状态密度可根据交接类型而彼此不同。因此,如本文所使用的,低交接状态密度的概念对应于给定结合,并且相比在没有交接层的情况下实现结合,(例如通过使用一个或多个交接层140)实现了针对给定结合的相对低的交接状态密度。例如,对于Si/SiO2交接,~10^10cm^(-2)*eV^(-1)可被认为是相对低的交接状态密度。相比而言,对于InP/氧化物交接,相对低的交接状态密度可以比Si/SiO2交接高一个或两个数量级。因此,低交接状态密度会有利地影响诸如在MOS电容器性能的应用。对于MOS电容器应用,一个或多个交接层实现包括但不限于HfO2、ZrO2、TiO2、以及Al2O3的高k电介质的使用,(在没有一个或多个交接层的情况下)它们对于获取高电容性是期望的但是对于结合特性并不理想。
因此,第一层/第二层可被提供作为其中夹有一个或多个介电层的掺杂异质或同质半导体材料。一个或多个介电层和/或一个或多个交接层可用作为结合交接,并且还可充当例如MOS电容器的绝缘层。可引入具有高介电常数k或低介电常数k的电介质,同时通过一个或多个交接层或一个或多个适当的介电层来实现低孔隙密度(例如,如果介电层直接结合到第一固态层和/或第二固态层)。电介质方案的使用可通过结合技术提供异构集成,以与结合交接的优化分开地优化半导体/电介质交接,从而提供优化给定装置的多种技术。
图3示出了包括第二固态材料层307上方的台面315的装置。该装置包括衬底301、包括气隙305的牺牲材料层302、包括槽308和结构304的第一固态材料层303、以及第二固态材料层307。这些元件可分别如本文针对衬底101、包括气隙105的牺牲材料层102、包括槽108和结构104的第一固态材料层103、以及第二固态材料层107所述的那样。另外,尽管示出具有单个介电层106,但是装置可包括多个介电层,并且还可包括针对图2所述的交接层。
装置进一步包括台面结构315。台面结构315布置在气隙305上方。例如,台面结构315可布置在延伸通过槽308的垂直边界314内。在其他示例中,气隙305可延伸到超出槽308的外侧壁的牺牲层302的侧。在这种示例中,台面结构可在延伸通过气隙305的外侧壁的垂直边界内(即,台面可重叠第一层303的主体部分309的与气隙305重叠的部分)。
气隙305的存在可减轻由槽的侧壁限定的垂直区(即,边界314之间的区域)或由气隙305的侧壁限定的垂直区中缺陷的形成和传播。例如,气隙305可允许第一层304的独立部分309弹性变形,以适应由第一半导体层303和第二半导体层307之间的错配而产生的应力。通过将应力集中在第一半导体层303上,第二半导体层307的独立部分能够不易于缺陷形成和传播。另外,在一些示例中,第一半导体层303的厚度可在临界厚度以下,缺陷形成在临界厚度以下大大减少。因此,也可减轻第二层307的独立区域中的缺陷形成。由于结构305在第二层307的独立区域上方,所以也可避免结构315中的缺陷形成。
结构315可包括一个或多个材料层310-313。所示出的示例包括第二固态材料层307上的第一层310。在本示例中,第二固态材料层具有第一晶体结构,并且台面包括具有与第一晶体结构的晶格匹配的第二晶体结构的固态材料。当两种材料在相同的材料系统中时,它们可具有匹配的晶格,从而允许第二材料在第一材料上异质外延生长,以满足装置可操作性约束的足够低的缺陷率。例如,AlGaAs具有与GaAs、In上的InGaAsP匹配的晶格,并且可在这些衬底上以足够低的缺陷率生成。例如,在第一晶体结构与第一晶体结构相同的情况下,层310可包括与第二固态材料层307相同的固态材料。
在一些实施方式中,台面315可包括有源光子装置。例如,台面可包括激光器。例如,第一层310可以是掺杂半导体材料,并且台面可包括第二掺杂半导体层312和激光器增益材料层311。例如,层310-312可形成III-V半导体激光器。在其他示例中,台面315可包括其他光子装置,诸如二极管、饱和吸收体、光子放大器、或量子点激光器。
在所示出的示例中,台面315的下层310还用作为电容器317的上层。电容器371包括层310、层307、一个或多个介电层306、以及结构304的至少一部分。因此,结构304可用作为用于传输所生成的光的波导以及用于对光进行调节的电容器的一部分。例如,电容器317可以是金属氧化物半导体(MOS)电容器,其可被用来基于高k电介质的使用来增大调解范围,从而调节光学折射率和光损。还可通过使用低k电介质来降低一些电容器的调解容量,因为低k电介质为所使用的光波长提供了较低的光损的好处。因此,一个或多个介电层306可提供与光模319兼容的介电特性,这些光模至少部分地与装置重叠。光模319与大约10纳米级到1毫米级的波长相关联,并且一个或多个介电层和一个或多个交接层的方案基于装置的给定波长并且基于给定波长实现了低光损。另外,层310、307、306、304所形成的电容器307可被用来调节光学折射率和光损,其中,优选高k电介质。经由横跨激光器层313-310施加的电压(VLASER)生成激光器光模319,并且横跨层310、304施加的电压(VMOS)导致载波分布变化,从而提供了激光谐振波长调节和损失调节。
图4示出了包括脊形波导404的示例的装置。在图3中,矩形波导304允许限制在台面315的宽度上的光模。在图4中,脊型波导404准许光模419被限制到脊型波导404的上部。因此,图4可允许更广泛的通信415,而不会对所准许的光模造成影响。
图5A示出了示例的制造工艺流程。图5B示出了在流程的步骤501之后的组件的俯视图。各个层可通过等离子增强化学气相沉积(PECVD)、原子层沉积(ALD)、溅射沉积、热氧化、臭氧氧化、湿化学氧化、天然氧化物、旋涂、或一种或多种方法的组合来产生。
示例的过程开始于步骤501。步骤501包括在第一固态材料层520中形成延伸到牺牲材料层521的槽523,使得槽523限定与第一材料层520的主体部分分隔开的结构524。例如,步骤501可包括光刻限定和化学蚀刻槽。在所示出的示例中,槽523延伸通过第一层523并且止于牺牲层521。但是,在其他实施方式中,槽523可延伸通过或部分通过牺牲层521,以引入用于形成适当深度的气隙524的蚀刻剂。
例如,可使用同位素湿法蚀刻,例如,使用氢氟酸(HF)来形成槽。作为另一示例,层520可利用一种或多种等离子体气体(例如,包含氟离子的四氟化碳)在商业上可获得的蚀刻机(例如,平行板DRIE装置或者电子回旋共振(ECR)等离子体反应器)中各向异性地蚀刻,以在层520中复制槽的掩膜图案。在所示出的示例中,结构524可以是矩形波导,并且槽523是矩形棱柱。在其他示例中,步骤501可包括蚀刻结构524的进一步特征。例如,步骤501可包括蚀刻其他波导特征,例如,蚀刻脊型波导的外部。作为另一示例,步骤501可包括蚀刻凹槽以限定光栅的脊或光子晶体的孔。
示例的过程继续到步骤502。步骤502包括使用槽523来有选择地移除牺牲材料层521的一部分,以在结构524下方形成气隙525。例如,步骤502可包括引入选择性的湿法蚀刻剂来通过槽523进入层521以及同位素蚀刻气隙。例如,可采用使用HF的湿法蚀刻来移除气隙。
示例的过程继续到步骤503。步骤503包括在第一固态材料层520上方布置介电层526。例如,步骤503可包括在第一固态材料层520上沉积介电层526。在利用交接层的实施方式中,步骤530可包括在层520上沉积一个或多个交接层,并且于是在最上面的交接层上沉积介电层526。
示例的过程继续到步骤504。在步骤504,获取包括第二固态材料层的晶片527。步骤504还可包括在晶片527上沉积第二介电层529并翻转晶片,使得第二介电层529面向第一介电层526。
示例的过程继续到步骤505。在步骤505,晶片527被结合到包括牺牲材料层521和第一固态材料层520的组件530。例如,步骤505可包括将晶片527的外部介电层529结合到组件530的外部介电层526。另外,步骤505可包括各种结合前处理,以增强结合步骤。例如,步骤505可包括通过沉积前清洗的处理,例如,美国无线电公司(RCA)清洗、自生氧化物去除、通过湿法化学或通过等离子清洗的悬挂键钝化。层可通过应用沉积后热退火产生密集电介质、通过应用沉积后等离子处理抑制交接气泡形成、或者通过应用结合后退火生成大结合表面能量来改善。
示例的过程继续到步骤506和步骤507,以创建由MOS电容器调节的激光器。但是,由步骤505产生的平台可用在各种光子系统或MEM系统中。
步骤506包括在晶片527的上表面上形成台面531。例如,步骤506可包括利用电介质掩膜532对组件表面的一部分图案化并且在组件的未遮掩部分上产生台面531。如上所述,台面可包括与第二固态材料528相同或不同的材料。台面的将在材料528上外延生长的部分可具有与材料528相同或兼容的晶格结构。
步骤S507包括将电压源534耦合到由结构和台面的一部分形成的电容器。例如,电容器可由台面531的下层536、第二固态材料层528、介电层529、526、以及结构524形成。步骤507可进一步包括将电压源533耦合到台面531的第二部分,以对第二有源光子装置供电。例如,步骤507可包括耦合第二电压源533,以对形成在台面531的上部区537中的III-V材料激光器供电。
在上面的描述中,给出了很多细节,以提供对本文公开的主题的理解。但是,可在没有这些细节中的一些或所有细节的情况下实施实施方式。其他实施方式包括对于以上讨论的细节的变型和改变。希望所附权利要求覆盖这些变型和改变。
Claims (20)
1.一种装置,包括:
衬底;
牺牲材料层,所述牺牲材料层在所述衬底上方,所述牺牲材料层包括气隙;
第一固态材料层,所述第一固态材料层在所述牺牲层上方,所述固态材料层包括在所述气隙上方并且通过槽与所述第一材料层的主体部分分隔开的结构,所述槽延伸到所述气隙;
介电层,所述介电层在固态材料层上方;
第二固态材料层,所述第二固态材料层在所述介电层上方。
2.如权利要求1所述的装置,其中,所述气隙在所述第一固态材料层的主体部分的一部分下方延伸。
3.如权利要求1所述的装置,其中,所述结构是无源光子装置。
4.如权利要求3所述的装置,其中,所述结构是波导。
5.如权利要求4所述的装置,其中,所述结构是脊型波导。
6.如权利要求1所述的装置,其中,所述结构、所述介电层以及所述第二固态材料层形成电容器。
7.如权利要求1所述的装置,进一步包括台面,所述台面在所述第二固态材料层上方。
8.如权利要求7所述的装置,其中,所述第二固态材料层具有第一晶体结构,并且所述台面包括固态材料,所述固态材料具有第二晶体结构,所述第二晶体结构具有与所述第一晶体结构匹配的晶格。
9.如权利要求8所述的装置,其中,所述台面包括与所述第二固态材料层相同的固态材料,并且所述第一晶体结构与所述第二晶体结构相同。
10.如权利要求1所述的装置,进一步包括有源光子装置,所述有源光子装置在所述第二固态材料层和所述气隙上方。
11.如权利要求10所述的装置,其中,所述有源光子装置在由所述槽限定的垂直边界内。
12.如权利要求1所述的装置,进一步包括第二介电层,所述第二介电层在所述第一介电层上方。
13.如权利要求1所述的装置,其中,所述第一材料层包括氧化物,所述第一固态材料层包括硅,并且所述第二固态材料层包括III-V材料。
14.如权利要求1所述的装置,其中,所述气隙延伸穿过整个牺牲材料层。
15.一种方法,包括:
在第一固态材料层中形成延伸到牺牲材料层的槽,使得所述槽限定与所述第一材料层的主体部分分隔开的结构;
使用所述槽以有选择地移除所述牺牲材料层的一部分,以便在所述结构下方形成气隙;
在所述第一固态材料层上方布置介电层;以及
将包括第二固态材料层的晶片结合到包括所述牺牲材料层和所述第一固态材料层的组件。
16.如权利要求15所述的方法,进一步包括:
在第二固态材料层上形成台面,所述第二固态材料层在所述气隙上方。
17.如权利要求16所述的方法,其中,所述台面包括与所述第二固态材料层相同的材料。
18.如权利要求16所述的方法,进一步包括将电压源耦合到电容器,所述电容器由所述台面的一部分和所述结构形成。
19.如权利要求15所述的方法,其中,在所述第一固态材料层上方布置所述介电层包括在所述第一固态材料层上方沉积第一介电层。
20.如权利要求19所述的方法,进一步包括在所述晶片上沉积第二介电层,并且其中,结合所述晶片包括将所述第二介电层结合到所述第一介电层。
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