CN1120523C - 制造栅极导体的方法 - Google Patents

制造栅极导体的方法 Download PDF

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CN1120523C
CN1120523C CN98118732A CN98118732A CN1120523C CN 1120523 C CN1120523 C CN 1120523C CN 98118732 A CN98118732 A CN 98118732A CN 98118732 A CN98118732 A CN 98118732A CN 1120523 C CN1120523 C CN 1120523C
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polysilicon
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CN1213159A (zh
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马丁·施莱姆斯
马赛厄·勒格
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Infineon Technologies AG
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Abstract

提供了一种形成具有多晶硅和硅化物层并且减小的电阻和减小的厚度的栅极的方法。多晶硅层经过退火，使掺杂物从表面扩散开，从而将掺杂物的浓度减小到一个低于能够产生富金属界面的水平。因此，可以在没有一层本征多晶硅冠层或者需要一层具有减小的掺杂物浓度的情况下淀积一层金属硅化物层。如是，获得了一种具有低薄膜电阻和改进的稳定性的较薄的栅极叠层。

Description

制造栅极导体的方法
技术领域
本发明的领域总的说来涉及半导体制造，确切地说涉及具有多晶硅-硅化物(polysilicon-silicide)栅极的晶体管。
背景技术
在器件制造中，在一块衬底上形成绝缘层、半导体层和导体层。对这些层进行刻图形成图形区和空白区。所刻的图形区和空白区能够形成器件，例如晶体管、电容和电阻。这些器件然后被相互连接起来以取得所需要的电功能，建立一个集成电路(IC)。
为了减小薄膜电阻(sheet resistance)，金属氧化物半导体晶体管(MOS)采用多晶硅硅化物(polycide)栅极，多晶硅-硅化物(polycide)栅极由金属硅化物，例如硅化钨(WSix)置于重掺杂的多晶硅(poly)上构成。通常，多晶硅掺杂磷(P)。多晶硅应当包含尽可能高的杂质浓度以降低其薄膜电阻。
但是，重掺杂的多晶硅之上的金属硅化物呈现出理想配比控制问题，其表现形式为富金属界面。富金属界面是不希望的，因为它不耐受后续的热处理过程。其结果是，界面被氧化。氧化导致表面粗糙，在某些情况下，硅化物薄膜脱层。因此，多晶硅和硅化物之间的界面应当被保持在低于产生富金属界面的水平。通常，磷浓度应当被保持在低于1019原子/cm3。
传统地，富金属界面的负效应通过在重掺杂的多晶硅和金属硅化物之间设置一层本征(不掺杂)的多晶硅层来避免。另一种避免富金属界面的技术是降低多晶硅的掺杂浓度。但是，这些技术不希望地增加了栅极电阻，导致器件性能的下降。
发明内容
根据以上描述可知，希望提供一种可靠的具有减小的薄膜电阻的多晶硅-硅化物(polycide)栅极。本发明的任务是提供一种制造栅极导体的方法，以获得可靠的具有减小的薄膜电阻的多晶硅-硅化物栅极。
为此，本发明提供一种制造栅极导体的方法包括：
提供一个衬底；
在衬底上制造一层介质并且在介质层上形成一层多晶硅层，其中介质用作栅极介质，多晶硅掺杂的掺杂物的浓度大于能够引起富金属界面的浓度；
使衬底退火，退火的温度大于上述形成介质层和多晶硅层的温度，退火的压力小于上述形成介质层和多晶硅层的压力，其中退火使掺杂物从多晶硅层的表面扩散开，从而产生一个其掺杂物浓度低于能够引起富金属界面的浓度的上部；
在多晶硅层上面形成一层金属硅化物层。
本发明涉及一种具有减小的厚度和降低的薄膜电阻的栅极导体的制造。在一个实施例中，通过制造一个重掺杂的多晶硅层并使其退火，使得杂质从其表面扩散开从而使杂质浓度降低到能引起富金属界面的水平以下，取得了厚度的减小和薄膜电阻的降低。这样允许金属硅化物层在没有一层本征多晶硅冠层或者需要一层低掺杂浓度的多晶硅层的情况下淀积。
附图说明
图1显示一个示意性的DRAM单元；
图2A-2C表示制造根据本发明的多晶硅-硅化物栅极叠层的方法。
具体实施方式
本发明涉及一种具有减小的薄膜电阻的可靠的多晶硅-硅化物栅极。为了有助于本发明的讨论，对其描述借助于一个存储器IC。然而，本发明显然是更宽的，适用于一般的集成电路。这里提供的是一种DRAM单元的说明。
参考图1，表示了一种沟槽电容型DRAM单元100。该沟槽电容型DRAM单元在例如Nesbit等所著的“A 0.6μm2256Mb Trench DRAM With Self-alignedBuried Strap(BEST)”，IEDM 93-627中有说明，该文在这里被引用作为任何情况下的参考。尽管画出的是一个沟槽电容型DRAM单元，但本发明并不局限于此。例如，也可以使用一个叠层电容型DRAM单元。通常，该元件的一个阵列经过字线和位线的相互连接后构成一个DRAM集成电路。
说明性地，DRAM单元101包括在衬底100上形成的沟槽电容160。沟槽通常填充重掺杂了具有第一电导率例如n-型的杂质的多晶硅(poly)161。多晶硅起电容器的一个极板—称为“存储结”的作用。一个埋入的掺杂了具有第一电导率的杂质的极板包围着沟槽的底部。在沟槽的上部，有一个环168，用以减小寄生漏电。结介质163将电容的两个极板隔开。设置一个由第一电导率的杂质构成的埋入井170以便将埋入的DRAM单元极板连接成阵列。在埋入井的上方有一个由具有第二电导率例如p-型杂质构成的井173。p-井所包含的杂质浓度足以形成一个相反的导电结，以减小晶体管110的垂直漏电。
晶体管包括一个多晶硅-硅化物栅极叠层112。栅极叠层，有时被称为“栅极导体”，在DRAM单元阵列中起字线作用。如图所示，栅极叠层包括一个重掺杂了杂质的多晶硅层120。在一个实施例中，多晶硅层120重掺杂了磷杂质。使用硼(B)和砷(As)也是可行的。为了将薄膜电阻保持在低水平，多晶硅的掺杂浓度应当尽可能高。在重掺杂的多晶硅120之上设置了一层本征多晶硅层121和一层金属硅化物层122。本征多晶硅层起避免硅化物和重掺杂的多晶硅层之间的富金属界面的缓冲层的作用。尽管重掺杂的多晶硅层中的杂质在后续的热处理工艺中扩散进入本征多晶硅，但多晶硅在最初的金属硅化物层的淀积过程中是本征的。金属硅化物层之上是氮化物层，它起腐蚀阻挡层的作用。
靠近栅极形成了重掺杂扩散区113和114。扩散区包含具有与多晶硅层相同，与井173相反的第一电导率的杂质。扩散区重掺杂了例如n型杂质。根据电流流动的方向，扩散区113和114被分别称为“漏极”和“源极”。在文本中，“漏极”和“源极”是可以互换的。晶体管和电容器之间的连接通过扩散区实现，称为“结扩散”。
一个浅沟槽隔离(STI)180被提供以将DRAM单元与其它元件和器件进行隔离。如图所示，字线在沟槽之上形成并且被STI与之隔离。字线被称为“通过字线”，因为它没有被电连接到DRAM单元。这样的构造被称为折叠的位线结构。也可以使用的其它的构造，包括开口和开口折叠的构造。
在字线上形成了一个层间介质层189。一个代表位线的导电层被形成在层间介质层之上。在层间介质层中形成了一个位线接触孔186，目的是使源极113与位线190接触。
如前面所述，重掺杂的多晶硅与硅化物层之间的多晶硅缓冲层的使用增加了栅极叠层的厚度。增加的厚度是不希望的，因为它产生较高的图形外观比(高宽比)，导致填充的困难。
图2A-2C表示制造根据本发明的多晶硅-硅化物(polycide)栅极叠层的方法。参考图2A，示出了代表一个集成电路一部分的衬底的剖面。该集成电路，是例如一个随机存取存储器(RAM)，一个动态RAM(DRAM)，一个同步DRAM(SDRAM)，一个静态RAM(SRAM)，和一个只读存储器(ROMs)，此外，集成电路可以是一个逻辑器件，例如可编程逻辑阵列(PLA)，专用集成电路(ASIC)，混合DRAM-逻辑集成电路(嵌入DRAM单元)或其它逻辑器件。
通常，在一个半导体衬底例如硅片上并列地制造若干个集成电路。完成以后，切割硅片，从而将集成电路分成单个的芯片。然后芯片被封装成最后的使用产品，例如消费产品，如计算机系统，蜂窝电话，个人数字辅助设备(PDAs)，和其它电子产品。
衬底201是，例如一个硅晶片。其它衬底，如绝缘材料上的硅(SOI)，蓝宝石上的硅(SOS)，锗，砷化镓和III-V族化合物也可以使用。在一个实施例中，衬底轻掺杂了具有第一电导率的杂质。在一个实施例中，衬底轻掺杂了p-型杂质(p-)，例如硼。硼的浓度大约为1.5×1016原子/cm3。
举例说，衬底上包括一组形成在其上的沟槽电容器(未画出)。沟槽电容器，是例如图1中所描述的。在一个实施例中，沟槽电容器n-沟道DRAM单元的存储电容的作用。设置埋入的n-井以连接电容器的n型埋入极板。为n-沟道的DRAM单元存取晶体管设置了p-井。p-井的浓度是大约5×1017-8×1017原子/cm3。此外，为p-沟道晶体管，例如支持电路所使用的p-沟道晶体管设置了n-井。可根据需要在衬底上制造其它的扩散区。
在制造过程的这一点，衬底包括一个平面的表面210。一牺牲氧化物层(未示出)形成在表面之上。牺牲氧化物层的作用是为注入离子以调整后面形成的晶体管的栅极阈值电压(Vt)作屏蔽氧化物之用。Vt调整注入使用，例如常规的光刻和掩模工艺，在栅极的沟槽区域选择性地注入杂质。该工艺包括在屏蔽氧化物层上淀积一层光刻胶层，并且选择性地使其暴露到曝光源和掩模。根据所用的光刻胶的正性和负性，光刻胶或者是曝光的部分或者是未曝光的部分在显影过程被除去，以选择性地露出下面的衬底。然后在露出的部分注入离子以取得所希望Vt。
在Vt注入之后，光刻胶和屏蔽氧化物层通过例如一次湿腐蚀除去。然后在衬底表面生长一层薄膜的氧化物层220。该氧化物层作为栅极氧化层。在一个实施例中，栅极氧化层通过热氧化生长。栅极氧化层的厚度是例如6-10nm左右。
然后在栅极氧化层220上淀积一层多晶硅层230。多晶硅层进行重掺杂以减小薄膜电阻。在一个实施例中，多晶硅层掺杂磷。n-型杂质例如砷(As)或者p-型杂质例如硼(B)也可以使用。磷的重掺杂浓度大约为2×1020-5×1020原子/cm3，优选约5×1020原子/cm3。
掺杂的多晶硅层通过化学汽相淀积(CVD)法淀积。杂质在CVD过程中与该层结合。该过程被称为即时(in-situ)掺杂CVD。在一个实施例中，掺杂磷的多晶硅层通过即时掺杂快速热CVD法(RTCVD)淀积。在一个说明性的实施例中，该层是在一个CVD反应器中，在温度为大约620-680℃，压力为大约100托的条件下淀积的。或者，多晶硅层也可以非结晶形式淀积。例如，多晶硅的非结晶淀积可以在570℃这样低的温度下进行。SiH4和PH3与载体气体一起被注入反应器。SiH4的作用是作为硅的先驱物，PH3的作用是作为磷源。另外低压CVD(LPCVD)也可用于多晶硅的淀积。
接下来对衬底进行退火，对于磷掺杂的多晶硅层230，使掺杂剂向外扩散。退火足以减小掺杂的多晶硅层表面的杂质浓度。杂质浓度减小到低于能够产生富金属介面的水平。在一个实施例中，磷浓度被减小到低于约1019原子/cm3，以避免与以后淀积的金属硅化物层之间形成富金属介面，退火是在大于淀积温度的温度下进行的。在一个实施例中，退火温度在大约700-1000℃之间。退火的压力低于淀积的压力。在一个实施例中，压力大约0.02-10托之间。如果多晶硅层是通过LPCVD淀积的，则退火压力将较低，以低于淀积压力。
向外扩散步骤能够使掺杂的多晶硅层的体内具有足够高的杂质浓度，同时减小表面的杂质浓度。这样在不需要一层缓冲多晶硅层的情况下，避免了由于与后面淀积的金属硅化物层之间的相互作用而引起的富金属界面。结果就形成了一个可靠的具有较低薄膜电阻的多晶硅-硅化物(polycide)栅极导体。
参考图2B，一层金属硅化物层淀积在多晶硅层230上。在一个实施例中，金属硅化物由硅化钨(WSix)构成，也可以使用例如硅化钼(MoSix)，硅化钽(TaSix)，硅化钛(TiSix)，硅化钴(CoSix)，或任何其它硅化物。WSix通过已知的CVD工艺淀积。该工艺包括将六氟化钨(WF6)，硅烷(SiH4)，二氯硅烷(SiCl2H2)和载体气体注入一个反应室，以生成WSix层。在金属硅化物层之上形成一层冠层250。冠层由例如氮化物构成。冠层可以作为后序处理工艺的抛光和/或腐蚀阻挡层。
参考图2C，对栅极叠层刻图以形成栅极导体260。栅极导体的刻图使用常规的光刻和腐蚀工艺完成。该工艺包括淀积一层光致抗蚀剂层，并选择性地将光致抗蚀剂层暴露到曝光源和掩模。一部分光致抗蚀剂层显影后被剥除，将栅极叠层的一部分置于不受保护状态。栅极叠层未被保护的部分通过例如反应离子蚀刻法(RIE)被除去。
可以选择性地在栅极导体的侧壁制造隔离层(未画出)。隔离层形成之后，将杂质注入，在晶体管的栅极邻近区域形成扩散区。隔离层限制了扩散区的缩窄扩散(underlap diffusion)，这样能够减小重叠电容。
在衬底表面上淀积一层氮化物层，作为迁移离子的阻挡层以及形成无边缘的位线接点的腐蚀阻挡层。在器件结构上形成了一层介质层265从而在导电层(除需要的接点之外)之间形成绝缘，或者作为将器件结构与杂质、湿度和划痕隔离的层。举例来说，介质层包括掺磷的二氧化硅，磷硅酸盐玻璃(PSG)或硼磷硅酸盐玻璃(BPSG)。
接点270被形成在介质层上，与导电层280形成连接。举例来说，导电层为DRAM芯片的位线。
尽管借助于各实施例对本发明进行了特别的展示和说明，本领域普通技术人员可以发现可以对本发明作出许多不偏离其范围的改进和改变。因此，本发明的范围不应当借助上述说明确定，而是应当借助于所附的权利要求书以及其各种等同物的所有范围来确定。

Claims (1)

1.一种制造栅极导体的方法包括：
提供一个衬底；
在衬底上制造一层介质并且在介质层上形成一层多晶硅层，其中介质用作栅极介质，多晶硅掺杂的掺杂物的浓度大于能够引起富金属界面的浓度；
使衬底退火，退火的温度大于上述形成介质层和多晶硅层的温度，退火的压力小于上述形成介质层和多晶硅层的压力，其中退火使掺杂物从多晶硅层的表面扩散开，从而产生一个其掺杂物浓度低于能够引起富金属界面的浓度的上部；
在多晶硅层上面形成一层金属硅化物层。
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Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6358788B1 (en) * 1999-08-30 2002-03-19 Micron Technology, Inc. Method of fabricating a wordline in a memory array of a semiconductor device
US6774439B2 (en) * 2000-02-17 2004-08-10 Kabushiki Kaisha Toshiba Semiconductor device using fuse/anti-fuse system
US6916745B2 (en) 2003-05-20 2005-07-12 Fairchild Semiconductor Corporation Structure and method for forming a trench MOSFET having self-aligned features
US6696345B2 (en) * 2002-01-07 2004-02-24 Intel Corporation Metal-gate electrode for CMOS transistor applications
JP2004241687A (ja) * 2003-02-07 2004-08-26 Toshiba Corp トレンチキャパシタの形成方法及び半導体装置
KR100497474B1 (ko) * 2003-06-20 2005-07-01 주식회사 하이닉스반도체 반도체소자의 게이트전극 형성방법
CN1790642A (zh) 2004-11-08 2006-06-21 松下电器产业株式会社 半导体装置的制造方法
US7888245B2 (en) 2006-05-11 2011-02-15 Hynix Semiconductor Inc. Plasma doping method and method for fabricating semiconductor device using the same
KR100844957B1 (ko) * 2006-05-11 2008-07-09 주식회사 하이닉스반도체 플라즈마 도핑 방법 및 이를 이용한 반도체 소자의 제조방법
CN102157360B (zh) * 2010-02-11 2012-12-12 中芯国际集成电路制造(上海)有限公司 一种栅极制造方法
KR102127792B1 (ko) 2013-04-02 2020-06-30 삼성디스플레이 주식회사 표시장치
CN108321147A (zh) * 2018-02-05 2018-07-24 华大半导体有限公司 一种改变多晶电阻阻值的方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0772231A2 (en) * 1995-10-31 1997-05-07 International Business Machines Corporation A method of forming a low stress polycide conductors on a semiconductor chip
CN1149198A (zh) * 1995-10-24 1997-05-07 台湾茂矽电子股份有限公司 具有倒t型栅极mos晶体管的低度掺杂漏极的制造方法及其结构
JPH09219500A (ja) * 1996-02-07 1997-08-19 Taiwan Moshii Denshi Kofun Yugenkoshi 高密度メモリ構造及びその製造方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4992391A (en) * 1989-11-29 1991-02-12 Advanced Micro Devices, Inc. Process for fabricating a control gate for a floating gate FET
JPH07297400A (ja) * 1994-03-01 1995-11-10 Hitachi Ltd 半導体集積回路装置の製造方法およびそれにより得られた半導体集積回路装置
US5824577A (en) * 1995-02-16 1998-10-20 National Semiconductor Corporation MOSFET with reduced leakage current
US5571733A (en) * 1995-05-12 1996-11-05 Micron Technology, Inc. Method of forming CMOS integrated circuitry
US5712196A (en) * 1995-06-07 1998-01-27 Advanced Micro Devices, Inc. Method for producing a low resistivity polycide
JP2792467B2 (ja) * 1995-06-13 1998-09-03 日本電気株式会社 半導体装置の製造方法
US5792686A (en) * 1995-08-04 1998-08-11 Mosel Vitelic, Inc. Method of forming a bit-line and a capacitor structure in an integrated circuit
US5543350A (en) * 1995-09-29 1996-08-06 Chartered Semiconductor Manufacturing Pte Ltd SRAM resistor tab doping by plug implant from buried contact
US5719071A (en) * 1995-12-22 1998-02-17 Sgs-Thomson Microelectronics, Inc. Method of forming a landing pad sturcture in an integrated circuit
US5767558A (en) * 1996-05-10 1998-06-16 Integrated Device Technology, Inc. Structures for preventing gate oxide degradation
US5672525A (en) * 1996-05-23 1997-09-30 Chartered Semiconductor Manufacturing Pte Ltd. Polysilicon gate reoxidation in a gas mixture of oxygen and nitrogen trifluoride gas by rapid thermal processing to improve hot carrier immunity
US5834356A (en) * 1997-06-27 1998-11-10 Vlsi Technology, Inc. Method of making high resistive structures in salicided process semiconductor devices

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1149198A (zh) * 1995-10-24 1997-05-07 台湾茂矽电子股份有限公司 具有倒t型栅极mos晶体管的低度掺杂漏极的制造方法及其结构
EP0772231A2 (en) * 1995-10-31 1997-05-07 International Business Machines Corporation A method of forming a low stress polycide conductors on a semiconductor chip
JPH09219500A (ja) * 1996-02-07 1997-08-19 Taiwan Moshii Denshi Kofun Yugenkoshi 高密度メモリ構造及びその製造方法

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