CN112017971A - 集成电路器件的封装件及其形成方法 - Google Patents

集成电路器件的封装件及其形成方法 Download PDF

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CN112017971A
CN112017971A CN202010265226.XA CN202010265226A CN112017971A CN 112017971 A CN112017971 A CN 112017971A CN 202010265226 A CN202010265226 A CN 202010265226A CN 112017971 A CN112017971 A CN 112017971A
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package
device die
forming
opening
die
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CN112017971B (zh
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李宛谕
林强
林岳霆
曾华伟
黄立贤
胡毓祥
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

形成集成电路器件的封装件的方法包括：形成重构晶圆，包括将器件管芯密封在密封剂中，在器件管芯和密封剂上方形成介电层，形成延伸至介电层中以电耦接至器件管芯的多条再分布线，以及在用于形成多条再分布线的常规工艺中形成金属环。金属环环绕多条再分布线，并且金属环延伸至重构晶圆的划线中。沿重构晶圆的划线实施管芯锯切工艺以将封装件从重构晶圆分离。封装件包括器件管芯和至少部分金属环。本发明的实施例还涉及集成电路器件的封装件。

Description

集成电路器件的封装件及其形成方法
技术领域
本发明的实施例涉及集成电路器件的封装件及其形成方法。
背景技术
随着半导体技术的发展，半导体芯片/管芯变得越来越小。同时，需要将更多功能集成到半导体管芯中。因此，半导体管芯需要越来越多的I/O焊盘封装到较小的区域中，并且I/O焊盘的密度会随着时间的推移而迅速提高。因此，半导体管芯的封装变得更加困难，这不利地影响了封装件的良率。
常规封装技术可以分为两类。在第一类中，晶圆上的管芯在锯切之前被封装。这种封装技术具有一些有利特征，诸如更高的产量和更低的成本。此外，需要较少的底部填充物或模塑料。然而，这种封装技术也存在缺点。由于管芯的尺寸变得越来越小，并且相应的封装件只能是扇入型封装件，其中，每个管芯的I/O焊盘被限制在相应管芯的表面正上方的区域。在管芯的有限区域中，由于I/O焊盘的间距的限制，I/O焊盘的数量受到限制。如果要减小焊盘的间距，则可能会出现焊桥。此外，在固定的球尺寸要求下，焊球必须具有一定尺寸，这又限制了可以封装在管芯表面上的焊球的数量。
在另一类封装中，在它们被封装之前先从晶圆上锯切管芯。这种封装技术的一个优势是可以形成扇出封装件，这意味着可以将管芯上的I/O焊盘再分布到比管芯更大的区域，并且因此，可以增加形成在管芯表面上的I/O焊盘的数量。该封装技术的另一有利特征是，封装“已知良好管芯”，并且丢弃有缺陷的管芯，并且因此，不会在有缺陷的管芯上浪费成本和精力。
发明内容
本发明的一些实施例提供了一种形成集成电路器件的封装件的方法，包括：将第一器件管芯和第二器件管芯密封在密封剂中；在所述第一器件管芯、所述第二器件管芯和所述密封剂上方形成第一介电层；图案化所述第一介电层以形成第一开口和第二开口，其中，所述第一器件管芯和所述第二器件管芯的导电部件暴露于所述第一开口，并且其中，所述第二开口延伸至所述第一器件管芯和所述第二器件管芯之间的划线中；形成延伸至所述第一开口中以电耦接至所述第一器件管芯和所述第二器件管芯的第一再分布线；在所述第一再分布线上方形成第二介电层；图案化所述第二介电层以形成第三开口和第四开口，其中，所述第一再分布线的部分暴露于所述第三开口，并且所述第四开口延伸至所述划线中；形成延伸至所述第三开口中以电耦接至所述第一再分布线的第二再分布线；以及实施管芯锯切工艺，以分别将所述第一器件管芯和所述第二器件管芯分离为第一封装件和第二封装件，其中，所述管芯锯切工艺的切口穿过所述划线。
本发明的又一些实施例提供了一种形成集成电路器件的封装件的方法，包括：形成重构晶圆，包括：将器件管芯密封在密封剂中；在所述器件管芯和所述密封剂上方形成第一介电层；形成延伸至所述第一介电层中以电耦接至所述器件管芯的第一多条再分布线；以及在用于形成所述第一多条再分布线的常规工艺中形成第一金属环，其中，所述第一金属环环绕所述第一多条再分布线，并且所述第一金属环延伸至所述重构晶圆的划线中；以及沿所述重构晶圆的划线实施管芯锯切工艺以从所述重构晶圆分离封装件，其中，所述封装件包括所述器件管芯和至少部分所述第一金属环。
本发明的另一些实施例提供了一种集成电路器件的封装件，所述封装件包括：器件管芯；密封剂，将所述器件管芯密封在所述密封剂中；多个介电层，位于所述密封剂上面，其中，所述多个介电层的边缘与所述封装件的边缘间隔开，并且所述多个介电层的上层的边缘比所述多个介电层的相应下层的边缘朝向所述封装件的中心凹进更多；以及多条再分布线，延伸至所述多个介电层中以电耦接至所述器件管芯。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该指出，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1至图16示出了根据一些实施例的封装件的形成中的中间阶段。
图17示出了根据一些实施例的密封环的截面图。
图18示出了根据一些实施例的再分布线的截面图。
图19至图22示出了根据一些实施例的一些封装件的截面图。
图23示出了根据一些实施例的重构晶圆的平面图。
图24示出了根据一些实施例的重构晶圆的划线的截面图。
图25示出了根据一些实施例的封装件的平面图。
图26示出了根据一些实施例的用于形成封装件的工艺流程。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实施例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等间隔相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外，间隔相对术语旨在包括器件在使用或操作中的不同方位。器件可以以其它方式定向(旋转90度或在其它方位上)，而本文使用的间隔相对描述符可以同样地作出相应的解释。
根据各个实施例，提供了包括空气通道的封装件及其形成方法。根据一些实施例，示出了形成集成扇出(InFO)封装件的中间阶段。讨论了一些实施例的一些变型。贯穿各个视图和示例性实施例，相同的参考标号用于指示相同的元件。
将参照特定上下文(即，包括空气通道的封装件)描述实施例。本文讨论的实施例将提供实例以使得能够制造或使用本发明的主题，并且本领域普通技术人员将容易理解，可以进行修改的同时仍在不同实施例的预期范围内。下图中相同的参考数字和字符表示相同的组件。尽管方法实施例可以被讨论为以特定顺序实施，但是其它方法实施例可以以任何逻辑顺序实施。
图1至图16示出了根据一些实施例的封装件的形成中的中间阶段的截面图。在图26所示的工艺流程300中还示意性地示出了图1至图16所示的工艺。
参考图1，提供了载体20，并且释放膜22涂覆在载体20上。载体20由透明材料形成，并且可以是玻璃载体、陶瓷载体、有机载体等。载体20可以具有圆形的俯视形状，并且可以具有硅晶圆的尺寸。释放膜22与载体20的顶面物理接触。释放膜22可以由光热转换(LTHC)涂层材料形成。释放膜22可以通过涂覆施加到载体20上。根据本发明的一些实施例，LTHC涂层材料能够在光/辐射(诸如激光束)的热量下分解，并且因此可以从形成在其上的结构释放载体20。
根据一些实施例，也如图1所示，在LTHC涂层材料22上形成聚合物缓冲层24。聚合物缓冲层24可以由聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)或其它适用的聚合物形成。金属晶种层25例如通过物理汽相沉积(PVD)形成在聚合物缓冲层24上方。金属晶种层25可以与聚合物缓冲层24物理接触。根据本发明的一些实施例，金属晶种层25包括钛层和位于钛层上方的铜层。根据本发明的可选实施例，金属晶种层25包括接触缓冲介电层24的铜层。
图2至图4示出了聚合物缓冲层24上方的金属杆32的形成。相应的工艺示出为图26所示的工艺流程中的工艺302。在整个说明书中，金属杆32可以可选地称为通孔32，因为金属杆32穿透随后分配的密封剂。
如图2所示，在金属晶种层25上方形成光刻胶26。然后，使用光刻掩模(未示出)对光刻胶26实施曝光工艺。在随后的显影工艺之后，在光刻胶26中形成开口28，使得金属晶种层25的一些部分通过开口28暴露。
下一步，如图3所示，通过在开口28中镀金属材料来形成金属杆32。镀的金属材料可以包括铜或铜合金。金属杆32的顶面低于光刻胶26的顶面，使得金属杆32由开口28限制。金属杆32可具有基本垂直和直的边缘。可选地，金属杆32在截面图中可以具有沙漏计时器形状，其中，金属杆32的中间部分比相应的顶部和底部窄。
在随后的步骤中，去除光刻胶26，并且暴露下面的金属晶种层25的部分。然后，在例如多个各向异性和/或各向同性蚀刻工艺中的蚀刻步骤中去除金属晶种层25的暴露部分。因此，剩余的晶种层25的边缘与金属杆32的相应的上面的部分基本共末端。所得的金属杆32在图4中示出。在整个说明书中，金属晶种层25的剩余部分被认为是金属杆32的一部分，并且未单独示出。金属杆32的俯视形状包括但不限于圆形、矩形、六边形、八边形等。在形成金属杆32之后，暴露聚合物缓冲层24。
图5示出了器件管芯36的放置和附接。相应的工艺示出为图26所示的工艺流程中的工艺304。器件管芯36可以通过为粘合剂膜的管芯附接膜(DAF)38附接至聚合物缓冲层24。在将器件管芯36放置在聚合物缓冲层24上之前，可以将DAF 38预附接至器件管芯36上。器件管芯36可以包括半导体衬底，该半导体衬底具有与DAF 38物理接触的背面(面向下的表面)。器件管芯36可以包括位于半导体衬底的正面(面向上的表面)处的集成电路器件(诸如有源器件，其包括例如未示出的晶体管)。根据本发明的一些实施例，器件管芯36是逻辑管芯，其可以是中心处理单元(CPU)管芯、图形处理单元(GPU)管芯、移动应用程序管芯、微控制单元(MCU)管芯、输入输出(IO)管芯、基带(BB)管芯、应用处理器(AP)管芯等。由于载体20处于晶圆级，尽管示出了一个器件管芯36，但是多个相同的器件管芯36放置在聚合物缓冲层24上方，并且可以被分配为包括多行和多列的阵列。
根据一些实施例，金属柱42(诸如铜柱)预先形成为器件管芯36的一部分，并且金属柱42电耦接至器件管芯36中的诸如晶体管(未示出)的集成电路器件。根据本发明的一些实施例，诸如聚合物的介电材料填充相邻金属柱42之间的间隙以形成顶部介电层44。顶部介电层44还可以包括覆盖和保护金属柱42的部分。根据本发明的一些实施例，聚合物层44可以由PBO、聚酰亚胺等形成。
下一步，如图6所示，将器件管芯36和金属杆32密封在密封剂48中。相应的工艺示出为图26所示的工艺流程中的工艺306。密封剂48填充相邻金属杆32之间的间隙以及金属杆32和器件管芯36之间的间隙。密封剂48可以包括模塑料、模塑底部填充物、环氧树脂和/或树脂。密封剂48的顶面高于金属柱42的顶端。当由模塑料形成时，密封剂48可以包括基底材料，其可以是聚合物、树脂、环氧树脂等的基底材料以及位于该基底材料中的填料颗粒。填料颗粒可以是SiO2、Al2O3、二氧化硅等的介电颗粒，并且可以具有球形形状。而且，球形填料颗粒可以具有多个不同的直径。密封剂48中的填料颗粒和基底材料都可以与聚合物缓冲层24物理接触。
在随后的步骤中，实施诸如化学机械抛光(CMP)工艺或机械研磨工艺的平坦化工艺以减薄密封剂48和介电层44，直至暴露金属杆32和金属柱42。相应的工艺示出为图26所示的工艺流程中的工艺306。由于平坦化工艺，金属杆32的顶端与金属柱42的顶面基本齐平(共面)，并且与密封剂48的顶面基本共面。金属杆32在随后的段落中可选地称为通孔32，因为它们穿过密封剂48。
图7至图13示出了前侧再分布结构的形成。图7和图8示出了第一层再分布线(RDL)和相应的介电层的形成。参考图7，形成介电层50。相应的工艺示出为图26所示的工艺流程中的工艺308。根据本发明的一些实施例，介电层50由诸如PBO、聚酰亚胺等的聚合物形成。形成方法包括以可流动形式涂覆介电层50，并且然后固化介电层50。根据本发明的可选实施例，介电层50由诸如氮化硅、氧化硅等的无机介电材料形成。形成方法可以包括涂覆、化学汽相沉积(CVD)、原子层沉积(ALD)、等离子体增强化学汽相沉积(PECVD)或其它适用的沉积方法。然后通过图案化介电层50形成通孔开口52。相应的工艺示出为图26所示的工艺流程中的工艺308。根据其中介电层50由诸如PBO或聚酰亚胺的光敏材料形成的一些实施例，开口52的形成涉及使用光刻掩模(未示出)的曝光工艺以及显影工艺。通孔32和金属柱42通过通孔开口52暴露。
除了通孔开口52之外，还形成开口53和可能的开口54。根据本发明的一些实施例，实施晶圆级封装工艺，并且将多个器件管芯36放置在载体20上，并且以常规工艺封装以形成重构晶圆100，该晶圆最终被锯切成多个封装件102，如图23所示。图23示出了根据一些实施例的重构晶圆100的俯视图。在重构晶圆100中，以阵列形式形成多个封装件102，每个封装件102包括器件管芯36以及对应的通孔32和RDL等。划线110形成为将封装件102分开的栅格。如图7所示，通孔32和器件管芯36所在的区域被标记为内部封装区域102’，其由外围区域104围绕。外围区域104形成环绕相应封装件的内部封装区域102’的环形区域(在相应封装件的俯视图中)。形成在外围区域104中的每个部件可以形成环绕内封装区域102’的环。示例性的环形外围区域104在图23中示出，并且其它封装件102也具有相同的环形外围区域，尽管未示出。
在图7中，左侧划线110仅示出相应划线110的一半(右半部分)，而未示出相应划线110的左半部分。划线110的左半部分中的部件可以反映将在后续工艺中形成的部件。可以从图23中的参考截面SC-SC(也在图25中示出)获得图7中的截面图。图24示意性地示出了示例性划线110的截面图，同时示出了左半部分和右半部分。将在随后的段落中讨论如图24所示的形成在划线110中的部件。
再次参考图7，根据本发明的一些实施例，每个开口53形成为延伸成邻接相应封装件的边缘的四个划线110(图23)。因此，开口53形成环形开口。因此，从图23中可以看出，将存在多个开口53(未示出)，每个开口形成环绕相应封装区域102’/104的环。如图24所示，介电层50的一部分50’可以留在相应划线110的中心。划线110中的部分50’被连接为介电栅格。介电栅格将开口53彼此分隔开。此外，开口54也将形成环绕内部封装区域102’的环，这可以从图7和图23中实现。
下一步，参考图8，形成金属环56(也参考图24)、金属环58和RDL60。相应的工艺示出为图26所示的工艺流程中的工艺310。形成工艺可以包括在图7所示的结构上形成毯式金属晶种层(未示出)，形成并且图案化镀掩模(诸如光刻胶)以露出金属晶种层的一些部分，在镀掩模的开口中镀金属环56、金属环58和RDL60，去除镀掩模，并且蚀刻金属晶种层的先前由镀掩模覆盖的部分。根据本发明的一些实施例，金属晶种层包括钛层和位于钛层上方的铜层。金属晶种层的形成可以包括例如PVD。金属晶种层延伸至开口52、53和54中，并且接触通孔32和金属柱42。根据本发明的一些实施例，镀材料包括铜或铜合金。镀可以包括电化学镀或化学镀。
金属环56、金属环58和RDL60中的每个均可以包括位于介电层50中的通孔部分和位于介电层50上方的金属迹线部分。RDL60的通孔部分与金属柱42或通孔32接触。金属环56和金属环58的通孔部分与密封剂48的顶面接触。
参考图9，形成介电层66。相应的工艺示出为图26所示的工艺流程中的工艺312。介电层66可以使用选自用于形成介电层50的同一组候选材料中的材料形成，该候选材料可以包括PBO、聚酰亚胺、BCB或其它有机或无机材料。然后，例如通过曝光和显影工艺在介电层66中形成开口68、69和70。介电层66覆盖RDL60。RDL60、金属环58和金属环56的一些部分分别通过开口68、69和70暴露。开口70延伸至划线110和外围区域104中。
根据一些实施例，介电层66的边缘从介电层50的边缘凹进(朝向相应封装件的中心线102C)距离D1。根据一些实施例，凹进距离D1在约2μm和约15μm之间的范围内，并且可以在8μm左右。采用凹进来改进不同介电层之间的重叠的工艺窗口。介电层66可以覆盖金属环56的边缘部分，而金属环56的外部部分暴露。
参考图10，形成RDL72、金属环74和金属环76。相应的工艺示出为图26所示的工艺流程中的工艺314。RDL72、金属环74和金属环76的形成工艺可以与RDL60的形成基本相同。RDL72还包括经由介电层66中的通孔开口延伸至接触RDL60的通孔部分，以及直接位于介电层66上方的金属迹线部分，并且因此是金属环74和金属环76。RDL72、金属环74和金属环76的形成可以与RDL60、金属环58和金属环56的形成工艺类似。
图11示出了介电层上方的介电层78的形成。相应的工艺示出为图26所示的工艺流程中的工艺316。下一步，在介电层78中形成开口79、80和81。开口81延伸至划线110和外围区域104中。介电层78可以由选自用于形成介电层50和66的同一组候选材料中的材料形成。根据一些实施例，介电层78的边缘从介电层66的相应边缘朝向中心线102C凹进距离D2。根据一些实施例，凹进距离D2在约2μm和约15μm之间的范围内，并且可以在8μm左右。介电层78可以覆盖金属环76的边缘部分，而金属环76的外部部分暴露。
参考图12，形成RDL82、金属环84和金属环86。相应的工艺示出为图26所示的工艺流程中的工艺318。RDL82、金属环84和金属环86的形成工艺可以与RDL60、金属环58和金属环56的形成工艺基本上相同。RDL82、金属环84和金属环86可以由包括铝、铜、钨或它们的合金的金属或金属合金形成。应该理解，尽管在所示的示例性实施例中形成了三个RDL层，但是封装件可以具有其它数量的RDL层，诸如一层、两层或多于三层。
图13示出了介电层88的形成。相应的工艺示出为图26所示的工艺流程中的工艺320。介电层88可以由选自用于形成介电层50、66和78的同一组候选材料中的材料形成。例如，可以使用PBO、聚酰亚胺或BCB形成介电层88。在介电层88中形成开口(由UBM 90和电连接件92占据)以暴露下面的金属焊盘，这些金属焊盘是RDL82的一部分。进一步形成延伸至划线110和外围区域104中的开口89。根据一些实施例，介电层88的边缘从介电层78的边缘朝向中心线102C凹进距离D3。根据一些实施例，凹进距离D3在约2μm和约15μm之间的范围内，并且可以在8μm左右。介电层88可以覆盖金属环86的边缘部分，而金属环86的外部部分暴露。
图13还示出了根据一些实施例的凸块下金属(UBM)90和电连接件92的形成。相应的工艺示出为图26所示的工艺流程中的工艺322。根据本发明的一些实施例，UBM 90形成为延伸至介电层88中的开口中，以接触RDL82中的金属焊盘。UBM 90可以由镍、铜、钛或它们的多层形成。根据一些实施例，UBM 90包括钛层和位于钛层上方的铜层。
然后，根据一些实施例形成电连接件92。电连接件92的形成可以包括将焊球放置在UBM 90的暴露部分上，并且然后使焊球回流。根据本发明的可选实施例，电连接件92的形成包括实施镀步骤以在UBM 90上方形成焊料层，并且然后使焊料层回流。电连接件92还可以包括非焊料金属柱，或者金属柱和位于非焊料金属柱上方的焊料盖，它们也可以通过镀形成。在整个说明书中，包括介电缓冲层24和上面的结构的组合的结构称为重构晶圆100。
在图13所示的结构中，密封环120形成在外围区域104中，并且包括金属环58、74和84，它们连接在一起以形成集成密封环。密封环120中环绕RDL60、72和82。根据一些实施例，密封环120电接地或电浮置。
示意性地示出了图13中所示的密封环120。图17示出了密封环120的更详细的视图，该密封环包括金属环58、74和84。金属环58、74和84的上部堆叠在相应下面的金属环的迹线部分上。密封环120可以占据宽度W1，该宽度W1例如可以在约30μm和约50μm之间的范围内。
图18示出了RDL的更详细的视图，该RDL可以是RDL60、72和82中的任何一个。RDL包括向下延伸至下面的介电层中的通孔部分以及位于相应的介电层上方的迹线部分。
同样，如图13所示，划线110中的开口形成空气通道122。重构晶圆100包括互连的多个空气通道122，以形成栅格。空气通道122延伸至划线110中，并且可以延伸至外围区域104中。根据一些实施例，空气通道122的上部比相应的下面部分更宽。此外，金属环56、76和86互连以形成集成金属环，该集成金属环延伸至划线110中，并且可以延伸至外围区域104中。
下一步，参考图14，将重构晶圆100附接至框架124，其中，电连接件92面向并且附接至框架124中的带。然后，例如，通过将激光束投射在释放膜22上，将重构晶圆100从载体20上卸下(图13)。释放膜22在激光束的热量下分解。在图14中，空气通道122具有将空气从框架124和重构晶圆100之间的空间中排出的功能。在随后的工艺中，例如，在某些清洁工艺中，可能会产生等离子体，并且空气通道可用于传导出除气气体，使得重构晶圆100不会从框架124剥离。如果未形成空气通道，则可能需要实施预开槽工艺以形成空气通道。预开槽工艺会产生额外的制造成本。作为比较，根据本发明的实施例形成的空气通道不会产生额外的制造成本，因此可以节省预开槽工艺的成本。
下一步，参考图15，例如通过激光钻孔在介电缓冲层24中形成开口126。当通孔32包括钛层，并且钛层来自金属晶种层25(图2)时，可以通过蚀刻去除钛层，从而暴露通孔32中的铜。
然后可以在管芯锯切工艺中分割重构晶圆100。相应的工艺示出为图26所示的工艺流程中的工艺324。例如，刀片可锯切划线110以将晶圆100分割成多个相同的封装件102，每个封装件具有根据一些实例所示的结构。示出了位于划线110中的切口128。由于工艺原因，切口128可出现在划线110的任何位置，并且可比图15所示的向左或向右移动。例如，虚线130示出了切口128的右边缘的可能位置。在管芯锯切工艺中，可以切穿或可以不切穿金属环56，并且在管芯锯切工艺中，可以不切穿金属环76和86。
图25示出了封装件102的平面图(俯视图或仰视图)。根据本发明的一些实施例，每个金属环56包括四个侧，四个侧中的每个平行于相应封装件102的四个边缘102A中的一个。可以切穿金属环56的一个、两个、三个或全部四个侧。因此，在所得的封装件102中，金属环56可以延伸至边缘102A中的一个、两个、三个或四个。另一方面，在管芯锯切工艺中没有锯切金属环76和86。金属环56、76和86可以连接以形成集成金属环，其可以电接地或电浮置。虚线矩形122A示出了空气通道122的内部边界，其中，空气通道122还形成了从虚线矩形122A延伸至封装件102的相应边缘102A的环。虚线矩形76A和86A分别示出了金属环76和86的外边界的位置。封装件102的中心处于102C。
图16示出了封装件102通过焊料区域92接合至封装组件134。根据本发明的一些实施例，封装组件134是封装衬底，其可以是无芯衬底或有芯衬底。根据其它实施例，封装组件134是印刷电路板、封装件等。底部填充物136可以分配在封装件102和封装组件134之间。底部填充物136可以包括基底材料，其可以是聚合物、树脂、环氧树脂等，以及位于该基底材料中的填料颗粒。填料颗粒可以是SiO2、Al2O3、二氧化硅等的介电颗粒，并且可以具有直径相同或不同的球形形状。封装件102也可以通过焊料区域206接合至封装件200。根据一些实施例，封装件200包括器件管芯202和衬底204。管芯202可以是诸如动态随机存取存储器(DRAM)管芯的存储器管芯。底部填充物208可以设置在封装件102和封装件200之间。图16中所得的封装件称为封装件140。
图19至图22示出了根据本发明的一些实施例的封装件140的截面图。除非另有说明，否则这些实施例中的组件的材料和形成方法与相同的组件基本相同，在图1至图16所示的实施例中，它们由相同的参考标号表示。因此，可以在对图1至图16所示的实施例的讨论中找到关于图19至图22所示的组件的形成工艺和材料的细节。
图19示出了根据一些实施例的封装件140。除了未形成金属环56、76和86(图16)之外，这些实施例与图16所示的实施例类似。因此，介电层66、78和88暴露于空气通道122，该空气通道122由底部填充物136填充。底部填充物136也可以与密封剂48接触。
图20示出了根据一些实施例的封装件140。除了未形成密封环120(图16)以外，这些实施例与图16所示的实施例类似。金属环56、76和86互连，并且因此用作密封环。由金属环56、76和86形成的密封环可以电接地或电浮置。由于未形成密封环120，因此节省了用于形成密封环120的芯片面积。
图21示出了根据一些实施例的封装件140。除了介电层88延伸为也覆盖并且接触金属环56和76之外，这些实施例与图16所示的实施例类似。
图22示出了根据一些实施例的封装件140。除了未形成密封环120(图21)之外，这些实施例与图21所示的实施例类似。金属环56、76和86互连，并且因此用作密封环。由金属环56、76和86形成的密封环可以电接地或电浮置。由于未形成密封环120，因此节省了用于形成密封环120的芯片面积。
在上面示出的实施例中，根据本发明的一些实施例讨论了一些工艺和部件。也可以包括其它部件和工艺。例如，可以包括测试结构以辅助3D封装件或3DIC器件的验证测试。测试结构可以包括例如形成在再分布层中或衬底上的测试焊盘，其允许使用探针和/或探针卡等对3D封装件或3DIC测试。验证测试可以对中间结构以及最终结构实施。另外，本文公开的结构和方法可以与结合已知良好管芯的中间验证的测试方法结合使用，以增加良率并且降低成本。
本发明的实施例具有一些有利特征。通过利用现有的介电形成工艺和RDL形成工艺来形成空气通道，节省了形成空气通道的制造成本(例如，使用激光的预开槽)。由于可以通过在封装件的边缘部分上形成连接的金属环来形成密封环，因此还可以节省原本保留用于形成密封环的芯片面积。
根据本发明的一些实施例，方法包括：将第一器件管芯和第二器件管芯密封在密封剂中；在第一器件管芯、第二器件管芯和密封剂上方形成第一介电层；图案化第一介电层以形成第一开口和第二开口，其中，第一器件管芯和第二器件管芯的导电部件暴露于第一开口，并且其中，第二开口延伸至第一器件管芯和第二器件管芯之间的划线中；形成延伸至第一开口中以电耦接至第一器件管芯和第二器件管芯的第一再分布线；在第一再分布线上方形成第二介电层；图案化第二介电层以形成第三开口和第四开口，其中，第一再分布线的一部分暴露于第三开口，并且第四开口延伸至划线中；形成延伸至第三开口中以电耦接至第一再分布线的第二再分布线；并且实施管芯锯切工艺以分别将第一器件管芯和第二器件管芯分离为第一封装件和第二封装件，其中，管芯锯切工艺的切口穿过划线。在实施例中，第四开口比第二开口宽。在实施例中，第一器件管芯和第二器件管芯形成重构晶圆的一部分，并且该方法还包括将重构晶圆附接至框架，其中，第二开口和第四开口具有至少剩余的部分以形成空气通道的一部分，并且空气通道位于密封剂和框架之间。在实施例中，该方法还包括，在用于形成第一再分布线的相同工艺中，形成延伸至划线中的第一金属环，其中，第一金属环环绕第一封装件的内部。在实施例中，在管芯锯切工艺中，切穿第一金属环。在实施例中，在管芯锯切工艺之后，第一金属环形成环绕第一封装件的内部的堆叠金属环的一部分。在实施例中，该方法还包括，在用于形成第二再分布线的相同工艺中，形成与第一金属环连接的第二金属环，其中，整个第二金属环在划线的外部。在实施例中，该方法还包括将第一封装件接合至封装组件；以及将底部填充物设置在第一封装件和封装组件之间的间隙中，其中，底部填充物设置在第二开口和第四开口的至少一部分中。
根据本发明的一些实施例，方法包括：形成重构晶圆，包括将器件管芯密封在密封剂中；在器件管芯和密封剂上方形成第一介电层；形成延伸至第一介电层中以电耦接至器件管芯的第一多条再分布线；并且在用于形成第一多条再分布线的常规工艺中，形成第一金属环，其中，第一金属环环绕第一多条再分布线，并且第一金属环延伸至重构晶圆的划线中；以及沿重构晶圆的划线实施管芯锯切工艺，以将封装件与重构晶圆分离，其中，封装件包括器件管芯和至少一部分第一金属环。在实施例中，在管芯锯切工艺中，切穿第一金属环。在实施例中，该方法还包括在第一介电层和第一多条再分布线上方形成第二介电层；形成延伸至第二介电层中的第二多条再分布线，以与第一多条再分布线连接；以及在用于形成第二多条再分布线的相同工艺中形成第二金属环，其中，第二金属环环绕第二多条再分布线。在实施例中，在管芯锯切工艺中，不切穿第二金属环。在实施例中，第二金属环连接至第一金属环以形成集成密封环的一部分。在实施例中，封装件在集成密封环和第一多个再分布线之间没有密封环。在实施例中，该方法还包括形成延伸至第一介电层中的附加密封环，其中第一金属环环绕附加密封环。
根据本发明的一些实施例，集成电路器件的封装件包括：器件管芯；将器件管芯密封在其中的密封剂；位于密封剂上面的多个介电层，其中，多个介电层的边缘与封装件的边缘间隔开，并且多个介电层的上层的边缘比多个介电层的相应下层的边缘向封装件的中心凹进更多；以及多个再分布线，延伸至多个介电层中以电耦接至器件管芯。在实施例中，封装件还包括金属环，其中，金属环环绕多个介电层和多条再分布线。在实施例中，金属环包括底部环，该底部环至少延伸至封装件的边缘；以及上部环，位于底部环上方并且与底部环连接，其中，上部环与封装件的边缘间隔开。在实施例中，封装件还包括与多个介电层的边缘间隔开的附加密封环，其中，金属环环绕附加密封环。在实施例中，封装件还包括底部填充物，该底部填充物环绕多个介电层并且与多个介电层处于相同的层级，其中，底部填充物与密封剂的边缘部分重叠。
上面概述了若干实施例的特征，使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解，它们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中它们可以做出多种变化、替换以及改变。

Claims (10)

1.一种形成集成电路器件的封装件的方法，包括：
将第一器件管芯和第二器件管芯密封在密封剂中；
在所述第一器件管芯、所述第二器件管芯和所述密封剂上方形成第一介电层；
图案化所述第一介电层以形成第一开口和第二开口，其中，所述第一器件管芯和所述第二器件管芯的导电部件暴露于所述第一开口，并且其中，所述第二开口延伸至所述第一器件管芯和所述第二器件管芯之间的划线中；
形成延伸至所述第一开口中以电耦接至所述第一器件管芯和所述第二器件管芯的第一再分布线；
在所述第一再分布线上方形成第二介电层；
图案化所述第二介电层以形成第三开口和第四开口，其中，所述第一再分布线的部分暴露于所述第三开口，并且所述第四开口延伸至所述划线中；
形成延伸至所述第三开口中以电耦接至所述第一再分布线的第二再分布线；以及
实施管芯锯切工艺，以分别将所述第一器件管芯和所述第二器件管芯分离为第一封装件和第二封装件，其中，所述管芯锯切工艺的切口穿过所述划线。
2.根据权利要求1所述的方法，其中，所述第四开口比所述第二开口宽。
3.根据权利要求1所述的方法，其中，所述第一器件管芯和所述第二器件管芯形成重构晶圆的一部分，并且所述方法还包括将所述重构晶圆附接至框架，其中，所述第二开口和所述第四开口具有至少剩余的部分以形成空气通道的一部分，并且所述空气通道位于所述密封剂和所述框架之间。
4.根据权利要求1所述的方法，还包括，在用于形成所述第一再分布线的相同工艺中，形成延伸至所述划线中的第一金属环，其中，所述第一金属环环绕所述第一封装件的内部。
5.根据权利要求4所述的方法，其中，在所述管芯锯切工艺中，切穿所述第一金属环。
6.根据权利要求5所述的方法，其中，在所述管芯锯切工艺之后，所述第一金属环形成环绕所述第一封装件的内部的堆叠金属环的一部分。
7.根据权利要求4所述的方法，还包括，在用于形成所述第二再分布线的相同工艺中，形成与所述第一金属环连接的第二金属环，其中，整个所述第二金属环位于所述划线的外部。
8.根据权利要求1所述的方法，还包括：
将所述第一封装件接合至封装组件；以及
将底部填充物设置在所述第一封装件和所述封装组件之间的间隙中，其中，所述底部填充物设置在所述第二开口和所述第四开口的至少部分中。
9.一种形成集成电路器件的封装件的方法，包括：
形成重构晶圆，包括：
将器件管芯密封在密封剂中；
在所述器件管芯和所述密封剂上方形成第一介电层；
形成延伸至所述第一介电层中以电耦接至所述器件管芯的第一多条再分布线；以及
在用于形成所述第一多条再分布线的常规工艺中形成第一金属环，其中，所述第一金属环环绕所述第一多条再分布线，并且所述第一金属环延伸至所述重构晶圆的划线中；以及
沿所述重构晶圆的划线实施管芯锯切工艺以从所述重构晶圆分离封装件，其中，所述封装件包括所述器件管芯和至少部分所述第一金属环。
10.一种集成电路器件的封装件，所述封装件包括：
器件管芯；
密封剂，将所述器件管芯密封在所述密封剂中；
多个介电层，位于所述密封剂上面，其中，所述多个介电层的边缘与所述封装件的边缘间隔开，并且所述多个介电层的上层的边缘比所述多个介电层的相应下层的边缘朝向所述封装件的中心凹进更多；以及
多条再分布线，延伸至所述多个介电层中以电耦接至所述器件管芯。
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