TW202046447A - 積體電路元件的封裝體及其形成方法 - Google Patents

積體電路元件的封裝體及其形成方法 Download PDF

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TW202046447A
TW202046447A TW108133565A TW108133565A TW202046447A TW 202046447 A TW202046447 A TW 202046447A TW 108133565 A TW108133565 A TW 108133565A TW 108133565 A TW108133565 A TW 108133565A TW 202046447 A TW202046447 A TW 202046447A
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metal ring
die
ring
forming
metal
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TW108133565A
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TWI707428B (zh
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李宛諭
曾華偉
黃立賢
胡毓祥
林岳霆
林強
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台灣積體電路製造股份有限公司
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Abstract

一種方法，包含形成重構晶圓，形成重構晶圓包含：將元件晶粒包封於包封體中；在元件晶粒及包封體上方形成介電層；形成延伸至介電層中以與元件晶粒電耦接的多個重佈線；以及在用於形成多個重佈線的共同製程中形成金屬環。金屬環環繞多個重佈線，且金屬環延伸至重構晶圓的多個切割道中。沿重構晶圓的多個切割道執行晶粒鋸切製程以將封裝體從重構晶圓分離。封裝體包含元件晶粒及金屬環的至少一部分。

Description

於封裝製程中形成空氣通道
隨著半導體技術的發展，半導體晶片/晶粒正變得愈來愈小。同時，需要將更多功能整合至半導體晶粒中。因此，半導體晶粒需要具有封裝於較小面積中的數目愈來愈多的I/O襯墊，且I/O襯墊的密度隨時間而快速增大。因此，半導體晶粒的封裝變得愈加困難，此不利地影響封裝體的良率。
習知封裝技術可劃分成兩種類別。在第一類別中，封裝晶圓上的晶粒，隨後鋸切晶粒。此封裝技術具有一些有利特徵，諸如較高處理量及較低成本。另外，需要較少底填充料或模製化合物。然而，此封裝技術亦有缺點。由於晶粒的大小正變得愈來愈小，且各別封裝體可僅為扇入型封裝體，其中將每一晶粒的I/O襯墊限制於位於各別晶粒的表面的正上方的區域。隨著晶粒的面積受限，I/O襯墊的數目因I/O襯墊的間距限制而受限。若襯墊的間距減小，則可出現焊橋（solder bridges）。此外，在固定球大小要求下，焊球必須具有一定大小，此轉而限制可封裝於晶粒的表面上的焊球的數目。
在封裝的另一類別中，自晶圓鋸切晶粒，隨後封裝晶粒。此封裝技術的有利特徵在於形成扇出型封裝體的可能性，此意謂可將晶粒上的I/O襯墊重佈至比晶粒大的面積，且因此可增大形成於晶粒的表面上的I/O襯墊的數目。此封裝技術的另一有利特徵在於封裝「良裸晶粒（known-good-dies）」且捨棄有缺陷的晶粒，且因此不在有缺陷的晶粒上浪費成本及精力。
以下揭露內容提供用於實施本發明的不同特徵的多個不同實施例或實例。以下描述組件及配置的具體實例以便簡化本揭露內容。當然，這些組件及配置僅僅為實例且並不意欲為限制性的。舉例而言，在以下描述中，在第二特徵上方或在第二特徵上形成第一特徵可包含第一特徵與第二特徵直接接觸地形成的實施例，且亦可包含在第一特徵與第二特徵之間可形成有額外特徵使得第一特徵與第二特徵可不直接接觸的實施例。此外，本揭露內容可在各種實例中重複圖式元件符號及/或字母。此重複是為了簡單及清楚起見，且本身並不指示所論述的各種實施例及/或組態之間的關係。
另外，為易於描述，本文中可使用諸如「在...之下」、「在…下方」、「下部」、「上覆」、「上部」等的空間相對術語來描述如圖式中所說明的一個元件或特徵與另一（一些）元件或特徵的關係。除圖式中所描繪的定向之外，空間相對術語亦意欲涵蓋元件在使用或操作中的不同定向。設備可以其他方式定向（旋轉90度或處於其他定向），且本文中所使用的空間相對描述詞可同樣相應地加以解釋。
根據各種實施例提供一種包含空氣通道的封裝體及形成所述封裝體的方法。根據一些實施例說明形成積體扇出型（Integrated Fan-Out；InFO）封裝體的中間階段。論述一些實施例的一些變化。貫穿各視圖及說明性實施例，相同的圖式元件符號用以指代相同元件。
將針對具體內容背景（即，包含空氣通道的封裝體）描述實施例。本文中所論述的實施例將提供使得能夠製備或使用本揭露內容的主題的實例，且所屬技術領域中具有通常知識者將易於理解在屬於不同實施例的所設想範疇內的情況下可進行的修改。以下圖式中的相同圖式元件符號及字符指的是相同組件。儘管方法實施例可論述為以特定次序執行，但其他方法實施例可以任何邏輯次序執行。
圖1至圖16說明根據一些實施例的封裝體的形成中的中間階段的橫截面視圖。亦在圖26中所展示的製程流程300中示意性地說明圖1至圖16中所展示的製程。
參看圖1，提供載體20，且將釋放膜22塗佈於載體20上。載體20由透明材料形成，且可為玻璃載體、陶瓷載體、有機載體或類似者。載體20可具有圓形俯視圖形狀，且可具有矽晶圓的大小。釋放膜22與載體20的頂部表面實體接觸。釋放膜22可由光-熱轉換（Light-To-Heat-Conversion；LTHC）塗佈材料形成。釋放膜22可經由塗佈來塗覆至載體20上。根據本揭露內容的一些實施例，LTHC塗佈材料在光/輻射（諸如雷射束）的熱量下能夠分解，且因此可自其上形成的結構釋放載體20。
根據一些實施例，如亦在圖1中所展示，聚合物緩衝層24形成於LTHC塗佈材料（釋放膜22）上。聚合物緩衝層24可由聚苯并噁唑（polybenzoxazole；PBO）、聚醯亞胺、苯并環丁烯（benzocyclobutene；BCB）或另一可適用的聚合物形成。金屬晶種層25例如經由物理氣相沈積（Physical Vapor Deposition；PVD）形成於聚合物緩衝層24上方。金屬晶種層25可與聚合物緩衝層24實體接觸。根據本揭露內容的一些實施例，金屬晶種層25包含鈦層及鈦層上方的銅層。根據本揭露內容的替代性實施例，金屬晶種層25包含接觸緩衝介電層（聚合物緩衝層24）的銅層。
圖2至圖4說明在聚合物緩衝層24上方形成金屬柱32。將各別製程說明為圖26中所展示的製程流程中的製程302。貫穿本說明書，金屬柱32替代地被稱作穿孔32，此是由於金屬柱32穿透隨後施配的包封體。
如圖2中所展示，光阻26形成於金屬晶種層25上方。隨後使用微影罩幕（未展示）對光阻26執行曝光製程（light-exposure process）。在後續顯影製程之後，開口28形成於光阻26中，使得經由開口28暴露金屬晶種層25的一些部分。
接下來，如圖3中所展示，藉由在開口28中鍍覆金屬材料來形成金屬柱32。被鍍覆的金屬材料可包含銅或銅合金。金屬柱32的頂部表面低於光阻26的頂部表面，使得金屬柱32受開口28限制。金屬柱32可具有實質上垂直且筆直的邊緣。可替代地，金屬柱32在橫截面圖中可具有沙漏計時器形狀，其中金屬柱32的中間部分比各別頂部部分及底部部分窄。
在後續步驟中，移除光阻26，且暴露金屬晶種層25的下伏部分。隨後在蝕刻步驟中（例如在多個非等向性及/或等向性蝕刻製程中）移除金屬晶種層25的暴露部分。因此，剩餘晶種層25的邊緣實質上與金屬柱32的各別上覆部分同邊界。所得金屬柱32說明於圖4中。貫穿本說明書，金屬晶種層25的剩餘部分被視為金屬柱32的部分，而不單獨說明。金屬柱32的俯視圖形狀包含但不限於圓形形狀、矩形、六邊形、八邊形以及類似者。在形成金屬柱32之後，暴露聚合物緩衝層24。
圖5說明元件晶粒36的置放/貼合。將各別製程說明為圖26中所展示的製程流程中的製程304。元件晶粒36經由作為黏合膜的晶粒貼合膜（Die-Attach Film；DAF）38來貼合至聚合物緩衝層24。DAF 38可預先貼合於元件晶粒36上，隨後元件晶粒36被置放於聚合物緩衝層24上。元件晶粒36可包含具有與DAF 38實體接觸的背表面（面朝下的表面）的半導體基底。元件晶粒36可包含半導體基底的前表面（面朝上的表面）處的積體電路元件（諸如包含電晶體的主動元件，例如未展示）。根據本揭露內容的一些實施例，元件晶粒36是邏輯晶粒，所述邏輯晶粒可為中央處理單元（Central Processing Unit；CPU）晶粒、圖形處理單元（Graphic Processing Unit；GPU）晶粒、行動應用晶粒、微控制單元（Micro Control Unit；MCU）晶粒、輸入-輸出（input-output；IO）晶粒、基頻（BaseBand；BB）晶粒、應用處理器（Application processor；AP）晶粒或類似者。由於載體20處於晶圓級，因此儘管說明一個元件晶粒36，但多個相同的元件晶粒36被置放於聚合物緩衝層24上方，且可被分配為包含多列及多行的陣列。
根據一些實施例，金屬支柱42（諸如，銅支柱）預形成為元件晶粒36的部分，且金屬支柱42電耦接至積體電路元件，諸如元件晶粒36中的電晶體（未展示）。根據本揭露內容的一些實施例，介電材料（諸如聚合物）填充相鄰金屬支柱42之間的間隙以形成頂部介電層44。頂部介電層44亦可包含覆蓋且保護金屬支柱42的部分。根據本揭露內容的一些實施例，聚合物層（頂部介電層44）可由PBO、聚醯亞胺或類似者形成。
接下來，如圖6中所展示，將元件晶粒36及金屬柱32包封於包封體48中。將各別製程說明為圖26中所展示的製程流程中的製程306。包封體48填充相鄰金屬柱32之間的間隙及金屬柱32與元件晶粒36之間的間隙。包封體48可包含模製化合物、模製底填充料、環氧樹脂及/或樹脂。包封體48的頂部表面高於金屬支柱42的頂端。當包封體48由模製化合物形成時，所述包封體可包含基礎材料及基礎材料中的填充劑粒子，所述基礎材料可以是聚合物、樹脂、環氧樹脂或類似者。填充劑粒子可以是SiO2 、Al2 O3 、二氧化矽或類似者的介電粒子，且可具有球形形狀。此外，球形填充劑粒子可具有多個不同的直徑。包封體48中的填充劑粒子及基礎材料二者可與聚合物緩衝層24實體接觸。
在後續步驟中，執行平坦化製程，諸如化學機械研磨（Chemical Mechanical Polish；CMP）製程或機械研磨製程，以使包封體48及介電層（頂部介電層44）變薄，直至暴露金屬柱32及金屬支柱42為止。亦將各別製程說明為圖26中所展示的製程流程中的製程306。歸因於平坦化製程，金屬柱32的頂端與金屬支柱42的頂部表面實質上齊平（共面），且與包封體48的頂部表面實質上共面。在後續段落中，金屬柱32替代地被稱作穿孔32，此是由於所述穿孔32穿透包封體48。
圖7至圖13說明前側重佈線結構的形成。圖7及圖8說明重佈線（Redistribution Lines；RDL）的第一層及各別介電層的形成。參看圖7，形成介電層50。將各別製程說明為圖26中所展示的製程流程中的製程308。根據本揭露內容的一些實施例，介電層50由諸如PBO、聚醯亞胺或類似者的聚合物形成。形成方法包含以可流動形式塗佈介電層50，且隨後固化介電層50。根據本揭露內容的替代性實施例，介電層50由諸如氮化矽、氧化矽或類似者的無機介電材料形成。形成方法可包含塗佈、化學氣相沈積（Chemical Vapor Deposition；CVD）、原子層沈積（Atomic Layer Deposition；ALD）、電漿增強型化學氣相沈積（Plasma-Enhanced Chemical Vapor Deposition；PECVD）或其他可適用的沈積方法。通孔開口52隨後經由使介電層50圖案化而形成。各別製程亦說明為圖26中所展示的製程流程中的製程308。根據介電層50由光敏性材料（諸如PBO或聚醯亞胺）形成的一些實施例，通孔開口52的形成涉及使用微影罩幕（未展示）的曝光製程（photo exposure process）及顯影製程。穿孔32及金屬支柱42經由通孔開口52暴露。
除通孔開口52之外，亦形成開口53及可能的開口54。根據本揭露內容的一些實施例，在晶圓級下執行封裝製程，且多個元件晶粒36被置放於載體20上並在共同製程中封裝以形成重構晶圓100，所述重構晶圓100最終被鋸切分成如圖23中所展示的多個封裝體102。圖23說明根據一些實施例的重構晶圓100的俯視圖。多個封裝體102（各自包含元件晶粒36及對應穿孔32以及RDL等）形成為重構晶圓100中的陣列。多個切割道110形成為將多個封裝體102分離開的柵格。如圖7中所展示，將穿孔32及元件晶粒36所位於的區域標記為內部封裝區域102'，所述內部封裝區域102'由外圍區域104包圍。外圍區域104形成環繞各別封裝體的內部封裝區域102'的環形區域（在各別封裝體的俯視圖中）。形成於外圍區域104中的多個特徵中的每一者可形成環，所述環環繞內部封裝區域102'。環形外圍區域104的實例展示於圖23中，且儘管未展示，但其他封裝體102亦具有相同的環形外圍區域。
在圖7中，左側切割道110僅展示各別切割道110的一半（右半部分），而並未展示各別切割道110的左半部分。在切割道110的左半部分中的特徵可鏡射於將形成於後續製程中的特徵。圖7中的橫截面視圖可自圖23中的參考橫截面SC-SC（亦展示於圖25中）獲得。圖24示意性地說明左半部分及右半部分二者均說明的切割道110實例的橫截面視圖。形成於如圖24中所展示的切割道110中的特徵將在後續段落中論述。
返回參看圖7，根據本揭露內容的一些實施例，多個開口53中的每一者形成為延伸至四個切割道110（圖23）中，所述四個切割道110鄰接各別封裝體的多個邊緣。因此，開口53形成環形開口。因此，如自圖23中可見，將存在多個開口53（未展示），所述開口各自形成環繞各別的內部封裝區域102'/外圍區域104的環。如圖24中所展示，介電層50的部分50'可留在各別切割道110的中心中。切割道110中的部分50'連接為介電柵格。介電柵格使多個開口53彼此分離。此外，開口54亦將形成環繞內部封裝區域102'的環，如自圖7及圖23可得知。
接下來，參看圖8，形成金屬環56（同樣參看圖24）、金屬環58以及RDL 60。將各別製程說明為圖26中所展示的製程流程中的製程310。形成製程可包含：在圖7中所展示的結構上形成毯覆式金屬晶種層（blanket metal seed layer）（未展示）；形成鍍覆罩幕（諸如光阻）並使所述鍍覆罩幕圖案化以顯露金屬晶種層的某些部分；在鍍覆罩幕中的開口中鍍覆金屬環56、金屬環58以及RDL 60；移除鍍覆罩幕；以及蝕刻先前由鍍覆罩幕覆蓋的金屬晶種層的部分。根據本揭露內容的一些實施例，金屬晶種層包含鈦層及鈦層上方的銅層。金屬晶種層的形成可包含例如PVD。金屬晶種層延伸至通孔開口52、開口53以及開口54中，且接觸穿孔32及金屬支柱42。根據本揭露內容的一些實施例，鍍覆材料包括銅或銅合金。鍍覆可包含電化學鍍覆或非電鍍覆。
金屬環56、金屬環58以及RDL 60中的每一者可包含介電層50中的通孔部分，及介電層50上方的金屬跡線部分。RDL 60的通孔部分與金屬支柱42或穿孔32接觸。金屬環56及金屬環58的通孔部分與包封體48的頂部表面接觸。
參看圖9，形成介電層66。將各別製程說明為圖26中所展示的製程流程中的製程312。可使用自用於形成介電層50的同一組候選材料中選出的材料來形成介電層66，所述候選材料可包含PBO、聚醯亞胺、BCB或其他有機材料或無機材料。開口68、開口69以及開口70隨後例如經由曝光製程及顯影製程來形成於介電層66中。介電層66覆蓋RDL 60。RDL 60、金屬環58以及金屬環56的某些部分分別經由開口68、開口69以及開口70暴露。開口70延伸至切割道110及外圍區域104中。
根據一些實施例，介電層66的邊緣自介電層50的邊緣（朝向各別封裝體的中心線102C）凹進了距離D1。根據一些實施例，凹進的距離D1在約2微米與約15微米之間的範圍內，且可為大約8微米。採用凹進以改良不同介電層之間的疊加的製程裕度（process window）。介電層66可在暴露金屬環56的外部部分的情況下覆蓋金屬環56的邊緣部分。
參看圖10，形成RDL 72、金屬環74以及金屬環76。將各別製程說明為圖26中所展示的製程流程中的製程314。RDL 72、金屬環74以及金屬環76的形成製程可基本上與RDL 60的形成相同。RDL 72亦包含通孔部分及金屬跡線部分，所述通孔部分延伸至介電層66中的通孔開口中以接觸RDL 60，所述金屬跡線部分在介電層66的正上方，且金屬環74及金屬環76亦如此。RDL 72、金屬環74以及金屬環76的形成可與RDL 60、金屬環58以及金屬環56的形成製程類似。
圖11說明在介電層上方形成介電層78。將各別製程說明為圖26中所展示的製程流程中的製程316。接下來，開口79、開口80以及開口81形成於介電層78中。開口81延伸至切割道110及外圍區域104中。可由自用於形成介電層50及介電層66的同一組候選材料中選出的材料形成介電層78。根據一些實施例，介電層78的邊緣自介電層66的各別邊緣朝向中心線102C凹進了距離D2。根據一些實施例，凹進的距離D2在約2微米與約15微米之間的範圍內，且可為大約8微米。介電層78可在暴露金屬環76的外部部分的情況下覆蓋金屬環76的邊緣部分。
參看圖12，形成RDL 82、金屬環84以及金屬環86。將各別製程說明為圖26中所展示的製程流程中的製程318。RDL 82、金屬環84以及金屬環86的形成製程可基本上與RDL 60、金屬環58以及金屬環56的形成相同。RDL 82、金屬環84以及金屬環86可由金屬或金屬合金形成，所述金屬或金屬合金包含鋁、銅、鎢或其合金。應理解，儘管在所說明的實例實施例中形成有三層RDL，但封裝體可具有其他數目的RDL層，諸如一層、兩層或大於三層。
圖13說明介電層88的形成。將各別製程說明為圖26中所展示的製程流程中的製程320。可由自用於形成介電層50、介電層66以及介電層78的同一組候選材料中選出的材料形成介電層88。舉例而言，介電層88可使用PBO、聚醯亞胺或BCB來形成。開口（由UBM 90及電連接件92佔據）形成於介電層88中以暴露下伏金屬襯墊，所述下伏金屬襯墊是RDL 82的部分。開口89進一步形成為延伸至切割道110及外圍區域104中。根據一些實施例，介電層88的邊緣自介電層78的邊緣朝向中心線102C凹進了距離D3。根據一些實施例，凹進的距離D3在約2微米與約15微米之間的範圍內，且可為大約8微米。介電層88可在暴露金屬環86的外部部分的情況下覆蓋金屬環86的邊緣部分。
圖13亦說明根據一些實施例的凸塊下金屬（Under-Bump Metallurgy；UBM）90及電連接件92的形成。將各別製程說明為圖26中所展示的製程流程中的製程322。根據本揭露內容的一些實施例，UBM 90形成為延伸至介電層88中的開口中，以便接觸RDL 82中的金屬襯墊。UBM 90可由鎳、銅、鈦或其多層形成。根據一些實施例，UBM 90包含鈦層及鈦層上方的銅層。
根據一些實施例，隨後形成電連接件92。電連接件92的形成可包含將焊球置放於UBM 90的暴露部分上，且隨後回焊焊球。根據本揭露內容的替代性實施例，電連接件92的形成包含執行鍍覆步驟以在UBM 90上方形成焊料層，及隨後回焊焊料層。電連接件92亦可包含亦經由鍍覆形成的非焊料金屬支柱或是金屬支柱及焊料蓋，所述焊料蓋位於非焊料金屬支柱上方。貫穿本說明書，組合地包含介電緩衝層24及上覆結構的結構被稱為重構晶圓100。
在圖13中所展示的結構中，密封環120形成於外圍區域104中，且包含連結在一起以形成積體密封環的金屬環58、金屬環74以及金屬環84。密封環120環繞其中的RDL 60、RDL 72以及RDL 82。根據一些實施例，密封環120電接地或電浮置。
如圖13中所展示的密封環120僅為示意性地說明。圖17說明包含金屬環58、金屬環74以及金屬環84的密封環120的更詳細視圖。金屬環58、金屬環74以及金屬環84的上部金屬環堆疊於各別下伏金屬環的跡線部分上。密封環120可佔據寬度W1，例如，所述寬度可在約30微米與約50微米之間的範圍內。
圖18說明RDL的更詳細視圖，所述RDL可以是以下中的任一者：RDL 60、RDL 72以及RDL 82。RDL包含向下延伸至下伏介電層中的通孔部分，及各別介電層上方的跡線部分。
此外，如圖13中所展示，切割道110中的開口形成空氣通道122。重構晶圓100包含內連以形成柵格的多個空氣通道122。空氣通道122延伸至切割道110中，且可延伸至外圍區域104中。根據一些實施例，空氣通道122的上部部分比各別下伏部分寬。此外，金屬環56、金屬環76以及金屬環86經內連以形成積體金屬環，所述積體金屬環延伸至切割道110中，且可延伸至外圍區域104中。
接下來，參看圖14，在使電連接件92面朝支架（frame）124中的載帶且貼合至所述載帶的情況下，將重構晶圓100貼合至支架124。隨後例如藉由將雷射束投影於釋放膜22上而自載體20（圖13）卸下重構晶圓100。釋放膜22在雷射束的熱量下被分解。在圖14中，空氣通道122具有將空氣從支架124與重構晶圓100之間的空間中導出的功能。在後續製程中，可例如在一些清洗製程中產生電漿，且空氣通道可用於導出將除氣的氣體，使得重構晶圓100不會自支架124剝離。若未形成空氣通道，則可能需要執行預開槽製程（pre-grooving process）以形成空氣通道。預開槽製程產生額外製造成本。作為對比，根據本揭露內容的實施例形成的空氣通道並不產生額外製造成本，且因此可節省預開槽製程的成本。
接下來，參看圖15，開口126例如經由雷射鑽孔而形成於介電緩衝層24中。當穿孔32包含鈦層，且鈦層來自金屬晶種層25（圖2）時，可經由蝕刻移除鈦層，因此暴露穿孔32中的銅。
隨後可在晶粒鋸切製程中使重構晶圓100單體化。將各別製程說明為在圖26中所展示的製程流程中的製程324。舉例而言，鋸片可鋸切穿過切割道110以將重構晶圓100分離至多個相同封裝體102中，所述多個相同封裝體各自具有如根據一些實例所說明的結構。說明位於切割道110中的切口（kerf）128。由於製程原因，切口128可出現在切割道110中的任何位置中，且與圖15中所說明的切口相比，可向左或向右偏移。舉例而言，虛線130說明切口128的右側邊緣的可能位置。在晶粒鋸切製程中可鋸切穿過或可不鋸切穿過金屬環56，且在晶粒鋸切製程中不可鋸切穿過金屬環76及金屬環86。
圖25展示封裝體102的平面圖（俯視圖或仰視圖）。根據本揭露內容的一些實施例，每一金屬環56包含四個側邊，其中所述四個側邊中的每一者與各別封裝體102的四個邊緣102A中的一者平行。可鋸切穿過金屬環56的一個側邊、兩個側邊、三個側邊或所有四個側邊。因此，在所得封裝體102中，金屬環56可延伸至多個邊緣102A中的一者、兩者、三者或四者。另一方面，金屬環76及金屬環86在晶粒鋸切製程中未被鋸切。金屬環56、金屬環76以及金屬環86可連結以形成積體金屬環，所述積體金屬環可電接地或電浮置。虛線矩形122A說明空氣通道122的內部邊界，其中空氣通道122亦形成環，所述環自虛線矩形122A延伸至封裝體102的各別邊緣102A。虛線矩形76A及虛線矩形86A分別說明金屬環76及金屬環86的外部邊界的位置。封裝體102的中心在中心線102C處。
圖16說明經由焊料區域（電連接件92）將封裝體102接合至封裝組件134。根據本揭露內容的一些實施例，封裝組件134是封裝基底，所述封裝基底可以是無芯基底或具有芯的基底。根據其他實施例，封裝組件134是印刷電路板、封裝體或類似者。底填充料136可施配在封裝體102與封裝組件134之間。底填充料136可包含基礎材料及基礎材料中的填充劑粒子，所述基礎材料可以是聚合物、樹脂、環氧樹脂或類似者。填充劑粒子可以是SiO2 、Al2 O3 、二氧化矽或類似者的介電粒子，且可為具有相同直徑或不同直徑的球形形狀。封裝體102亦可經由焊料區域206接合至封裝體200。根據一些實施例，封裝體200包含元件晶粒202及基底204。晶粒202可以是記憶體晶粒，諸如動態隨機存取記憶體（Dynamic Random Access Memory；DRAM）晶粒。底填充料208可設置於封裝體102與封裝體200之間。圖16中的所得封裝體被稱作封裝體140。
圖19至圖22說明根據本揭露內容的一些實施例的封裝體140的橫截面視圖。除非另外規定，否則這些實施例中的組件的材料及形成方法基本上與類似組件相同，所述類似組件由圖1至圖16中所展示的實施例中的相同圖式元件符號表示。關於圖19至圖22中所展示的組件的形成製程及材料的細節因此在對圖1至圖16中所展示的實施例的論述中可見。
圖19說明根據一些實施例的封裝體140。除未形成金屬環56、金屬環76以及金屬環86（圖16）之外，這些實施例與圖16中所展示的內容類似。因此，介電層66、介電層78以及介電層88暴露於空氣通道122，所述空氣通道122由底填充料136填充。底填充料136亦可與包封體48接觸。
圖20說明根據一些實施例的封裝體140。除未形成密封環120（圖16）之外，這些實施例與圖16中所展示的實施例類似。金屬環56、金屬環76以及金屬環86內連，且因此充當密封環。由金屬環56、金屬環76以及金屬環86形成的密封環可電接地或電浮置。由於未形成密封環120，因此節省了用於形成密封環120的晶片面積。
圖21說明根據一些實施例的封裝體140。除介電層88亦延伸以覆蓋並接觸金屬環56及金屬環76之外，這些實施例與圖16中所展示的實施例類似。
圖22說明根據一些實施例的封裝體140。除未形成密封環120（圖21）之外，這些實施例與圖21中所展示的實施例類似。金屬環56、金屬環76以及金屬環86內連，且因此充當密封環。由金屬環56、金屬環76以及金屬環86形成的密封環可電接地或電浮置。由於未形成密封環120，因此節省了用於形成密封環120的晶片面積。
在上文所說明的實施例中，根據本揭露內容的一些實施例來論述一些製程及特徵。亦可包含其他特徵及製程。舉例而言，可包含測試結構以幫助對3D封裝體或3DIC元件的驗證測試。測試結構可包含例如形成於重佈線層中或基底上的測試襯墊，所述測試襯墊允許測試3D封裝體或3DIC、使用探針及/或探針卡，及類似者。可對中間結構以及最終結構執行驗證測試。此外，本文中所揭露的結構及方法可與併入有對良裸晶粒的中間驗證的測試方法結合使用，以提高良率且降低成本。
本揭露內容的實施例具有一些有利特徵。藉由利用現有介電形成製程及RDL形成製程來形成空氣通道，節省用於形成空氣通道的製造成本（例如，使用雷射的預開槽）。由於密封環可藉由在封裝體的多個邊緣部分上形成連接的金屬環而形成，因此亦可節省以其他方式保留以供形成密封環的晶片面積。
根據本揭露內容的一些實施例，方法包含：將第一元件晶粒及第二元件晶粒包封於包封體中；在第一元件晶粒、第二元件晶粒以及包封體上方形成第一介電層；使所述第一介電層圖案化以形成多個第一開口及第二開口，其中第一元件晶粒的導電特徵及第二元件晶粒的導電特徵暴露於所述多個第一開口，且其中第二開口延伸至第一元件晶粒與第二元件晶粒之間的切割道中；形成多個第一重佈線，所述多個第一重佈線延伸至多個第一開口中以與第一元件晶粒及第二元件晶粒電性耦接；在多個第一重佈線上方形成第二介電層；使第二介電層圖案化以形成多個第三開口及第四開口，其中多個第一重佈線的多個部分暴露於多個第三開口，且第四開口延伸至切割道中；形成多個第二重佈線，所述多個第二重佈線延伸至多個第三開口中以與所述多個第一重佈線電性耦接；以及執行晶粒鋸切製程以分別將第一元件晶粒及第二元件晶粒分離至第一封裝體及第二封裝體中，其中晶粒鋸切製程的切口穿過切割道。在一實施例中，第四開口比第二開口寬。在一實施例中，第一元件晶粒及第二元件晶粒形成重構晶圓的部分，且所述方法更包括將所述重構晶圓貼合至支架，其中第二開口及第四開口餘留有至少部分以形成空氣通道的一部分，且所述空氣通道在包封體與支架之間。在一實施例中，所述方法更包括在用於形成多個第一重佈線的同一製程中形成延伸至切割道中的第一金屬環，其中所述第一金屬環環繞第一封裝體的內部部分。在一實施例中，在晶粒鋸切製程中，第一金屬環被鋸切穿過。在一實施例中，在晶粒鋸切製程之後，第一金屬環形成環繞第一封裝體的內部部分的多個堆疊金屬環的一部分。在一實施例中，所述方法更包括在用於形成多個第二重佈線的同一製程中形成連結至第一金屬環的第二金屬環，其中整個第二金屬環在切割道外部。在一實施例中，所述方法更包括：將第一封裝體接合至封裝組件；以及將底填充料設置於第一封裝體與封裝組件之間的間隙中，其中底填充料設置於第二開口及第四開口的至少一部分中。
根據本揭露內容的一些實施例，方法包含形成重構晶圓，包括：將元件晶粒包封於包封體中；在元件晶粒及包封體上方形成第一介電層；形成多個第一重佈線，所述多個第一重佈線延伸至第一介電層中以與元件晶粒電性耦接；以及在用於形成多個第一重佈線的共同製程中形成第一金屬環，其中第一金屬環環繞多個第一重佈線，且第一金屬環延伸至重構晶圓的多個切割道中；以及沿重構晶圓的多個切割道執行晶粒鋸切製程以使封裝體從重構晶圓分離，其中封裝體包括元件晶粒及第一金屬環的至少一部分。在一實施例中，在晶粒鋸切製程中，第一金屬環被鋸切穿過。在一實施例中，所述方法更包括：在第一介電層及多個第一重佈線上方形成第二介電層；形成多個第二重佈線，所述多個第二重佈線延伸至第二介電層中以連結至多個第一重佈線；以及在用於形成多個第二重佈線的同一製程中形成第二金屬環，其中第二金屬環環繞多個第二重佈線。在一實施例中，在晶粒鋸切製程中，第二金屬環未被鋸切穿過。在一實施例中，第二金屬環連結至第一金屬環以形成積體密封環的部分。在一實施例中，封裝體在積體密封環與多個第一重佈線之間的不含密封環。在一實施例中，所述方法更包括形成延伸至第一介電層中的額外密封環，其中第一金屬環環繞額外密封環。
根據本揭露內容的一些實施例，積體電路元件的封裝體包含：元件晶粒；包封體，將所述元件晶粒包封於其中；多個介電層，上覆於包封體，其中多個介電層的多個邊緣與封裝體的多個邊緣間隔開，且多個介電層的多個上部層的多個邊緣比多個介電層的各別的多個下部層的多個邊緣朝向封裝體的中心凹進得更多；以及多個重佈線，延伸至多個介電層中以與元件晶粒電性耦接。在一實施例中，所述封裝體更包括金屬環，其中所述金屬環環繞多個介電層及多個重佈線。在一實施例中，金屬環包括：底部環，延伸至封裝體的至少一邊緣；以及上部環，位於底部環上方且連結至底部環，其中所述上部環與封裝體的多個邊緣間隔開。在一實施例中，所述封裝體更包括額外密封環，所述額外密封環與多個介電層的多個邊緣間隔開，其中金屬環環繞所述額外密封環。在一實施例中，所述封裝體更包括底填充料，所述底填充料環繞多個介電層且位於與多個介電層相同的層級處，其中所述底填充料重疊於包封體的多個邊緣部分。
前文概述若干實施例的特徵，使得所屬領域中的技術人員可更佳地理解本揭露內容的態樣。所屬領域中的技術人員應瞭解，其可易於使用本揭露內容作為設計或修改用於實現本文中所引入的實施例的相同目的及/或達成相同優點的其他製程及結構的基礎。所屬領域中的技術人員亦應認識到，此類等效構造並不脫離本揭露內容的精神及範疇，且所屬領域中的技術人員可在不脫離本揭露內容的精神及範疇的情況下在本文中作出各種改變、替代以及更改。
20:載體 22:釋放膜 24:聚合物緩衝層 25:金屬晶種層 26:光阻 28、53、54、68、69、70、79、80、81、126:開口 32:金屬柱/穿孔 36、202:元件晶粒 38:晶粒貼合膜 42:金屬支柱 44:頂部介電層 48:包封體 50、66、78、88:介電層 50':部分 52:通孔開口 56、58、74、76、84、86:金屬環 60、72、82:重佈線 76A、86A、122A:虛線矩形 90:凸塊下金屬 92:電連接件 100:重構晶圓 102、140、200:封裝體 102A:邊緣 102C:中心線 102':內部封裝區域 104:外圍區域 110:切割道 120:密封環 122:空氣通道 124:支架 128:切口 130:虛線 134:封裝組件 136、208:底填充料 204:基底 206:焊料區域 300:製程流程 302、304、306、308、310、312、314、316、318、320、322、324:製程 D1、D2、D3:距離 W1:寬度
結合隨附圖式閱讀以下詳細描述時會最佳地理解本揭露內容的態樣。應注意，根據業界中的標準慣例，各種特徵並未按比例繪製。事實上，可出於論述清楚起見而任意地增加或縮減各種特徵的尺寸。 圖1至圖16說明根據一些實施例的封裝體的形成中的中間階段。 圖17說明根據一些實施例的密封環的橫截面視圖。 圖18說明根據一些實施例的重佈線（redistribution line）的橫截面視圖。 圖19至圖22說明根據一些實施例的一些封裝體的橫截面視圖。 圖23說明根據一些實施例的重構晶圓的平面圖。 圖24說明根據一些實施例的重構晶圓的切割道的橫截面視圖。 圖25說明根據一些實施例的封裝體的平面圖。 圖26說明用於形成根據一些實施例的封裝體的製程流程。
300:製程流程
302、304、306、308、310、312、314、316、318、320、322、324:製程

Claims (20)

  1. 一種方法，包括： 將第一元件晶粒及第二元件晶粒包封於包封體中； 在所述第一元件晶粒、所述第二元件晶粒以及所述包封體上方形成第一介電層； 使所述第一介電層圖案化以形成多個第一開口及第二開口，其中所述第一元件晶粒的導電特徵及所述第二元件晶粒的導電特徵暴露於所述多個第一開口，且其中所述第二開口延伸至所述第一元件晶粒與所述第二元件晶粒之間的切割道中； 形成多個第一重佈線，所述多個第一重佈線延伸至所述多個第一開口中以與所述第一元件晶粒及所述第二元件晶粒電性耦接； 在所述多個第一重佈線上方形成第二介電層； 使所述第二介電層圖案化以形成多個第三開口及第四開口，其中所述多個第一重佈線的多個部分暴露於所述多個第三開口，且所述第四開口延伸至所述切割道中； 形成多個第二重佈線，所述多個第二重佈線延伸至所述多個第三開口中以與所述多個第一重佈線電性耦接；以及 執行晶粒鋸切製程以分別將所述第一元件晶粒及所述第二元件晶粒分離至第一封裝體及第二封裝體中，其中所述晶粒鋸切製程的切口穿過所述切割道。
  2. 如申請專利範圍第1項所述的方法，其中所述第四開口比所述第二開口寬。
  3. 如申請專利範圍第1項所述的方法，其中所述第一元件晶粒及所述第二元件晶粒形成重構晶圓的部分，且所述方法更包括將所述重構晶圓貼合至支架，其中所述第二開口及所述第四開口餘留有至少部分以形成空氣通道的一部分，且所述空氣通道在所述包封體與所述支架之間。
  4. 如申請專利範圍第1項所述的方法，更包括在用於形成所述多個第一重佈線的同一製程中形成延伸至所述切割道中的第一金屬環，其中所述第一金屬環環繞所述第一封裝體的內部部分。
  5. 如申請專利範圍第4項所述的方法，其中在所述晶粒鋸切製程中，所述第一金屬環被鋸切穿過。
  6. 如申請專利範圍第5項所述的方法，其中在所述晶粒鋸切製程之後，所述第一金屬環形成環繞所述第一封裝體的所述內部部分的多個堆疊金屬環的一部分。
  7. 如申請專利範圍第4項所述的方法，更包括在用於形成所述多個第二重佈線的同一製程中形成連結至所述第一金屬環的第二金屬環，其中整個所述第二金屬環在所述切割道外部。
  8. 如申請專利範圍第1項所述的方法，更包括： 將所述第一封裝體接合至封裝組件；以及 將底填充料設置於所述第一封裝體與所述封裝組件之間的間隙中，其中所述底填充料設置於所述第二開口及所述第四開口的至少一部分中。
  9. 一種方法，包括： 形成重構晶圓，包括： 將元件晶粒包封於包封體中； 在所述元件晶粒及所述包封體上方形成第一介電層； 形成多個第一重佈線，所述多個第一重佈線延伸至所述第一介電層中以與所述元件晶粒電性耦接；以及 在用於形成所述多個第一重佈線的共同製程中形成第一金屬環，其中所述第一金屬環環繞所述多個第一重佈線，且所述第一金屬環延伸至所述重構晶圓的多個切割道中；以及 沿所述重構晶圓的所述多個切割道執行晶粒鋸切製程以使封裝體從所述重構晶圓分離，其中所述封裝體包括所述元件晶粒及所述第一金屬環的至少一部分。
  10. 如申請專利範圍第9項所述的方法，其中在所述晶粒鋸切製程中，所述第一金屬環被鋸切穿過。
  11. 如申請專利範圍第9項所述的方法，更包括： 在所述第一介電層及所述多個第一重佈線上方形成第二介電層； 形成多個第二重佈線，所述多個第二重佈線延伸至所述第二介電層中以連結至所述多個第一重佈線；以及 在用於形成所述多個第二重佈線的同一製程中形成第二金屬環，其中所述第二金屬環環繞所述多個第二重佈線。
  12. 如申請專利範圍第11項所述的方法，其中在所述晶粒鋸切製程中，所述第二金屬環未被鋸切穿過。
  13. 如申請專利範圍第11項所述的方法，其中所述第二金屬環連結至所述第一金屬環以形成積體密封環的部分。
  14. 如申請專利範圍第13項所述的方法，其中所述封裝體在所述積體密封環與所述多個第一重佈線之間不含密封環。
  15. 如申請專利範圍第9項所述的方法，更包括形成延伸至所述第一介電層中的額外密封環，其中所述第一金屬環環繞所述額外密封環。
  16. 一種積體電路元件的封裝體，所述封裝體包括： 元件晶粒； 包封體，將所述元件晶粒包封於其中； 多個介電層，上覆於所述包封體，其中所述多個介電層的多個邊緣與所述封裝體的多個邊緣間隔開，且所述多個介電層的多個上部層的多個邊緣比所述多個介電層的各別的多個下部層的多個邊緣朝向所述封裝體的中心凹進得更多；以及 多個重佈線，延伸至所述多個介電層中以與所述元件晶粒電性耦接。
  17. 如申請專利範圍第16項所述的積體電路元件的封裝體，更包括金屬環，其中所述金屬環環繞所述多個介電層及所述多個重佈線。
  18. 如申請專利範圍第17項所述的積體電路元件的封裝體，其中所述金屬環包括： 底部環，延伸至所述封裝體的至少一邊緣；以及 上部環，位於所述底部環上方且連結至所述底部環，其中所述上部環與所述封裝體的所述多個邊緣間隔開。
  19. 如申請專利範圍第17項所述的積體電路元件的封裝體，更包括額外密封環，所述額外密封環與所述多個介電層的所述多個邊緣間隔開，其中所述金屬環環繞所述額外密封環。
  20. 如申請專利範圍第16項所述的積體電路元件的封裝體，更包括底填充料，所述底填充料環繞所述多個介電層且位於與所述多個介電層相同的層級處，其中所述底填充料重疊於所述包封體的多個邊緣部分。
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US11984410B2 (en) 2024-05-14
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US20210366845A1 (en) 2021-11-25
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US11088094B2 (en) 2021-08-10
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