CN111868917A - 基板贴合构造及基板贴合方法 - Google Patents

基板贴合构造及基板贴合方法 Download PDF

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CN111868917A
CN111868917A CN201880091122.2A CN201880091122A CN111868917A CN 111868917 A CN111868917 A CN 111868917A CN 201880091122 A CN201880091122 A CN 201880091122A CN 111868917 A CN111868917 A CN 111868917A
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substrate
bonding
bump
circuit
counter substrate
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CN201880091122.2A
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西泽弘一郎
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Publication of CN111868917A publication Critical patent/CN111868917A/zh
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Abstract

在基板(1)的主面形成有器件(2)。基板(1)的主面和相对基板(14)的下表面经由接合部件(11、12、13)以中空状态接合。电路(17)及凸块构造(26)形成于相对基板(14)的上表面。凸块构造(26)至少配置于与接合部件(11、12、13)对应的区域，与电路(17)相比高度高。

Description

基板贴合构造及基板贴合方法
技术领域
本发明涉及将基板和相对基板贴合的构造及其贴合方法。
背景技术
为了缩小半导体装置的安装面积，提出将半导体基板和其它半导体基板或玻璃或蓝宝石等半导体之外的基板贴合的构造。另外，为了提高可靠性，还提出了在基板间设置封装框而形成了中空部的构造(例如，参照专利文献1)。
作为基板贴合方法，存在将晶片状态的基板和相对基板贴合，通过切割而分离为各个器件的晶片级别芯片规模封装件(WLCSP)这样的方法。例如，通过晶片工艺在基板阵列状地形成器件，在相对基板也形成与器件对应的电路，经由连接凸块将两者接合。在该方法中，能够同时形成大量器件，成本低于单独地进行封装的情况。
专利文献1：日本特开2009-285810号公报
发明内容
将基板和相对基板进行定位而以从上下通过台板均匀地施加压力的方式进行接合。此时，就相对基板而言，由于在上表面形成的电路等各个要素受到向下的压力，因此有时相对基板之上的电路等受到损伤。另外，由于来自上侧的压力分散并改变方向而传递至连接凸块，因此不能够向连接凸块向正下方传递充分的压力。因此，有时连接凸块的密合性变差，无法实现电导通。其结果，存在可靠性受损这样的问题。
本发明就是为了解决上述那样的课题而提出的，其目的在于得到能够使可靠性提高的基板贴合构造及基板贴合方法。
本发明涉及的基板贴合构造的特征在于，具有：基板，其具有主面；器件，其形成于所述基板的所述主面；相对基板，其具有与所述主面相对的下表面、与所述下表面相反侧的上表面；接合部件，其将所述基板的所述主面和所述相对基板的所述下表面以中空状态接合；以及电路及凸块构造，它们形成于所述相对基板的所述上表面，所述凸块构造至少配置于与所述接合部件对应的区域，与所述电路相比高度高。
发明的效果
在本发明中，在相对基板的上表面形成电路及凸块构造，凸块构造至少配置于与接合部件对应的位置，与电路相比高度高。由此，在将基板和相对基板粘合时，由于高度低的电路没有与台板接触，因此能够保护电路。另外，来自上侧的台板的载荷没有分散至电路，而是经由凸块构造直线地传递至连接凸块及封装框。因此，能够施加充分的载荷，所以能够确保相对基板与接合部件的密合性。其结果，能够使可靠性提高。
附图说明
图1是表示实施方式1涉及的基板贴合构造的俯视图。
图2是沿图1的I-II的剖面图。
图3是沿图1的III-IV的剖面图。
图4是表示实施方式1涉及的基板的俯视图。
图5是表示实施方式1涉及的相对基板的仰视图。
图6是表示空气桥和凸块构造的关系的剖面图。
图7是表示空气桥和凸块构造的关系的剖面图。
图8是表示实施方式1涉及的基板侧的制造工序的一个例子的剖面图。
图9是表示实施方式1涉及的基板侧的制造工序的一个例子的剖面图。
图10是表示实施方式1涉及的基板侧的制造工序的一个例子的剖面图。
图11是表示实施方式1涉及的基板侧的制造工序的一个例子的剖面图。
图12是表示实施方式1涉及的基板侧的制造工序的其它例子的剖面图。
图13是表示实施方式1涉及的基板侧的制造工序的其它例子的剖面图。
图14是表示实施方式1涉及的基板侧的制造工序的其它例子的剖面图。
图15是表示实施方式1涉及的相对基板侧的制造工序的剖面图。
图16是表示实施方式1涉及的相对基板侧的制造工序的剖面图。
图17是表示实施方式1涉及的相对基板侧的制造工序的剖面图。
图18是表示实施方式1涉及的相对基板侧的制造工序的剖面图。
图19是表示实施方式1涉及的基板和相对基板的贴合工序的剖面图。
图20是表示对比例1涉及的基板和相对基板的贴合工序的剖面图。
图21是表示对比例2涉及的基板和相对基板的贴合工序的剖面图。
图22是表示实施方式1涉及的基板贴合构造的变形例的剖面图。
图23是表示实施方式2涉及的基板贴合构造的主要部分的剖面图。
图24是表示实施方式3涉及的基板贴合构造的主要部分的剖面图。
图25是表示实施方式3涉及的基板贴合构造的凸块构造和接合部件的位置关系的俯视图。
具体实施方式
参照附图对实施方式涉及的基板贴合构造及基板贴合方法进行说明。对相同或对应的结构要素标注相同标号，有时省略重复说明。
实施方式1.
图1是表示实施方式1涉及的基板贴合构造的俯视图。图2是沿图1的I-II的剖面图。图3是沿图1的III-IV的剖面图。图4是表示实施方式1涉及的基板的俯视图。图5是表示实施方式1涉及的相对基板的仰视图。这里，对将基板贴合构造应用于使用了GaN-HEMT晶体管的功率放大器的例子进行说明。但是，并不限于该例子所示的晶体管、电路、基板种类等。另外，材料及尺寸只是一个例子，并不是对使用范围进行限定。
基板1例如是在SiC或Si的单晶基板之上使GaN-AlGaN层进行异质外延生长得到的基板。在基板1的主面的中央形成有HEMT晶体管即器件2。封装框承载焊盘3形成为将器件2包围。
器件2具有栅极电极4、源极电极5、漏极电极6、与栅极电极4连接的栅极焊盘7、与漏极电极6连接的漏极焊盘8。源极电极5也兼作源极焊盘。从栅极焊盘7输入信号电压，从源极电极5供给电流，从漏极焊盘8输出信号电流。
栅极电极4的一根的宽度为50～500μm左右，与所需要的输出对应地在横向平行地排列多根。这里，示出排列了2根栅极电极4的情况，但实际上排列2根～100根左右。器件2的大小根据1根的栅极宽度和栅极根数而不同，在1根的栅极宽度为500μm、栅极根数为70根的情况下为纵向1mm、横向3mm左右。栅极电极4的横向宽度即栅极长度越细，则信号特性越好。例如，栅极电极4是以0.1～1.0μm的横向宽度，依次通过蒸镀法形成了20nm厚度的Ti膜和200nm厚度的Al膜的2层构造。漏极电极6及源极电极5与基板1的GaN外延层欧姆接合，漏极电极6及源极电极5是在通过蒸镀法形成了50nm厚度的Ni膜和500nm厚度的Au膜的基础上通过镀敷形成1～10μm厚度的Au膜而成的。Au膜的厚度是与在电极流动的电流对应地选定的。栅极焊盘7和漏极焊盘8由500nm厚度的Ti膜和1～10μm厚度的Au膜形成，与漏极电极6和栅极电极4各自连接。
贯穿基板1的通路孔9是从基板1的背面侧通过干蚀刻形成的。基板1的厚度为50～100μm左右，通路孔9的直径为50～100μmΦ。在通路孔9内及基板1的背面形成有背面电极10。背面电极10是在50nm厚度的Ti膜和200nm厚度的Au膜这些溅射膜等种子膜之上，与在通路孔9内流动的电流对应地形成1～10μm厚度的Au镀层而成的。
在栅极焊盘7及漏极焊盘8之上各自形成有连接凸块11、12。在封装框承载焊盘3之上形成有封装框13。封装框13连接于源极电极5。基板1的主面和相对基板14的下表面经由连接凸块11、12及封装框13以中空状态接合。即，基板1的主面和相对基板14的下表面之间分离而在器件2之上构成空间，由连接凸块11、12及封装框13支撑。封装框13包围器件2而将该空间气密封装，由此可靠性提高。此外，封装框13不是必须形成的。连接凸块11、12及封装框13的高度设定为使得基板1侧的器件2与相对基板14不接触，例如为10μm左右。
相对基板14为蓝宝石、玻璃、InP、SiC、GaAs等绝缘基板、或Si高电阻基板等。在该相对基板14的上表面形成有电路17、栅极引出电极18、漏极引出电极19，该电路17具有MIM电容器15及螺旋电感16。电路17为匹配电路，这里，为与晶体管的输入侧连接的高次谐波处理电路。电路17由50nm厚度的Ti膜和1μm厚度的Au膜这些蒸镀膜、1～5μm厚度的Au镀膜构成。
贯穿相对基板14的通路孔20、21、22是从相对基板14的背面侧通过干蚀刻形成的。相对基板14的厚度为50～100μm左右，通路孔20、21、22的直径为50～100μmΦ。在通路孔20内形成有电极23。在通路孔21内及相对基板14的背面形成有屏蔽电极24。在通路孔22内形成有电极25。电极23、25及屏蔽电极24是在50nm厚度的Ti膜和200nm厚度的Au膜这些溅射膜等种子膜之上，与在通路孔20、21、22内流动的电流对应地形成1～5μm厚度的Au镀层而成的。为了使连接于栅极、漏极的连接凸块11、12与屏蔽电极24绝缘，在形成镀膜和溅射膜后使电极23、25与屏蔽电极24通过图案化而分离。
栅极引出电极18经由电极23和连接凸块11连接于基板1侧的栅极焊盘7。栅极引出电极18另行经由MIM电容器15、螺旋电感16连接于屏蔽电极24。该屏蔽电极24经由封装框13及源极电极5与接地即背面电极10连接。通过从该栅极引出电极18至接地为止的电路，能够进行高次谐波处理。另外，屏蔽电极24以使得从基板1侧的器件2产生的电磁波不从中空部传播到外部的方式进行屏蔽。
漏极引出电极19经由电极25和连接凸块12连接于基板1侧的漏极焊盘8。通过导线键合将信号输入至栅极引出电极18，通过导线键合从漏极引出电极19输出信号。这样，基板1的器件2与相对基板14的电路17经由连接凸块11、12及封装框13彼此连接。
凸块构造26是在相对基板14的上表面由10μm左右的Au镀层形成的。凸块构造26至少配置于与连接凸块11、12及封装框13对应的区域，高度比电路17高。
图6及图7是表示空气桥和凸块构造的关系的剖面图。例如，在电路17为GaN-HEMT的功率放大器的匹配电路的情况下，存在称为空气桥27的配线的交叉部。为了降低配线间的电容而通过空气桥27将配线间经由空气层隔开3μm左右，因此空气桥27比周边的配线高3μm。需要将凸块构造26制作得比该空气桥27高。如图6所示，当在蒸镀膜28及镀膜29的层叠构造之上形成凸块构造26的情况下，需要将凸块构造26的高度设为大于3μm。如图7所示，当在蒸镀膜28之上形成凸块构造26的情况下，需要将凸块构造26的高度设为大于镀层厚度+3μm。这里，示出了仅在相对基板14的上表面形成了电路17，在背面仅形成了屏蔽电极24的情况，但也可以在相对基板14的背面形成其它电路。另外，作为上表面的电路17示出了布置有MIM电容器15和螺旋电感16的例子，但将要素彼此电连接的配线构造、将要素彼此连接的连接部也包含于电路17。
接下来，对本实施方式涉及的基板贴合方法进行说明。图8至图11是表示实施方式1涉及的基板侧的制造工序的一个例子的剖面图。这些图与沿图4的III-IV的剖面图对应。在该例子中，连接凸块11、12及封装框13由Au镀层形成。此外，也可以通过基于蒸镀剥离的图案化工艺来形成连接凸块11、12及封装框13。
首先，如图8所示，在基板1的主面形成栅极焊盘7、漏极焊盘8、封装框承载焊盘3及具有漏极电极6等的器件2作为承载焊盘。此外，在基板1还形成通路孔9及背面电极10，但在图8至图14中省略了通路孔9及背面电极10的图示。此外，记载了栅极焊盘7、漏极焊盘8、漏极电极6各自为相同厚度，但这是简易地示出的，实际上漏极电极6在下层包含欧姆层，因此比其它电极厚。栅极焊盘7、漏极焊盘8、及封装框承载焊盘3并非必须，但优选是作为连接凸块11、12及封装框13的基底而形成的。由此，连接凸块11、12及封装框13的高度对齐，接合性变好。另外，通过将器件2的电极的任意者用作焊盘而使两者的电连接变得容易。
就承载焊盘而言，通过蒸镀等对与基板1密合良好的Ti等材料、和与连接凸块11、12及封装框13密合良好的材料进行连续成膜。例如，在由Au形成连接凸块11、12及封装框13的情况下，通过Ti/Au的连续成膜来形成承载焊盘。另外，承载焊盘是在器件形成过程中与器件2的电极同时形成的。此外，在漏极电极6的下层为了构成器件而需要由Ni/Au等作为欧姆电极。但是，如果连接凸块11、12及封装框13的高度没有对齐，则接合不稳定，因此优选承载焊盘的层结构是相同的。
接着，如图9所示，形成下层抗蚀层30而进行图案化。接着，在整个面形成镀敷的供电层31。接着，如图10所示，形成上层抗蚀层32而进行图案化。
接着，通过电镀仅在上层抗蚀层32的开口部分形成Au镀膜。此外，就晶片的Au镀层而言，通过以使镀敷液循环而在晶片表面使液流均匀、在晶片面内电场也变得均匀的方式构成装置，从而使镀层厚度的面内分布均匀化。如果镀层厚度产生波动，则不能够得到良好的接合，因此该镀敷工序是重要的。之后，通过去除上层抗蚀层32、供电层31、及下层抗蚀层30，从而如图11所示得到连接凸块11、12及封装框13。
图12至图14是表示实施方式1涉及的基板侧的制造工序的其它例子的剖面图。在该例子中，使用金属颗粒膏而形成连接凸块11、12及封装框13。金属颗粒膏是将金属颗粒与溶媒混合后的材料。
首先，与图8相同地在基板1的主面形成器件2、栅极焊盘7、漏极焊盘8、及封装框承载焊盘3。接着，准备另外的转印用基板33，在转印用基板33之上形成与连接凸块11、12及封装框13对应的图案。形成方法有在使用抗蚀层或掩模将金属颗粒膏填充于图案内之后将抗蚀层或掩模去除的方法等。在图案形成后进行热烘而使膏剂所包含的溶媒成分挥发。热烘的温度在Au膏的情况下为100～200℃左右。由此，形成金属颗粒凝集后的构造物，但在该阶段中没有一体化，在颗粒间存在很多空隙。此外，通过实验而知晓颗粒与空隙的体积比在Au颗粒膏的情况下为1：1左右。
接着，如图13所示，在进行了基板1之上的图案和转印用基板33之上的图案的定位后，进行加热，从两侧对基板1和转印用基板33进行加压而将连接凸块11、12及封装框13与基板1侧的焊盘接合。在进行加压时由金属颗粒膏构成的连接凸块11、12及封装框13被压缩变形，空隙减少。该变形量根据加压时的压力和温度而产生变动，例如在以30MPa、150℃对Au颗粒膏进行了加压的情况下，为原本的高度的0～20％左右。在20μm高度的图案的情况下，收缩0～4μm左右。由此，能够相对于承载焊盘的高度的不均匀或表面的微米级的凹凸柔软地变形而密合。例如，在通过镀敷而将承载焊盘形成为10μm厚度的情况下，根据图案尺寸或晶片的面内分布会产生几μm的高度分布，但在承载焊盘之上形成的金属颗粒膏图案能够将它们吸收而使高度均匀化。另外，例如，在承载焊盘3为10μm厚度的镀膜，栅极焊盘7和漏极焊盘8是将2μm厚度的蒸镀膜和10μm厚度的镀膜层叠后的膜的情况下，膏剂的收缩量也各自产生变化，由此能够使包含焊盘的整体的高度均匀化。通过使高度均匀化，从而在将基板1和相对基板14接合时密合性、封装性、电连接性提高。
最后，通过取下转印用基板33，从而完成基板侧的制造工序。如果预先将与金属颗粒膏剂密合性低的Ti等材料施涂于基板表面，则转印用基板33容易取下。此外，金属颗粒膏图案并不限于形成于基板1的主面侧，也可以形成于相对基板14的下表面侧。
图15至图18是表示实施方式1涉及的相对基板侧的制造工序的剖面图。首先，如图15所示，在相对基板14的上表面形成电路17。这里，以单层的金属图案表示电路17，但实际上由多个金属图案构成。另外，为了提高图案间的绝缘或耐湿可靠性，通过CVD法等形成氧化硅膜等绝缘膜，但省略了图示。
接着，如图16所示，对相对基板14的下表面进行研磨，进行抛光而薄化。在从相对基板14的下表面侧通过干蚀刻等形成了通路孔20、21、22，通过溅射法形成了供电层之后，通过镀敷形成厚膜的电极34。接着，如图17所示，通过利用抗蚀层进行图案化而对电极34的不需要的部分进行蚀刻，从而形成电极23、25和屏蔽电极24。
接着，如图18所示，在相对基板14的上表面形成凸块构造26。凸块构造26以与连接凸块11、12及封装框13对应的图案，形成得高度比电路17高。此外，凸块构造26的形成也可以在刚形成电路17之后进行，从下表面进行蚀刻而实现的通路孔20、21、22的形成、电极34的形成均只不过是作为一个例子而示出的。
图19是表示实施方式1涉及的基板和相对基板的贴合工序的剖面图。首先，对晶片状态的基板1的主面和晶片状态的相对基板14的下表面进行定位。然后，从上下通过平坦且平行的台板进行加压和加热而将基板1和相对基板14贴合。此时，以不与电路17接触的方式通过台板对凸块构造26进行加压而经由连接凸块11、12及封装框13将基板1的主面和相对基板14的下表面接合。连接凸块11、12及封装框13的上表面与相对基板14的背面的电极23、25、屏蔽电极24的密合面是平坦的，在高温且高压力下将两者接合。进行Ar和O2的等离子体处理而对表面进行清洁，施加超声波振动，由此能够提高密合性。作为两者的材料也可以选择在到达熔化温度之前接合的金属。例如，作为容易发生固溶反应的金属组，存在Au和In等，就Au、Pt、Ag、Pd等贵金属而言，相同的金属表面彼此也能够进行接合。
在与图13的工序相同的条件下进行加压和加热。由此，由金属颗粒膏构成的连接凸块11、12及封装框13的空隙进一步变得狭窄，金属颗粒彼此进一步密合，在没有到达金属的熔化温度的情况下颗粒的表面彼此接合而块体化。例如，Au颗粒膏在200℃、100MPa下块体化。在原本20μm高度的图案的情况下，通过接合而压缩为10μm左右。
接着，与对比例1、2进行比较地对本实施方式的效果进行说明。图20是表示对比例1涉及的基板和相对基板的贴合工序的剖面图。由于没有凸块构造26，因此有时台板会与电路17的空气桥27等接触而损伤、变形。
相对于此，在本实施方式中，在相对基板14的上表面形成凸块构造26，凸块构造26至少配置于与连接凸块11、12及封装框13对应的位置，高度比电路17高。由此，在将基板1和相对基板14粘合时，由于高度低的电路17没有与台板接触，因此能够保护电路17。另外，来自上侧的台板的载荷没有分散至电路17，而是经由凸块构造26直线地传递至连接凸块11、12及封装框13。因此，能够施加充分的载荷，所以能够确保相对基板14与连接凸块11、12及封装框13的密合性。其结果，能够使可靠性提高。
通过确保相对基板14与连接凸块11、12的密合性，能够提高两者的电连接的可靠性。另外，通过确保相对基板14与封装框13的密合性，能够提高器件的气密封装性。此外，为了电连接而向连接凸块11、12施加的压力也可以比为了提高气密封装性而向封装框13施加的压力低。因此，也可以在与封装框13对应的区域优先地设置凸块构造26，与连接凸块11、12相比向封装框13更强地施加接合时的压力。
图21是表示对比例2涉及的基板和相对基板的贴合工序的剖面图。在与连接凸块11对应的区域存在没有凸块构造26的部分。由于来自台板的压力没有直线地传递至该部分的连接凸块11，因此接合压力变低，接合变得不充分。另外，还存在相对基板14变形而产生裂缝等的可能性。因此，优选在与全部的连接凸块11、12及封装框13对应的区域配置有凸块构造26。
图22是表示实施方式1涉及的基板贴合构造的变形例的剖面图。如果凸块构造26配置于与连接凸块11、12及封装框13对应的区域，则能够得到上述效果，凸块构造26的一部分也可以局部地配置于与连接凸块11、12及封装框13对应的区域之外。但是，优选凸块构造26不配置于与连接凸块11、12及封装框13对应的区域之外。由此，针对相对基板14的上下的压力没有产生不均匀，因此能够防止相对基板14产生裂纹或裂缝。
另外，通过利用金属膏剂形成连接凸块11、12及封装框13，能够使接合前的高度均匀化。因此，能够在晶片面内稳定地接合。另外，即使在基底的承载焊盘的高度存在差异的情况下，也能够使连接凸块11、12及封装框13的高度均匀化。因此，针对器件2的限制少。例如，还能够与在具有欧姆电极的漏极电极之上制作接合凸块同时地，在没有制作欧姆电极的栅极焊盘之上形成接合凸块。并且，由于金属颗粒膏由金属颗粒构成，因此与通过镀敷等形成的块状金属相比表面积大，能够进行较低温、低压下的接合。通过在低温、低压下进行接合，能够形成不耐受高温的器件2。
实施方式2.
图23是表示实施方式2涉及的基板贴合构造的主要部分的剖面图。凸块构造26的剖面面积比连接凸块11等小，凸块构造26配置于与对应于连接凸块11等的区域相同的区域或比其更靠内侧的区域。即，凸块构造26仅配置于与连接凸块11等对应的区域内。由此，在接合时施加于凸块构造26的力全部施加于连接凸块11等，因此能够提高电连接的可靠性。
实施方式3.
图24是表示实施方式3涉及的基板贴合构造的主要部分的剖面图。在本实施方式中，将沿基板1的主面和相对基板14的上表面及下表面的方向设为横向，凸块构造26与连接凸块11等的横向的重心位置一致。由此，不会由于从凸块构造26和连接凸块11等施加于相对基板14的力产生力矩，因此使相对基板14变形的力难以起作用，难以引起由裂缝等导致的相对基板14的损伤。
图25是表示实施方式3涉及的基板贴合构造的凸块构造和接合部件的位置关系的俯视图。如果凸块构造26与连接凸块11等的横向的重心位置一致，则得到上述效果，可以如图25的左侧的图所示那样凸块构造26和连接凸块11等的图案形状不同，也可以如右侧的图所示那样彼此的分割数量不同。由此，凸块构造26和连接凸块11等的设计的自由度提高。
标号的说明
1基板，2器件，11、12连接凸块(接合部件)，13封装框(接合部件)，14相对基板，17电路，26凸块构造

Claims (9)

1.一种基板贴合构造，其特征在于，具有：
基板，其具有主面；
器件，其形成于所述基板的所述主面；
相对基板，其具有与所述主面相对的下表面、与所述下表面相反侧的上表面；
接合部件，其将所述基板的所述主面和所述相对基板的所述下表面以中空状态接合；以及
电路及凸块构造，它们形成于所述相对基板的所述上表面，
所述凸块构造至少配置于与所述接合部件对应的区域，与所述电路相比高度高。
2.根据权利要求1所述的基板贴合构造，其特征在于，
所述接合部件具有将所述器件和所述电路连接的连接凸块。
3.根据权利要求1或2所述的基板贴合构造，其特征在于，
所述接合部件具有以将所述器件包围的方式形成的封装框。
4.根据权利要求1至3中任一项所述的基板贴合构造，其特征在于，
所述凸块构造配置于与对应于所述接合部件的区域相同的区域或与对应于所述接合部件的区域相比更靠内侧的区域。
5.根据权利要求1至4中任一项所述的基板贴合构造，其特征在于，
所述凸块构造与所述接合部件的横向的重心位置一致。
6.根据权利要求5所述的基板贴合构造，其特征在于，
所述凸块构造与所述接合部件的图案形状或分割数量不同。
7.一种基板贴合方法，其特征在于，具有如下工序：
在基板的主面形成器件；
在所述基板的所述主面形成接合部件；
在相对基板的上表面形成电路和凸块构造，该凸块构造至少配置于与所述接合部件对应的位置且与所述电路相比高度高；以及
以与所述电路不接触的方式通过台板对所述凸块构造进行加压，经由所述接合部件将所述基板的所述主面和所述相对基板的下表面以中空状态接合。
8.根据权利要求7所述的基板贴合方法，其特征在于，
通过镀敷形成所述接合部件。
9.根据权利要求7所述的基板贴合方法，其特征在于，
通过金属颗粒膏形成所述接合部件。
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TWI664883B (zh) 2019-07-01
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