CN111640780A - 一种新型半导体芯片、制备方法及应用电路 - Google Patents
一种新型半导体芯片、制备方法及应用电路 Download PDFInfo
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- 239000000463 material Substances 0.000 claims abstract description 31
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 24
- 239000002184 metal Substances 0.000 claims abstract description 14
- 229910052681 coesite Inorganic materials 0.000 claims abstract description 12
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- 239000000377 silicon dioxide Substances 0.000 claims abstract description 12
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 12
- 229910052682 stishovite Inorganic materials 0.000 claims abstract description 12
- 229910052905 tridymite Inorganic materials 0.000 claims abstract description 12
- VMXJCRHCUWKQCB-UHFFFAOYSA-N NPNP Chemical compound NPNP VMXJCRHCUWKQCB-UHFFFAOYSA-N 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 12
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- 229910052698 phosphorus Inorganic materials 0.000 claims description 8
- 239000011574 phosphorus Substances 0.000 claims description 8
- 230000015556 catabolic process Effects 0.000 claims description 6
- 238000001259 photo etching Methods 0.000 claims description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 5
- 229910052796 boron Inorganic materials 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 claims description 4
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Abstract
本发明公开了一种新型半导体芯片、制备方法及应用电路,其中一种新型半导体芯片,包括:N型衬底,电阻率为0.2‑0.3Ω/cm;设置在N型衬底两侧的N型扩散层,结深为60~100μm,方块电阻为800~1500Ω/□;设置在N型扩散层中的P型扩散层,扩散结深为25~30μm,方块电阻为40~50Ω/□;在正面的P型扩散层上设置若干个N型扩散层,扩散结深为10~12μm,方块电阻0.6~0.8Ω/□;在围绕外围的N型扩散层上设置SiO2掩蔽层,厚度为2.5~3.0μm;在正面的N型扩散层设置正面金属层,材料为Al‑Ti‑Ni‑Ag,厚度3.5~4.0μm;在背面的N型扩散层设置背面金属层,材料为Al‑Ti‑Ni‑Ag,厚度3.5~4.0μm,由此形成NPNP型半导体结构。
Description
技术领域
本发明属于半导体技术领域,具体涉及一种新型半导体芯片、制备方法及应用电路。
背景技术
在电源领域有一类是直流转换为直流(DC/DC),这类电路广泛应用于采用电池供电的场合,目的是把电池电压通过DC/DC转换为适合负载的直流电压。
在二轮电动车充电应用中,功率型的非隔离型DC/DC成为二轮电动车的主流方案,但是每年曝光的二轮电动车自燃事件中经分析有一定比例就是非隔离型DC/DC开关管击穿造成的,另外根据调查获取的数据,凡是非隔离型DC/DC中由于开关管击穿造成的失效几乎都会伴随输出负载烧毁的记录。
针对以上情况,实有必要提供一种改进型的技术方案。
发明内容
鉴于以上存在的技术问题,本发明用于提供一种新型半导体芯片、制备方法及应用电路。
为解决上述技术问题,本发明采用如下的技术方案:
本发明实施例的一个方面在于提供一种新型半导体芯片,包括:
N型衬底,电阻率为0.2-0.3Ω/cm;
设置在N型衬底两侧的N型扩散层,结深为60~100μm,方块电阻为800~1500Ω/□;
设置在N型扩散层中的P型扩散层,扩散结深为25~30μm,方块电阻为40~50Ω/□;
在正面的P型扩散层上设置若干个N型扩散层,扩散结深为10~12μm,方块电阻0.6~0.8Ω/□;
在围绕外围的N型扩散层上设置SiO2掩蔽层,厚度为2.5~3.0μm;
在正面的N型扩散层设置正面金属层,材料为Al-Ti-Ni-Ag,厚度3.5~4.0μm;
在背面的N型扩散层设置背面金属层,材料为Al-Ti-Ni-Ag,厚度3.5~4.0μm,由此形成NPNP型半导体结构。
优选地,选择不同电阻率的N型衬底材料,结合对N型扩散层的扩散浓度和深度的控制,用于对该器件进入保护动作后的导通压降进行定量控制。
优选地,N型衬底材料电阻率0.20~0.25时,N型扩散层的扩散深度为80~100微米。
优选地,N型衬底材料电阻率为0.26~0.30时,N型扩散层的扩散深度为60~80微米。
本发明实施例的又一方面在于提供一种新型半导体芯片的制备方法,包括以下步骤:
S10,选择N型衬底材料,片厚300μm,衬底电阻率为0.2~0.3Ω/cm;
S20,清洗,生长氧化层,厚度为2μm;
S30,在N型衬底两侧进行N型扩散,结深60~100μm,方块电阻800~1500Ω/□;
S40,在N型扩散层中光刻P型扩散层,结深25~30μm,方块电阻40~50Ω/□;
S50,在正面的P型扩散层上光刻若干个N型扩散层,采用磷扩散,扩散温度为1145-1155℃,扩散时间为260-300min,结深10~12μm,方块电阻0.6~0.8Ω/□;
S60,刻蚀引线孔,表面金属化,材料为Al-Ti-Ni-Ag,厚度为3.5~4.0μm;
S70,背面金属化,材料为Al-Ti-Ni-Ag,厚度为3.5~4.0μm。
优选地,步骤S30中,进一步包括:采用磷扩散,扩散温度为1265-1275℃,扩散时间为11000-13000min。
优选地,步骤S40中,进一步包括:步骤S40中,进一步包括:采用硼扩散,1245~1255℃,900-1100min。
本发明实施例的又一方面在于提供一种新型半导体芯片的应用电路,包括保险丝,与保险丝串联的后级负载电路,以及与后级负载电路并接的新型半导体器件,包括以下工作状态:
所述新型半导体芯片在未动作前处于断态,仅有微安级的漏电;
当由于某种意外造成输入端的电压上升,过了触发点,所述新型半导体芯片以微秒级的速度动作,动作后拉低所述新型半导体芯片两端的电压值至低于额定电压,此时整个回路电流激增,此时新型半导体芯片处于高功率状态,此时串联在回路中的保险丝的电流大幅度超过额定值,保险丝进入熔断倒计时,此过程设计为不超过3~5个毫秒时间,一定比例的保险丝在此阶段熔断,回路被切断,保护功能实现;
新型半导体芯片正常抵抗持续的远超额定的大电流不超过1~3个微秒,半导体芯片将被热击穿进入芯片低阻态,公称融化热能在50~100A2S的保险丝在10~20毫秒的时间内熔断。
优选地,所述新型半导体芯片包括:
N型衬底,电阻率为0.2-0.3Ω/cm;
设置在N型衬底两侧的N型扩散层,结深为60~100μm,方块电阻为800~1500Ω/□;
设置在N型扩散层中的P型扩散层,扩散结深为25~30μm,方块电阻为40~50Ω/□;
在正面的P型扩散层上设置若干个N型扩散层,扩散结深为10~12μm,方块电阻0.6~0.8Ω/□;
在围绕外围的N型扩散层上设置SiO2掩蔽层,厚度为2.5~3.0μm;
在正面的N型扩散层设置正面金属层,材料为Al-Ti-Ni-Ag,厚度3.5~4.0μm;
在背面的N型扩散层设置背面金属层,材料为Al-Ti-Ni-Ag,厚度3.5~4.0μm,由此形成NPNP型半导体结构。
采用本发明具有如下的有益效果:
(1)当输入端电压超过动作电压后,本器件能够在2~5um内将电压钳位在10~14V,从而为后级电路继续供电直至保险丝熔断。
(2)处于低阻态状态时能耐受较长时间大电流,远大于保险丝熔断所需的时间。
(3)低阻态状态电压钳位稳定,且修改芯片参数后可以自由控制钳位电压。
附图说明
图1为本发明实施例的新型半导体芯片的剖面结构示意图;
图2为本发明实施例的新型半导体芯片制备方法的步骤流程图;
图3为本发明实施例的新型半导体芯片的一种应用电路;
图4为本发明实施例的新型半导体芯片的伏安特性曲线;。
具体实施方式
下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。
参照图1,所示为本发明实施例的新型半导体芯片的剖面结构示意图,包括:
N型衬底1,电阻率为0.2-0.3Ω/cm;
设置在N型衬底1两侧的N型扩散层2,结深为60~100μm,方块电阻为800~1500Ω/□;
设置在N型扩散层2中的P型扩散层3,扩散结深为25~30μm,方块电阻为40~50Ω/□;
在正面的P型扩散层3上设置若干个N型扩散层4,扩散结深为10~12μm,方块电阻0.6~0.8Ω/□;
在围绕外围的N型扩散层上设置SiO2掩蔽层5,厚度为2.5~3.0μm;
在正面的N型扩散层设置正面金属层6,材料为Al-Ti-Ni-Ag,厚度3.5~4.0μm;
在背面的N型扩散层设置背面金属层7,材料为Al-Ti-Ni-Ag,厚度3.5~4.0μm,由此形成NPNP型半导体结构。
通过以上设置的新型半导体芯片,具有过压保护功能的半导体芯片,芯片剖面共7层结构,采用单向结构,可以充分地利用单位面积的功能耐量,由于改变了击穿后动作模式(相对于放电管模式),动作后基本是处于原工作电位箝位,因此本器件既可用于信号接口的保护,也可用于电源接口的保护。
本发明实施例的半导体芯片,选择低电阻率N型单晶材料为基础材料(即N型衬底1),双面扩散杂质磷,形成高浓度梯度的扩散区域(即N型扩散层2),再进行双面硼扩散,形成中等扩散深度的硼掺杂区域(即P型扩散层3),再进行正面发射区磷杂质扩散,形成高浓度发射极(高浓度N型扩散层4),最终采用正面金属层6和背面金属层7形成电极接触,形成NPNP型半导体结构。通过选择低电阻率单晶材料(即N型衬底1),结合N型扩散层2的N型区域,调节PNP管的基区浓度梯度,使得NPN管在进入饱和区域后无法使PNP管进入饱和区域,从而使该器件的导通压降远远高于常规器件。
具体应用实例中,通过选择不同电阻率的单晶原材料,结合N型扩散层2的扩散浓度和深度的控制,可实现对该器件进入保护动作后的导通压降进行定量控制,已实现导通压降在10~14V@20A之间的自由调节。例如,N型衬底材料电阻率0.20~0.25时,N型扩散层的扩散深度为80~100微米。N型衬底材料电阻率为0.26~0.30时,N型扩散层的扩散深度为60~80微米。常规半导体放电管为NPN管和PNP管均进入饱和区域形成正反馈,从而实现低阻导通模式。本发明通过调整纵向扩散结构,使其中PNP管无法进入饱和区域,使得该结构在大电流时保持10~14V@20A的高导通压降
与本发明实施例提供的新型半导体芯片对应的,本发明又一实施例提供了一种新型半导体芯片的制备方法,包括以下步骤:
S10,选择N型衬底材料,片厚300μm,衬底电阻率为0.2~0.3Ω/cm;
S20,清洗,生长氧化层,厚度为2μm;
S30,在N型衬底两侧进行N型扩散,采用磷扩散,扩散温度为1265-1275℃,扩散时间为12000min,结深60~100μm,方块电阻800~1500Ω/□;
S40,在N型扩散层中光刻P型扩散层,采用硼扩散,1245~1255℃,900-1100min。结深25~30μm,方块电阻40~50Ω/□;
S50,在正面的P型扩散层上光刻若干个N型扩散层,采用磷扩散,扩散温度为1145-1155℃,扩散时间为280min,结深10~12μm,方块电阻0.6~0.8Ω/□;
S60,刻蚀引线孔,表面金属化,材料为Al-Ti-Ni-Ag,厚度为3.5~4.0μm;
S70,背面金属化,材料为Al-Ti-Ni-Ag,厚度为3.5~4.0μm。
通过以上工艺制成的新型半导体芯片,可形成12V系列和24V系列的产品,器件外形可以有两类,一是贴片二端器件,目前主要贴片形式为SMB(DO-214AA)、SMC(DO-214AB)封装等;二是插件二端器件,如DO-27封装。
在二轮电动车充电应用中,参见图3,本发明又一实施例提供了一种利用此新型半导体芯片的应用电路,包括保险丝10,与保险丝串联的后级负载电路20,以及与后级负载电路并接的新型半导体芯片30,包括以下工作状态:
新型半导体芯片30在未动作前处于断态,仅有微安级的漏电;
参见图4,为断态及触发钳位阶段伏安特性曲线,其中泄漏电流IDRM为最大峰值断开状态电流按VDRM计量,工作状态下电流IT为工作状态下最大额定连续电流,开关电压VS为开关前的最大电压,峰值状态外电压VDRM为在维持断开状态的最大电压,导通状态下电压VT为额定最大电压。
当由于某种意外造成输入端的电压上升,过了触发点,所述新型半导体芯片以微秒级的速度动作,动作后拉低所述新型半导体芯片两端的电压值至低于额定电压,此时整个回路电流激增,此时新型半导体芯片处于高功率状态,此时串联在回路中的保险丝的电流大幅度超过额定值,保险丝进入熔断倒计时,此过程设计为不超过3~5个毫秒时间,一定比例的保险丝在此阶段熔断,回路被切断,保护功能实现;根据型号的不同峰值功率大约会在400W~5000W间,回路电流大约在40A~200A间。
新型半导体芯片正常抵抗持续的远超额定的大电流不超过1~3个微秒,半导体芯片将被热击穿进入芯片低阻态,公称融化热能在50~100A2S的保险丝在10~20毫秒的时间内熔断。
具体的,新型半导体芯片30在电路中的真实使命是在保护后级负载电路20的前提下造成回路大电流并瞬间(小于20毫秒)熔断回路中的保险丝10,以断开回路并结束电路工作。新型半导体芯片30触发后实际是经历两个阶段,一是芯片钳制电压阶段(见图4),时间不超过5个毫秒;二是芯片热击穿后成为低阻态(高温态阻抗小于0.4欧姆),时间不超过20毫秒。无论是第一阶段还是第二阶段只要保险丝熔断则目的达成。
应当理解,本文所述的示例性实施例是说明性的而非限制性的。尽管结合附图描述了本发明的一个或多个实施例,本领域普通技术人员应当理解,在不脱离通过所附权利要求所限定的本发明的精神和范围的情况下,可以做出各种形式和细节的改变。
Claims (9)
1.一种新型半导体芯片,其特征在于,包括:
N型衬底,电阻率为0.2-0.3Ω/cm;
设置在N型衬底两侧的N型扩散层,结深为60~100μm,方块电阻为800~1500Ω/□;
设置在N型扩散层中的P型扩散层,扩散结深为25~30μm,方块电阻为40~50Ω/□;
在正面的P型扩散层上设置若干个N型扩散层,扩散结深为10~12μm,方块电阻0.6~0.8Ω/□;
在围绕外围的N型扩散层上设置SiO2掩蔽层,厚度为2.5~3.0μm;
在正面的N型扩散层设置正面金属层,材料为Al-Ti-Ni-Ag,厚度3.5~4.0μm;
在背面的N型扩散层设置背面金属层,材料为Al-Ti-Ni-Ag,厚度3.5~4.0μm,由此形成NPNP型半导体结构。
2.如权利要求1所述的新型半导体芯片,其特征在于,选择不同电阻率的N型衬底材料,结合对N型扩散层的扩散浓度和深度的控制,用于对该器件进入保护动作后的导通压降进行定量控制。
3.如权利要求2所述的新型半导体芯片,其特征在于,N型衬底材料电阻率0.20~0.25时,N型扩散层的扩散深度为80~100微米。
4.如权利要求2所述的新型半导体芯片,其特征在于,N型衬底材料电阻率为0.26~0.30时,N型扩散层的扩散深度为60~80微米。
5.一种新型半导体芯片的制备方法,其特征在于,包括以下步骤:
S10,选择N型衬底材料,片厚300μm,衬底电阻率为0.2~0.3Ω/cm;
S20,清洗,生长氧化层,厚度为2μm;
S30,在N型衬底两侧进行N型扩散,结深60~100μm,方块电阻800~1500Ω/□;
S40,在N型扩散层中光刻P型扩散层,结深25~30μm,方块电阻40~50Ω/□;
S50,在正面的P型扩散层上光刻若干个N型扩散层,采用磷扩散,扩散温度为1145-1155℃,扩散时间为260-300min,结深10~12μm,方块电阻0.6~0.8Ω/□;
S60,刻蚀引线孔,表面金属化,材料为Al-Ti-Ni-Ag,厚度为3.5~4.0μm;
S70,背面金属化,材料为Al-Ti-Ni-Ag,厚度为3.5~4.0μm。
6.如权利要求5所述的新型半导体芯片的制备方法,其特征在于,步骤S30中,进一步包括:采用磷扩散,扩散温度为1265-1275℃,扩散时间为11000-13000min。
7.如权利要求5所述的新型半导体芯片的制备方法,其特征在于,步骤S40中,进一步包括:采用硼扩散,1245~1255℃,900-1100min。
8.一种新型半导体芯片的应用电路,其特征在于,包括保险丝,与保险丝串联的后级负载电路,以及与后级负载电路并接的新型半导体器件,包括以下工作状态:
所述新型半导体芯片在未动作前处于断态,仅有微安级的漏电;
当由于某种意外造成输入端的电压上升,过了触发点,所述新型半导体芯片以微秒级的速度动作,动作后拉低所述新型半导体芯片两端的电压值至低于额定电压,此时整个回路电流激增,此时新型半导体芯片处于高功率状态,此时串联在回路中的保险丝的电流大幅度超过额定值,保险丝进入熔断倒计时,此过程设计为不超过3~5个毫秒时间,一定比例的保险丝在此阶段熔断,回路被切断,保护功能实现;
新型半导体芯片正常抵抗持续的远超额定的大电流不超过1~3个微秒,半导体芯片将被热击穿进入芯片低阻态,公称融化热能在50~100A2 S的保险丝在10~20毫秒的时间内熔断。
9.如权利要求8所述的新型半导体芯片的应用电路,其特征在于,所述新型半导体芯片包括:
N型衬底,电阻率为0.2-0.3Ω/cm;
设置在N型衬底两侧的N型扩散层,结深为60~100μm,方块电阻为800~1500Ω/□;
设置在N型扩散层中的P型扩散层,扩散结深为25~30μm,方块电阻为40~50Ω/□;
在正面的P型扩散层上设置若干个N型扩散层,扩散结深为10~12μm,方块电阻0.6~0.8Ω/□;
在围绕外围的N型扩散层上设置SiO2掩蔽层,厚度为2.5~3.0μm;
在正面的N型扩散层设置正面金属层,材料为Al-Ti-Ni-Ag,厚度3.5~4.0μm;
在背面的N型扩散层设置背面金属层,材料为Al-Ti-Ni-Ag,厚度3.5~4.0μm,由此形成NPNP型半导体结构。
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