WO2021042979A1 - 高性能、宽安全工作区、高可靠性晶体管 - Google Patents

高性能、宽安全工作区、高可靠性晶体管 Download PDF

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WO2021042979A1
WO2021042979A1 PCT/CN2020/109798 CN2020109798W WO2021042979A1 WO 2021042979 A1 WO2021042979 A1 WO 2021042979A1 CN 2020109798 W CN2020109798 W CN 2020109798W WO 2021042979 A1 WO2021042979 A1 WO 2021042979A1
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transistor
sub
transistors
current
emitter
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PCT/CN2020/109798
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English (en)
French (fr)
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闫守礼
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山东奥天电子科技有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H01L27/0211—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique adapted for requirements of temperature
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/082—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
    • H01L27/0823—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only including vertical bipolar transistors only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/732—Vertical transistors

Definitions

  • the high-performance, wide safe working area, and high-reliability transistor triode involved in the present invention is widely used in power amplifiers, ultrasonic generators, LED drivers, stabilized power supplies, computers/tablets, flat-panel TVs/displays, instrumentation, Motor drive, industrial power supply, automobile and other electronic equipment and application fields.
  • Transistor also called semiconductor triode, bipolar transistor, transistor, and triode, is a semiconductor device that uses base input current to control collector output current.
  • Transistors can amplify weak electrical signals into stronger electrical signals, which are widely used in low frequency/high frequency/RF/microwave small signal and power amplifiers; also used as non-contact high-speed electronic switches for high-efficiency switch stability Voltage/constant current power supply, PWM motor drive, LED drive, and power control.
  • the semiconductor material of the transistor can be germanium, silicon, gallium arsenide, silicon carbide and the like.
  • the transistor has three electrodes: emitter (E), base (B), and collector (C).
  • Transistors can be divided into NPN type and PNP type according to their conductivity.
  • the emitter area (E) is of N type, and the doping concentration is higher, generally above 10 19 /cm 3 ; the base area is of P type, and the doping concentration is moderate, generally between 10 15 and 10 17 /cm 3 ; collector area It is N-type, with the lowest doping concentration, generally around 10 15 /cm 3 or lower.
  • the transistor in Figure 1 is in a forward-biased amplification state, the transistor base-emitter P-N junction is forward-biased, and the base-collector P-N junction is reverse-biased.
  • the safe operating area (SOA) of the triode refers to the range of working conditions such as voltage and current that the device can work safely and normally without damage.
  • the DC safe working area of a high-power transistor produced by an internationally renowned semiconductor company is shown in Figure 2.
  • the horizontal axis of the figure is the collector-emitter voltage (V CE ), and the vertical axis is the collector current (I C ). .
  • the peripheral curve of the safe operating area of the transistor consists of several parts.
  • the AB section is the maximum collector current (I CM )
  • the BC section is the maximum collector dissipation power (P CM )
  • the CD section is the secondary breakdown limit
  • the DE section is Collector-emitter breakdown voltage (BV CEO ).
  • the maximum collector current of this power tube is 20A (AB section), the maximum collector power consumption is 200W (BC section), and the collector-emitter breakdown voltage (BV CEO ) is 140V (DE segment).
  • the CD segment is a secondary breakdown limit curve. Its characteristic is that as the collector-emitter voltage V CE increases, the maximum collector dissipation power allowed by the transistor (I C ⁇ V CE ) Dropped sharply.
  • the collector current of the device exceeds 20A, such as 25A; or the collector power consumption of the device exceeds 200W, such as 250W, as long as the collector-emitter voltage V CE is relatively low (For example, 30V), if the secondary breakdown limit is not exceeded, the device will continue to work safely and will not be damaged immediately.
  • the C-D section and D-E section of Fig. 2 are the hard technical index limits.
  • BV CEO collector-emitter breakdown voltage
  • secondary breakdown the transistor is very fragile. Even if it is overloaded for a very short time (milliseconds or even microseconds), the device will burn out immediately.
  • the root cause of secondary breakdown is due to the negative temperature coefficient of the transistor base-emitter voltage V BE and the transconductance (gm) from the larger base-emitter voltage V BE to the collector current I C Caused by electrical and thermal instability.
  • the increase of local collector power consumption causes the local temperature of this part of the chip to increase, and the increase of temperature causes the barrier potential of the base-emitter BE PN junction to be further reduced, and the current and power consumption are further increased... It can be seen that this is a positive feedback process.
  • the positive feedback process is stable, but it will cause local overheating of the chip; and it is easy to transition to the unstable zone after the working conditions change. If each cycle of the positive feedback process is stronger than the previous cycle, then this positive feedback process is unstable; in a very short time (usually a few microseconds to hundreds of microseconds, and the thermal time constant of the chip Related), the local temperature, current density, and power consumption density of this part of the chip will greatly increase.
  • the silicon material, metal contacts, and metal wires of this part of the chip will locally overheat, melt, collapse, and penetrate, thereby
  • the collector-emitter partial short circuit occurs, the collector-emitter voltage V CE decreases rapidly, and the collector current I C increases rapidly at the same time; the transistor structure is damaged, and the device is damaged.
  • the collector and emitter are easily short-circuited (generally, the short-circuit resistance is less than 1 ⁇ ), and the current is only limited by the peripheral circuit.
  • FIGS. 3 and 4 The top view and cross-sectional view of a general transistor semiconductor chip structure are shown in FIGS. 3 and 4.
  • the emitter of the transistor in FIG. 3 is rectangular, and the emitter of the transistor in FIG. 4 is interdigitated.
  • the emitter current Due to the positive temperature coefficient of the emitter current (the emitter current has an exponential relationship with temperature), the current density will further increase at the edge of the relatively high emitter. Therefore, when the collector-emitter voltage V CE is high, the edge-collecting effect of the emitter current becomes more serious.
  • the technical problem to be solved by the present invention is to address the above shortcomings, provide high-performance, wide safe working area, high-reliability transistor devices, improve the secondary breakdown tolerance of power transistors, broaden the safe working area range, and strengthen the device and electronic products. Reliability extends the working life of the transistor and the whole machine, and thus expands the application field of power transistors.
  • the present invention adopts the following technical solutions:
  • the high-performance, wide safe working area, and high-reliability transistors include several independent sub-transistors.
  • the sub-transistors are formed by the entire division interval of the original large transistor.
  • Each sub-transistor realizes the division of the total current of the transistor, making the transistor as a whole
  • the temperature of each part is uniform, and the excessive increase of the local current of the transistor is effectively suppressed.
  • a plurality of sub-transistors are arranged on a single crystal silicon wafer.
  • the base area of the transistor is divided into blocks, the base of the transistor is divided into blocks, and the emitter area of the transistor is divided into blocks.
  • the sub-transistors after the base and emitter are divided in parallel are connected in parallel, and the bases of the sub-transistors are all connected in series.
  • the current resistance is used to separate the small blocks in the base area, and the current limiting resistor is connected in series with the base of the sub-transistor to achieve the division of the total current of the transistor, so as to achieve the purpose of uniform temperature of all sub-transistors in the transistor.
  • the resistance value of the middle sub-transistor base series current-limiting resistor on the monocrystalline silicon wafer is high and the base of the surrounding sub-transistors
  • the resistance value of the series current limiting resistor is low, so that the current of the middle sub-transistor on the monocrystalline silicon chip is low, and the current of the surrounding sub-transistors is high, so that the temperature of all sub-transistors in the transistor can be made uniform.
  • the resistance value of the series current limiting resistors in the base of the sub-transistors is the same, and the current of all the sub-transistors flows equally. In this way, the temperature of all sub-transistors in the transistor can be made uniform.
  • each sub-transistor is connected in series with a current-limiting resistor, the lower end of the current-limiting resistor is connected to the base of the sub-transistor, and the upper ends of all the base-limiting current resistors are connected together as the base of the transistor as a whole;
  • the emitters of the sub-transistors on a single crystal silicon wafer are connected together as the emitter of the entire transistor; the collectors of the sub-transistors on the same single crystal silicon wafer are connected together as the collector of the entire transistor.
  • each sub-transistor to divide the total current of the transistor is as follows:
  • the emitter area of the transistor Divide the emitter area of the transistor into blocks. While the emitter of the transistor is divided into blocks, the base area of the transistor may not be divided into blocks. After the block, the emitter area can share a base area, and the sub-transistors after the emitter block are connected in parallel. Together, the emitters of the sub-transistors are connected in series with current-limiting resistors to separate the small blocks in the emitter area. By connecting the current-limiting resistors in series with the emitters of the sub-transistors, the total current of the transistor is divided to reach all sub-transistors. The purpose of the temperature uniformity of the transistor.
  • the middle sub-transistor emitter series current limiting resistor on the monocrystalline silicon wafer sets the middle sub-transistor emitter series current limiting resistor on the monocrystalline silicon wafer to have a high resistance value and the surrounding sub-transistor emitters.
  • the resistance value of the series current limiting resistor is low, so that the current of the middle sub-transistor on the monocrystalline silicon chip is low, and the current of the surrounding sub-transistors is high, so that the temperature of all sub-transistors in the transistor can be made uniform.
  • the resistance value of the current limiting resistor in series with the emitter of the sub-transistor is the same, and the current of all the sub-transistors flows equally. In this way, the temperature of all sub-transistors in the transistor can be made uniform.
  • the bases of the sub-transistors on the same single crystal silicon wafer are connected together as the base of the transistor as a whole; the emitter of each sub-transistor is connected in series with a current-limiting resistor, and the upper end of the current-limiting resistor is connected to the emitter of the sub-transistor , The lower ends of the current-limiting resistors are connected together as the emitter of the transistor as a whole; the collectors of the sub-transistors on the same monocrystalline silicon chip are connected together as the collector of the transistor as a whole.
  • the base area and emitter area of the transistor are divided into blocks, and the sub-transistors after the base and emitter are divided into blocks are connected in parallel.
  • the entire transistor is realized by connecting the emitter-emitter and the base of the sub-transistor with a current limiting resistor in series The division of the total current achieves the goal of uniform temperature of all sub-transistors in the transistor.
  • the sub-transistors are evenly distributed on the monocrystalline silicon wafer, and the resistance values of the base and/or emitter series current limiting resistors of the sub-transistors are not the same, set the intermediate sub-transistor base and/or emitter series current limiting resistors on the monocrystalline silicon wafer
  • the resistance of the surrounding sub-transistor is high, and the resistance of the surrounding sub-transistor base and/or the emitter series current limiting resistor is low, so that the current of the middle sub-transistor on the monocrystalline silicon chip is low, and the current of the surrounding sub-transistor is high, so that the transistor can be
  • the temperature of all sub-transistors is uniform.
  • the resistance of the base series current limiting resistor of the sub-transistor is the same, and the resistance of the emitter series current limiting resistor is the same.
  • the value is also the same, and the current of all sub-transistors flows equally, so that the temperature of all sub-transistors in the transistor can be made uniform.
  • each sub-transistor is connected in series with a current-limiting resistor, and the bases of the sub-transistors on the same monocrystalline silicon chip are connected together to form the base of the transistor as a whole;
  • the emitter of each sub-transistor is connected in series with a current-limiting resistor, Connect the emitters of the sub-transistors on the same single crystal silicon wafer to form the emitter of the entire transistor; connect the collectors of the sub-transistors on the same single crystal silicon wafer to form the collector of the entire transistor.
  • the distributed diffusion resistance of the emitter area and the distribution of the emitter current are changed to improve the edge effect of the emitter current, so that the current of the sub-transistor is in each of the emitters.
  • the area is evenly distributed.
  • the present invention adopts the above technical solutions and has the following technical effects:
  • the transistor of the present invention significantly increases the effective chip area of the transistor, and improves the current amplification factor, linearity, and frequency response when the transistor has a large current;
  • the emitter and collector currents of the transistor of the present invention are evenly distributed on the entire chip, eliminating local hot spots of the chip, and reducing the junction temperature of the hottest spot of the chip, even if the transistor works in the collector-emitter below point C in Figure 2 Extreme voltage V CE , the working life of the transistor has also been extended, and the working reliability of the transistor and electronic equipment has also been significantly improved;
  • the transistor designed according to the present invention is several times to several tens of times larger than the current industry transistor's secondary breakdown tolerance, and the safe working area of the transistor is greatly expanded;
  • the secondary breakdown limit curve can be outside the maximum allowable power consumption curve, thereby alleviating or even completely eliminating the restriction on the safe operating area of the transistor by the secondary breakdown of the transistor;
  • the linear collector-emitter effective working voltage V CE is generally limited to 100V due to the secondary breakdown problem, otherwise the transistor will work in a severely limited secondary breakdown The reliability of the work area, devices and electronic systems is greatly compromised.
  • the high-power transistors designed and produced by using the patented technology of the present invention can extend the linear working voltage to more than 300V, which significantly broadens the application range of silicon-based high-power transistors;
  • the present invention is applicable to transistors manufactured by all element semiconductor materials and compound semiconductor materials, such as germanium, silicon, gallium arsenide, silicon carbide, etc.; applicable to transistors with homojunction transistors and heterojunction structures Transistor.
  • the present invention is also suitable for improving the current uniformity of other power devices, such as MOS tubes, IGBTs, thyristors, etc., working in the linear region, eliminating local hot spots on the chip, prolonging the working life of power devices, and improving power devices (electronic equipment) reliability.
  • other power devices such as MOS tubes, IGBTs, thyristors, etc.
  • FIG. 1 is a schematic diagram of the structure of an NPN transistor in the background technology of the present invention
  • FIG. 2 is a diagram of the DC SOA (DC SOA) of the transistor in the background technology of the present invention
  • FIG. 3 is a top view and a cross-sectional view of a rectangular base and emitter structure of a transistor in the background of the present invention
  • FIG. 4 is a top view and a cross-sectional view of the rectangular base and interdigital emitter structure of a transistor in the background of the present invention
  • FIG. 5 is a schematic diagram of a cross-sectional structure of a transistor in the background art of the present invention.
  • Fig. 6 is a matrix arrangement diagram of square small blocks of neutron transistors on a single crystal silicon wafer in the embodiment 1-6 of the present invention
  • FIG. 7 is a honeycomb arrangement diagram of round small pieces of neutron transistors on a single crystal silicon wafer in the embodiment 1-6 of the present invention.
  • FIG. 8 is a schematic diagram of the base division block of the transistor in the embodiment 1-2 of the present invention.
  • FIG. 9 is an equivalent circuit diagram of the transistor base division block and the base isolation resistance added in the embodiment 1-2 of the present invention.
  • FIG. 10 is a schematic diagram of a transistor emitter partition block in Embodiment 3-4 of the present invention.
  • 11 is an equivalent circuit diagram of the transistor emitter division block and the emitter isolation resistor added in the embodiment 3-4 of the present invention.
  • FIG. 12 is a schematic diagram of the transistor base segmentation block and the addition of base and emitter isolation resistors in the embodiment 5-6 of the present invention.
  • FIG. 13 is a diagram of temperature distribution of transistors in embodiments 1-6 of the present invention.
  • FIG. 14 is a diagram showing the uniform distribution of neutron transistors and the distribution of transistor temperature in embodiments 1, 3, and 5 of the present invention.
  • 15 is a distribution diagram of neutron transistors sparsely distributed in the middle and densely distributed around the neutron transistors and the temperature of the transistors in embodiments 2, 4, and 6 of the present invention;
  • FIG. 16 is an equivalent circuit diagram of the transistor base distinguishing block or emitter distinguishing block in Embodiment 7 of the present invention, and no isolation resistance is added;
  • FIG. 17 shows that in the seventh embodiment of the present invention, a slot is formed in the emitter region of the sub-transistor to improve the current collecting effect at the emitter of the sub-transistor.
  • Embodiment 1 a high-performance, wide safe working area, and high-reliability transistor, including several independent sub-transistors.
  • the sub-transistors are formed by dividing the original large transistor into a whole interval, and the original large transistor is divided into several small sub-transistors.
  • Transistor the division adopts electrical separation, that is, the small sub-transistors divided into are electrically separated, not connected to each other to conduct electricity, but they are still a whole in physical form.
  • the number of divided sub-transistors can be set according to performance requirements and production technology, ranging from tens to thousands; each sub-transistor realizes the division of the total current of the transistor, so that the temperature of each part of the transistor is uniform, and the local current of the transistor is excessively increased. Is effectively suppressed.
  • the place marked n- is the collector of the transistor
  • the place marked p is the base of the transistor
  • the place marked n+ is the emitter of the transistor
  • the base is the island in the collector
  • the emitter is again It is an island in the base and cannot touch the outermost collector. It is surrounded by bases.
  • a general transistor has only one base region, and the base region has a larger emitter region.
  • the base area of the transistor is divided into blocks. After the base is divided into blocks, there will be multiple base islands, so the emitter area must also be divided. Each base island has an emitter island, so the transistor base is divided into blocks. At the same time, the entire emitter area of the transistor is also divided into blocks, and the sub-transistors after the base and emitter are divided in parallel are connected in parallel.
  • the bases of the sub-transistors are connected in series with current-limiting resistors to separate the small blocks in the base area.
  • the current limiting resistor is connected in series with the base of the sub-transistor to realize the division of the total current of the transistor, so as to achieve the goal of uniform temperature of all sub-transistors in the transistor.
  • the current limiting resistor can be replaced by resistive electronic components such as polysilicon resistors, thin film resistors, junction field effect transistors JFET, insulated gate field effect (IGFET/MOSFET), etc.
  • resistive electronic components such as polysilicon resistors, thin film resistors, junction field effect transistors JFET, insulated gate field effect (IGFET/MOSFET), etc.
  • a plurality of the sub-transistors are arranged on a single crystal silicon wafer.
  • the sub-transistors on the single crystal silicon wafer can be arranged in a matrix, honeycomb arrangement, and other arrangements.
  • Each sub-transistor on a single crystal silicon wafer can adopt a square, circular shape, or a triangle, rectangle, pentagon, hexagon, octagon, ellipse, hollow pattern, and irregular shape, etc. .
  • the arrangement order of the sub-transistors on the monocrystalline silicon wafer can be a regular arrangement or an irregular arrangement.
  • each sub-transistor is connected in series with a current-limiting resistor, the lower end of the current-limiting resistor is connected to the base of the sub-transistor, and the upper ends of all base-limiting current resistors are connected together as the base of the transistor as a whole;
  • the emitters of the sub-transistors are connected together as the emitter of the entire transistor; the collectors of the sub-transistors on the same single crystal silicon wafer are connected together as the collector of the entire transistor.
  • the resistance of the series current limiting resistors in the base of the sub-transistors is the same, and the current of all the sub-transistors flows equally, the temperature of the middle sub-transistor on the monocrystalline silicon wafer is high, The temperature of the surrounding sub-transistors is low, due to the slow heat dissipation in the middle of the sub-transistors on the monocrystalline silicon wafer and the fast heat dissipation of the surrounding sub-transistors, so that the temperature of all the sub-transistors in the transistor cannot reach uniformity.
  • the resistance values of the base series current limiting resistors of the sub-transistors are not the same.
  • the resistance value of the current limiting resistor in series with the base of the surrounding sub-transistor is low, so that the current of the middle sub-transistor on the monocrystalline silicon chip is low, and the current of the surrounding sub-transistor is high, so that the temperature of all sub-transistors in the transistor can be made uniform.
  • the transistor prepared by the present invention is suitable for transistors made of various materials.
  • the present invention is also suitable for improving the temperature uniformity of other power devices, such as MOS tubes, IGBTs, thyristors, etc., eliminates local hot spots on the chip, prolongs the working life of power devices, and improves Reliability of power devices and electronic equipment.
  • Embodiment 2 a high-performance, wide safe working area, and high-reliability transistor, including several independent sub-transistors.
  • the sub-transistors are formed by the entire division interval of the original large transistor, and the original large transistor is divided into several small sub-transistors.
  • Transistor, the division adopts electrical separation, that is, the small sub-transistors divided into are electrically separated, not connected to each other to conduct electricity, but they are still a whole in physical form.
  • the number of divided sub-transistors can be set according to performance requirements and production technology, ranging from tens to thousands; each sub-transistor realizes the division of the total current of the transistor, so that the temperature of each part of the transistor is uniform, and the local current of the transistor is excessively increased. Is effectively suppressed.
  • the place marked n- is the collector of the transistor
  • the place marked p is the base of the transistor
  • the place marked n+ is the emitter of the transistor
  • the base is the island in the collector
  • the emitter is again It is an island in the base and cannot touch the outermost collector. It is surrounded by bases.
  • a general transistor has only one base region, and the base region has a larger emitter region.
  • the base area of the transistor is divided into blocks. After the base is divided into blocks, there will be multiple base islands, so the emitter area must also be divided. Each base island has an emitter island, so the transistor base is divided into blocks. At the same time, the entire emitter area of the transistor is also divided into blocks, and the sub-transistors after the base and emitter are divided in parallel are connected in parallel.
  • the bases of the sub-transistors are connected in series with current-limiting resistors to separate the small blocks in the base area.
  • the current limiting resistor is connected in series with the base of the sub-transistor to realize the division of the total current of the transistor, so as to achieve the goal of uniform temperature of all sub-transistors in the transistor.
  • the current limiting resistor can be replaced by resistive electronic components such as polysilicon resistors, thin film resistors, junction field effect transistors JFET, insulated gate field effect (IGFET/MOSFET) and the like.
  • a plurality of the sub-transistors are arranged on a single crystal silicon wafer.
  • the sub-transistors on the single crystal silicon wafer can be arranged in a matrix, honeycomb arrangement, and other arrangements.
  • Each sub-transistor on a single crystal silicon wafer can adopt a square, circular shape, or a triangle, rectangle, pentagon, hexagon, octagon, ellipse, hollow pattern, and irregular shape, etc. .
  • the arrangement order of the sub-transistors on the monocrystalline silicon wafer can be a regular arrangement or an irregular arrangement.
  • each sub-transistor is connected in series with a current-limiting resistor, the lower end of the current-limiting resistor is connected to the base of the sub-transistor, and the upper ends of all base-limiting current resistors are connected together as the base of the transistor as a whole;
  • the emitters of the sub-transistors are connected together as the emitter of the entire transistor; the collectors of the sub-transistors on the same single crystal silicon wafer are connected together as the collector of the entire transistor.
  • the resistance of the series current limiting resistors in the base of the sub-transistors is the same, and the current of all the sub-transistors flows equally, the temperature of the middle sub-transistor on the monocrystalline silicon wafer is high, The temperature of the surrounding sub-transistors is low, due to the slow heat dissipation in the middle of the sub-transistors on the monocrystalline silicon wafer and the fast heat dissipation of the surrounding sub-transistors, so that the temperature of all the sub-transistors in the transistor cannot reach uniformity.
  • the sub-transistors are sparsely distributed in the middle of the monocrystalline silicon wafers and densely distributed around them, so that the heat dissipation speed of the sub-transistors on the monocrystalline silicon wafers is the same, and the resistance values of the series current limiting resistors of the sub-transistors are the same.
  • the currents of the transistors flow evenly, so that the temperature of all sub-transistors in the transistor can be made uniform.
  • the transistor prepared by the present invention is suitable for transistors made of various materials.
  • the present invention is also suitable for improving the temperature uniformity of other power devices, such as MOS tubes, IGBTs, thyristors, etc., eliminates local hot spots on the chip, prolongs the working life of power devices, and improves Reliability of power devices and electronic equipment.
  • Embodiment 3 high-performance, wide safe working area, high-reliability transistors, including several independent sub-transistors, the sub-transistors are formed by the entire division interval of the original large transistor, the original large transistor is divided into several small sub-transistors Transistor, the division adopts electrical separation, that is, the small sub-transistors divided into are electrically separated, not connected to each other to conduct electricity, but they are still a whole in physical form.
  • the number of divided sub-transistors can be set according to performance requirements and production technology, ranging from tens to thousands; each sub-transistor realizes the division of the total current of the transistor, so that the temperature of each part of the transistor is uniform, and the local current of the transistor is excessively increased. Is effectively suppressed.
  • the place marked n- is the collector of the transistor
  • the place marked p is the base of the transistor
  • the place marked n+ is the emitter of the transistor
  • the base is the island in the collector
  • the emitter is again It is an island in the base and cannot touch the outermost collector. It is surrounded by bases.
  • a general transistor has only one base region, and the base region has a larger emitter region.
  • the emitter area of the transistor Divide the emitter area of the transistor into blocks. While the emitter of the transistor is divided into blocks, the base area of the transistor may not be divided into blocks. After the block, the emitter area can share a base area, and the sub-transistors after the emitter block are connected in parallel. Together, the emitters of the sub-transistors are connected in series with current-limiting resistors to separate the small blocks in the emitter area. By connecting the current-limiting resistors in series with the emitters of the sub-transistors, the total current of the transistor is divided to reach all sub-transistors. The purpose of the temperature uniformity of the transistor.
  • the current limiting resistor can be replaced by resistive electronic components such as polysilicon resistors, thin film resistors, junction field effect transistors JFET, insulated gate field effect (IGFET/MOSFET) and the like.
  • a plurality of the sub-transistors are arranged on a single crystal silicon wafer.
  • the sub-transistors on the single crystal silicon wafer can be arranged in a matrix, honeycomb arrangement, and other arrangements.
  • Each sub-transistor on a single crystal silicon wafer can adopt a square, circular shape, or a triangle, rectangle, pentagon, hexagon, octagon, ellipse, hollow pattern, and irregular shape, etc. .
  • the arrangement order of the sub-transistors on the monocrystalline silicon wafer can be a regular arrangement or an irregular arrangement.
  • each sub-transistor emitter is connected in series with a current-limiting resistor, and the upper end of the current-limiting resistor is connected to the emitter of the sub-transistor to limit the current
  • the lower ends of the resistors are connected together as the emitter of the entire transistor; the collectors of the sub-transistors on the same single crystal silicon wafer are connected together as the collector of the entire transistor.
  • the emitters of the sub-transistors have the same resistance in series with the current limiting resistor, and the currents of all the sub-transistors flow evenly, the temperature of the middle sub-transistor on the monocrystalline silicon wafer is high, The temperature of the surrounding sub-transistors is low, due to the slow heat dissipation in the middle of the sub-transistors on the monocrystalline silicon wafer and the fast heat dissipation of the surrounding sub-transistors, so that the temperature of all the sub-transistors in the transistor cannot reach uniformity.
  • the resistance of the emitter series current limiting resistor of the sub-transistor is different, and the resistance value of the middle sub-transistor emitter series current limiting resistor on the single crystal silicon wafer is set to be high ,
  • the resistance value of the current limiting resistor in series with the base of the surrounding sub-transistor is low, so that the current of the middle sub-transistor on the monocrystalline silicon chip is low, and the current of the surrounding sub-transistor is high, so that the temperature of all sub-transistors in the transistor can be made uniform.
  • the transistor prepared by the present invention is suitable for transistors made of various materials.
  • the present invention is also suitable for improving the temperature uniformity of other power devices, such as MOS tubes, IGBTs, thyristors, etc., eliminates local hot spots on the chip, prolongs the working life of power devices, and improves Reliability of power devices and electronic equipment.
  • Embodiment 4 high-performance, wide safe working area, high-reliability transistors, including several independent sub-transistors, the sub-transistors are formed by the entire division interval of the original large transistor, the original large transistor is divided into a number of small sub-transistors Transistor, the division adopts electrical separation, that is, the small sub-transistors divided into are electrically separated, not connected to each other to conduct electricity, but they are still a whole in physical form.
  • the number of divided sub-transistors can be set according to performance requirements and production technology, ranging from tens to thousands; each sub-transistor realizes the division of the total current of the transistor, so that the temperature of each part of the transistor is uniform, and the local current of the transistor is excessively increased. Is effectively suppressed.
  • the place marked n- is the collector of the transistor
  • the place marked p is the base of the transistor
  • the place marked n+ is the emitter of the transistor
  • the base is the island in the collector
  • the emitter is again It is an island in the base and cannot touch the outermost collector. It is surrounded by bases.
  • a general transistor has only one base region, and the base region has a larger emitter region.
  • the emitter area of the transistor Divide the emitter area of the transistor into blocks. While the emitter of the transistor is divided into blocks, the base area of the transistor may not be divided into blocks. After the block, the emitter area can share a base area, and the sub-transistors after the emitter block are connected in parallel. Together, the emitters of the sub-transistors are connected in series with current-limiting resistors to separate the small blocks in the emitter area. By connecting the current-limiting resistors in series with the emitters of the sub-transistors, the total current of the transistor is divided to reach all sub-transistors. The purpose of the temperature uniformity of the transistor.
  • the current limiting resistor can be replaced by resistive electronic components such as polysilicon resistors, thin film resistors, junction field effect transistors JFET, insulated gate field effect (IGFET/MOSFET) and the like.
  • a plurality of the sub-transistors are arranged on a single crystal silicon wafer.
  • the sub-transistors on the single crystal silicon wafer can be arranged in a matrix, honeycomb arrangement, and other arrangements.
  • Each sub-transistor on a single crystal silicon wafer can adopt a square, circular shape, or a triangle, rectangle, pentagon, hexagon, octagon, ellipse, hollow pattern, and irregular shape, etc. .
  • the arrangement order of the sub-transistors on the monocrystalline silicon wafer can be a regular arrangement or an irregular arrangement.
  • each sub-transistor emitter is connected in series with a current-limiting resistor, and the upper end of the current-limiting resistor is connected to the emitter of the sub-transistor to limit the current
  • the lower ends of the resistors are connected together as the emitter of the entire transistor; the collectors of the sub-transistors on the same single crystal silicon wafer are connected together as the collector of the entire transistor.
  • the emitters of the sub-transistors have the same resistance in series with the current limiting resistor, and the currents of all the sub-transistors flow evenly, the temperature of the middle sub-transistor on the monocrystalline silicon wafer is high, The temperature of the surrounding sub-transistors is low, due to the slow heat dissipation in the middle of the sub-transistors on the monocrystalline silicon wafer and the fast heat dissipation of the surrounding sub-transistors, so that the temperature of all the sub-transistors in the transistor cannot reach uniformity.
  • the sub-transistors are sparsely distributed in the monocrystalline silicon wafers and densely distributed around them, so that the heat dissipation speeds of the sub-transistors on the monocrystalline silicon wafers are the same, and the resistance values of the series current limiting resistors of the emitters of the sub-transistors are the same.
  • the currents of the transistors flow evenly, so that the temperature of all sub-transistors in the transistor can be made uniform.
  • the transistor prepared by the present invention is suitable for transistors made of various materials.
  • the present invention is also suitable for improving the temperature uniformity of other power devices, such as MOS tubes, IGBTs, thyristors, etc., eliminates local hot spots on the chip, prolongs the working life of power devices, and improves Reliability of power devices and electronic equipment.
  • a high-performance, wide safe working area, and high-reliability transistor includes several independent sub-transistors.
  • the sub-transistors are formed by the entire division interval of the original large transistor, and the original large transistor is divided into several small sub-transistors.
  • Transistor, the division adopts electrical separation, that is, the small sub-transistors divided into are electrically separated, not connected to each other to conduct electricity, but they are still a whole in physical form.
  • the number of divided sub-transistors can be set according to performance requirements and production technology, ranging from tens to thousands; each sub-transistor realizes the division of the total current of the transistor, so that the temperature of each part of the transistor is uniform, and the local current of the transistor is excessively increased. Is effectively suppressed.
  • the place marked n- is the collector of the transistor
  • the place marked p is the base of the transistor
  • the place marked n+ is the emitter of the transistor
  • the base is the island in the collector
  • the emitter is again It is an island in the base and cannot touch the outermost collector. It is surrounded by bases.
  • a general transistor has only one base region, and the base region has a larger emitter region.
  • the current limiting resistor can be replaced by resistive electronic components such as polysilicon resistors, thin film resistors, junction field effect transistors JFET, insulated gate field effect (IGFET/MOSFET) and the like.
  • a plurality of the sub-transistors are arranged on a single crystal silicon wafer.
  • the sub-transistors on the single crystal silicon wafer can be arranged in a matrix, honeycomb arrangement, and other arrangements.
  • Each sub-transistor on a single crystal silicon wafer can adopt a square, circular shape, or a triangle, rectangle, pentagon, hexagon, octagon, ellipse, hollow pattern, and irregular shape, etc. .
  • the arrangement order of the sub-transistors on the monocrystalline silicon wafer can be a regular arrangement or an irregular arrangement.
  • each sub-transistor is connected in series with a current-limiting resistor, and the bases of the sub-transistors on the same monocrystalline silicon chip are connected together as the base of the entire transistor; the emitter of each sub-transistor is connected in series with a current-limiting resistor.
  • the emitters of the sub-transistors on a single crystal silicon wafer are connected together as the emitter of the entire transistor; the collectors of the sub-transistors on the same single crystal silicon wafer are connected together as the collector of the entire transistor.
  • the resistance of the base series current limiting resistor of the sub-transistor is the same, and the resistance value of the emitter series current limiting resistor is also the same, and the current of all sub-transistors flows equally. Then the temperature of the middle sub-transistor on the monocrystalline silicon chip is high, and the temperature of the surrounding sub-transistors is low. Because the middle sub-transistor on the monocrystalline silicon chip dissipates heat slowly and the surrounding sub-transistors quickly dissipate heat, the temperature of all sub-transistors in the transistor cannot reach uniformity.
  • the resistance of the emitter series current-limiting resistor is high, and the resistance of the surrounding sub-transistor base and/or the emitter series current-limiting resistor is low, that is, set the intermediate sub-transistor emitter and base series current-limiting resistor on the monocrystalline silicon wafer
  • the resistance values are all high, and the resistance values of the series current limiting resistors of the emitter and base of the surrounding sub-transistors are both low; or set the resistance value of the series current limiting resistance of the sub-transistor emitter on the monocrystalline silicon chip to be the same, and the middle sub-transistor on the monocrystalline silicon chip has the same resistance value.
  • the resistance value of the series current limiting resistor of the transistor base is high, and the resistance value of the series current limiting resistor of the surrounding sub-transistor base is low; the resistance value of the series current limiting resistor of the sub-transistor on the monocrystalline silicon chip can also be set to be the same.
  • the on-chip middle sub-transistor emitter series current-limiting resistor has high resistance, and the surrounding sub-transistor emitter series current-limiting resistor has a low resistance value, so that the current of the middle sub-transistor on the monocrystalline silicon wafer is low, and the current of the surrounding sub-transistor is high. In this way, the temperature of all sub-transistors in the transistor can be made uniform.
  • the transistor prepared by the present invention is suitable for transistors made of various materials.
  • the present invention is also suitable for improving the temperature uniformity of other power devices, such as MOS tubes, IGBTs, thyristors, etc., eliminates local hot spots on the chip, prolongs the working life of power devices, and improves Reliability of power devices and electronic equipment.
  • Embodiment 6 a high-performance, wide safe working area, and high-reliability transistor, including several independent sub-transistors.
  • the sub-transistors are formed by the entire division interval of the original large transistor, and the original large transistor is divided into several small sub-transistors.
  • Transistor, the division adopts electrical separation, that is, the small sub-transistors divided into are electrically separated, not connected to each other to conduct electricity, but they are still a whole in physical form.
  • the number of divided sub-transistors can be set according to performance requirements and production technology, ranging from tens to thousands; each sub-transistor realizes the division of the total current of the transistor, so that the temperature of each part of the transistor is uniform, and the local current of the transistor is excessively increased. Is effectively suppressed.
  • the place marked n- is the collector of the transistor
  • the place marked p is the base of the transistor
  • the place marked n+ is the emitter of the transistor
  • the base is the island in the collector
  • the emitter is again It is an island in the base and cannot touch the outermost collector. It is surrounded by bases.
  • a general transistor has only one base region, and the base region has a larger emitter region.
  • the current limiting resistor can be replaced by resistive electronic components such as polysilicon resistors, thin film resistors, junction field effect transistors JFET, insulated gate field effect (IGFET/MOSFET) and the like.
  • a plurality of the sub-transistors are arranged on a single crystal silicon wafer.
  • the sub-transistors on the single crystal silicon wafer can be arranged in a matrix, honeycomb arrangement, and other arrangements.
  • Each sub-transistor on a single crystal silicon wafer can adopt a square, circular shape, or a triangle, rectangle, pentagon, hexagon, octagon, ellipse, hollow pattern, and irregular shape, etc. .
  • the arrangement order of the sub-transistors on the monocrystalline silicon wafer can be a regular arrangement or an irregular arrangement.
  • each sub-transistor is connected in series with a current-limiting resistor, and the bases of the sub-transistors on the same monocrystalline silicon chip are connected together as the base of the entire transistor; the emitter of each sub-transistor is connected in series with a current-limiting resistor.
  • the emitters of the sub-transistors on a single crystal silicon wafer are connected together as the emitter of the entire transistor; the collectors of the sub-transistors on the same single crystal silicon wafer are connected together as the collector of the entire transistor.
  • the resistance of the base series current limiting resistor of the sub-transistor is the same, and the resistance value of the emitter series current limiting resistor is also the same, and the current of all sub-transistors flows equally. Then the temperature of the middle sub-transistor on the monocrystalline silicon chip is high, and the temperature of the surrounding sub-transistors is low. Because the middle sub-transistor on the monocrystalline silicon chip dissipates heat slowly and the surrounding sub-transistors quickly dissipate heat, the temperature of all sub-transistors in the transistor cannot reach uniformity.
  • the resistance values of the series current limiting resistors in the base of the sub-transistors are the same, and the emitters The resistance value of the series current-limiting resistor is also the same, and the current of all sub-transistors flows equally, so that the temperature of all sub-transistors in the transistor can be made uniform.
  • the transistor prepared by the present invention is suitable for transistors made of various materials.
  • the present invention is also suitable for improving the temperature uniformity of other power devices, such as MOS tubes, IGBTs, thyristors, etc., eliminates local hot spots on the chip, prolongs the working life of power devices, and improves Reliability of power devices and electronic equipment.
  • the collector current I C_unit of each sub-transistor is basically around I C_total /n, and its total collector current I C_total It is the collector current of the entire transistor chip, n is the number of sub-transistors, and the collector current is more evenly distributed across the entire transistor chip.
  • the collector current I C is larger, the base current is also larger Since the base current flows laterally through the laterally distributed resistance of the base, a potential difference will be generated, and the base-emitter voltage VBE at the edge of the emitter will be higher than that at the center of the emitter.
  • the emitter current density has an exponential relationship with VBE
  • the emitter current will have a side effect, that is, the current density at the edge of the emitter will be much greater than the current density at the center of the emitter, as shown in Figure 5.
  • the dissipated power density and temperature of the part with large current density are also high. Due to the positive temperature coefficient of the emitter current (the emitter current has an exponential relationship with temperature), the current density will further increase at the edge of the relatively high emitter. Therefore, when the collector-emitter voltage V CE is high, the edge-collecting effect of the emitter current becomes more serious.
  • the present invention adopts the following methods:
  • the distribution of diffusion resistance current in the emitter area is changed, and the edge effect of the emitter current is improved, so that the emitter current is evenly distributed in each area of the emitter of the sub-transistor, further improving
  • the secondary breakdown tolerance of the entire transistor improves the performance of the transistor.
  • the method for solving the edge effect of the emitter current in this embodiment is also applicable to the implementation under the condition that the base and emitter of the sub-transistor have no series resistance.

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Abstract

一种高性能、宽安全工作区、高可靠性晶体管，包括若干个相互独立的子晶体管，子晶体管是由原大晶体管整个分割间隔而成，在每个子晶体管实现晶体管整体总电流的分割，使得晶体管整体各部分的温度均一，晶体管局部电流过度增长被有效抑制，多个子晶体管排列在一块单晶硅片上。具有以下优点：提高了功率晶体管的二次击穿耐量，拓宽了其安全工作区范围，加强了器件及电子产品的可靠性，延长了晶体管及整机的工作寿命，也扩展了功率晶体管的应用领域。

Description

高性能、宽安全工作区、高可靠性晶体管 技术领域
本发明涉及的高性能、宽安全工作区、高可靠性晶体三级管，广泛应用于功率放大器、超声波发生器、LED驱动器、稳压电源、计算机/平板电脑、平板电视/显示器、仪器仪表、电机驱动、工业电源、汽车等电子设备及应用领域。
背景技术
晶体三极管，也称半导体三极管、双极性晶体管、晶体管、和三极管，是一种用基极输入电流控制集电极输出电流的半导体器件。
晶体三极管能够把微弱的电信号放大成强度较大的电信号，广泛用于低频/高频/射频/微波小信号及功率放大器；也用作无触点高速电子开关，应用于高效率开关稳压/恒流电源、PWM电机驱动、LED驱动、以及功率控制。
晶体管的半导体材料可以为锗、硅、砷化镓、碳化硅等。
晶体三极管有三个电极：发射极(E)、基极(B)、和集电极(C)。
晶体三极管按导电极性可分为NPN型和PNP型两种。
NPN型晶体三极管的结构示意图和外部电路的接法如图1所示：
其中发射区(E)为N型，掺杂浓度较高，一般在10 19/cm 3以上；基区为P型，掺杂浓度适中，一般在10 15到10 17/cm 3；集电区为N型，掺杂浓度最低，一般在10 15/cm 3左右或者更低。
图1中的晶体管处于正向偏置放大状态，晶体管基极-发射极的P-N结为正向偏置，而基极-集电极的P-N结为反向偏置。
晶体三级管的安全工作区(SOA)，是指器件能够安全正常工作而不会损坏的电压电流等工作条件的范围。
某国际知名半导体公司生产的一种大功率晶体三极管的直流安全工作区如图2所示，图中横轴为集电极-发射极电压(V CE)，纵轴为集电极电流(I C)。
晶体管安全工作区的外围曲线由几部分组成，A-B段为最大集电极电流(I CM)，B-C段为集电极最大耗散功率(P CM)，C-D段为二次击穿限制，D-E段为集电极-发射极击穿电压(BV CEO)。
图2中的横轴和纵轴都为对数坐标，如果都改为线性坐标，B-C段则为I C·V CE＝P CM的双曲线。
从图2可以看出，本功率管的最大集电极电流为20A(A-B段)，最大集电极功耗为200W(B-C段)，集电极-发射极击穿电压(BV CEO)为140V(D-E段)。
如前所述，C-D段为二次击穿限制曲线，其特点是，随着集电极-发射极电压V CE的升高，晶体管所允许承载的集电极最大耗散功率(I C·V CE)急剧降低。
图2中，当集电极-发射极电压V CE在40V时，集电极允许承载的最大耗散功率为200W；当集电极-发射极电压V CE升高到80V时，集电极允许承载的最大耗散功率显著降低到64W；当集电极-发射极电压V CE升高到140V时，集电极允许承载的最大耗散功率进一步降低到32W左右，仅为其标称集电极最大耗散功率200W的16％。
由此可见，二次击穿严重限制了晶体管的安全工作区范围。
另外值得注意的是，图2中A-B段和B-C段，是软技术指标限制。
也就是说，在短时间(如5秒)内，器件的集电极电流超过20A，如25A；或者器件的集电极功耗超过200W，如250W，只要集电极-发射极电压V CE相对比较低(如30V)，没有超过二次击穿限制，器件会继续安全工作，不会立即发生损坏。
当然，如果器件长期在A-B段和B-C段外的区域工作，因为器件结温过高，会发生晶体管过早老化失效，影响器件及电子系统长期稳定工作的可靠性。
图2的C-D段和D-E段则为硬技术指标限制。
器件在工作过程中，即使超出曲线比较短的时间，甚至是几毫秒甚至几微秒，也会立即发生烧毁、失效。
从集电极-发射极击穿电压(BV CEO)和二次击穿这两个方面来讲，晶体管非常脆弱，即使过载非常短的时间(毫秒甚至微秒级)，器件也会立即烧毁损坏。
所以，在我们设计晶体管应用电路时，必须考虑到晶体管的二次击穿耐量的限制，并且要留有足够的工程余量，以保证晶体管及电子系统长期稳定可靠地工作。
从以上的阐述可以看出，晶体管的二次击穿现象，严重限制了器件的应用范围，及电子系统的工作可靠性。另外，一般来讲，晶体管发生二次击穿以后，集电极和发射极之间会发生短路。如果电子系统保护电路不够完善，则容易引起电源系统或负载发生过流、过压、过热，连带电子系统发生大面积故障和损坏，甚至带来火灾隐患。
很多文献认为，产生二次击穿的原因，主要是因为芯片结面不均匀、晶格缺陷等原因引起的，事实上，即使结构完美的晶体管芯片，也会发生二次击穿现象，二次击穿属于晶体管的固有特性。
发生二次击穿的根本原因，是由于晶体管基极-发射极电压V BE的负温度系数，以及较大的基极-发射极电压V BE至集电极电流I C的跨导(gm)引起的的电热不稳定性引起的。
承载一定集电极电流I C和集电极-发射极电压V CE的晶体管，由于某些原因，如芯片不同部分散热条件的差异(芯片四周要比中心的散热好一些)、芯片PN结掺杂的梯度、芯片不同部分与键合盘距离的不同，等等，芯片各个部分的温度会略有不同，即有一定的梯度。由于晶体管基极-发射极B-E PN结电压的负温度系数，芯片温度高的部分基极-发射极B-E PN结的势垒电势会比较低；从而这部分基极-发射极B-E PN结的电流，即发射极电流I E会增大，集电极电流I C＝α·I E(其中α为晶体管的共基极电流放大系数)和晶体管功耗(或集电极功耗)P C＝I CV CE也相应增大。局部集电极功耗的增大引起这部分芯片局部温度升高，温度的升高又引起基极-发射极B-E PN结的势垒电势进一步降低，电流及功耗又进一步增大…由此可以看出，这是一个正反馈过程。
如果正反馈过程的每个循环参数变化幅度都比前一个循环要小，那这个正反馈过程是稳定的，但是会造成芯片局部过热；而且在工作条件变化后，很容易过渡到不稳定区。如果正反馈过程的每个循环都比前一个循环更加强烈，那这个正反馈过程是不稳定的；在很短的时间内(一般是几微秒到几百微秒，与芯片的热力时间常数有关)，芯片这部分的局部温度、电流密度、以及功耗密度会大大增加。
如果没有必要的保护措施立即切断或迅速减小晶体管电流，由于局部温度迅速升高，芯片这部分的硅材料、金属接触、及金属导线会发生局部过热、烧熔、塌陷、和穿透，从而发生集电极-发射极局部短路，集电极-发射极电压V CE迅速降低，集电极电流I C同时迅速 增大；晶体管结构损毁，器件损坏。这时，由于局部热点的半导体及金属材料已经发生热融化，并烧结在一起，集电极与发射极极易发生短路(一般短路电阻小于1Ω)，其电流仅仅受限于外围电路。
如果外围电路直流动态电阻比较低，又没有足够的过流保护措施，整个电子系统的耗电会急剧上升，从而发生电子系统二次烧毁的可能性也大大增加。
所以，如何加强晶体管的二次击穿耐量，扩展器件的安全工作区范围，提高器件以及电子系统的可靠性，是我们本发明需要解决的问题。
一般晶体管半导体芯片结构的俯视图及剖面图如图3和图4所示。其中图3中的晶体管发射极为矩形，图4中的晶体管发射极为叉指形。
另外，在集电极电流I C较大时，基极电流I B＝I C/β也比较大，由于基极电流横向流经基极横向分布电阻会产生I·R电势差，发射极边缘部分的基极-发射极电压V BE会比发射极中心部分的高。因为发射极电流密度与V BE成指数关系(J E∝e^(V BE/φ T))，发射极电流就会发生集边效应，即发射极边缘部分的电流密度会远远大于发射极中心部分的电流密度，如图5所示。电流密度大的部分耗散功率密度及温度也都高，由于发射极电流的正温度系数(发射极电流与温度呈指数关系)，电流密度在比较高的发射极边缘会进一步增大。因此，在集电极-发射极电压V CE较高时，发射极电流的集边效应就更加严重。
发明内容
本发明要解决的技术问题是针对以上不足，提供高性能、宽安全工作区、高可靠性晶体管器件，提高功率晶体管的二次击穿耐量，拓宽其安全工作区范围，加强器件及电子产品的可靠性，延长了晶体管及整机的工作寿命，也从而扩展功率晶体管的应用领域。
为解决以上技术问题，本发明采用以下技术方案：
高性能、宽安全工作区、高可靠性晶体管，包括若干个相互独立的子晶体管，子晶体管是由原大晶体管整个分割间隔而成，在每个子晶体管实现晶体管整体总电流的分割，使得晶体管整体各部分的温度均一，晶体管局部电流过度增长被有效抑制，分割后多个子晶体管排列在一块单晶硅片上。
进一步的，每个所述子晶体管实现晶体管整体总电流的分割的方法如下：
将晶体管基极区进行分块，晶体管基极区分块的同时晶体管发射区也进行分块，基极和发射极分块后的子晶体管之间并联在一起，在子晶体管的基极皆串联限流电阻来对基极区小块间进行分隔，通过在子晶体管的基极串联限流电阻实现了晶体管整体总电流的分割，达到晶体管中所有子晶体管的温度均一的目的。
进一步的，所有所述子晶体管的温度达到均一采用方法如下：
若子晶体管在单晶硅片均匀分布，子晶体管的基极串联限流电阻的阻值不相同，设置单晶硅片上中间子晶体管基极串联限流电阻的阻值高、四周子晶体管基极串联限流电阻的阻值低，使得单晶硅片上中间子晶体管的电流低、四周子晶体管的电流高，这样就可以使得晶体管中所有子晶体管的温度均一。
进一步的，所有所述子晶体管的温度达到均一采用方法如下：
若子晶体管在单晶硅片的分布中间稀疏、四周密集，使得子晶体管在单晶硅片的散热速度一致，子晶体管的基极串联限流电阻的阻值相同，所有子晶体管的电流均流，这样就可以使得晶体管中所有子晶体管的温度均一。
进一步的，每个所述子晶体管基极串联一限流电阻，限流电阻的下端接子晶体管的基极，所有基极限流电阻的上端连接在一起作为晶体管整体的基极；将在同一块单晶硅片上的子晶体管的发射极连接在一起作为晶体管整体的发射极；将在同一块单晶硅片上的子晶体管的集电极连接在一起作为晶体管整体的集电极。
进一步的，每个子晶体管实现晶体管整体总电流的分割的方法如下：
将晶体管发射极区进行分块，晶体管发射极区分块的同时晶体管基极区可不进行分块，分块后的发射极区可共享一个基极区，发射极分块后的子晶体管之间并联在一起，在子晶体管的发射极皆串联限流电阻来对发射极区小块间进行分隔，通过在子晶体管的发射极串联限流电阻实现了晶体管整体总电流的分割，达到晶体管中所有子晶体管的温度均一的目的。
进一步的，所有所述子晶体管的温度达到均一采用方法如下：
若子晶体管在单晶硅片均匀分布，子晶体管的发射极串联限流电阻的阻值不相同，设置单晶硅片上中间子晶体管发射极串联限流电阻的阻值高、四周子晶体管发射极串联限流电阻的阻值低，使得单晶硅片上中间子晶体管的电流低、四周子晶体管的电流高，这样就可以使得晶体管中所有子晶体管的温度均一。
进一步的，所有所述子晶体管的温度达到均一采用方法如下：
若子晶体管在单晶硅片的分布中间稀疏、四周密集，使得子晶体管在单晶硅片的散热速度一致，子晶体管的发射极串联限流电阻的阻值相同，所有子晶体管的电流均流，这样就可以使得晶体管中所有子晶体管的温度均一。
进一步的，将在同一块单晶硅片上的子晶体管的基极连接在一起作为晶体管整体的基极；每个子晶体管发射极串联一限流电阻，限流电阻的上端接子晶体管的发射极，限流电阻的下端连接在一起作为晶体管整体的发射极；将在同一块单晶硅片上的子晶体管的集电极连接在一起作为晶体管整体的集电极。
进一步的，每个所述子晶体管实现晶体管整体总电流的分割的方法如下：
将晶体管基极区和发射极区进行分块，基极和发射极分块后的子晶体管之间并联在一起，通过在子晶体管的发射极发射极和基极串联限流电阻实现了晶体管整体总电流的分割，达到晶体管中所有子晶体管的温度均一的目的。
进一步的，所有所述子晶体管的温度达到均一采用方法如下：
若子晶体管在单晶硅片均匀分布，子晶体管的基极和/或发射极串联限流电阻的阻值不相同，设置单晶硅片上中间子晶体管基极和/或发射极串联限流电阻的阻值高、四周子晶体管基极和/或发射极串联限流电阻的阻值低，使得单晶硅片上中间子晶体管的电流低、四周子晶体管的电流高，这样就可以使得晶体管中所有子晶体管的温度均一。
进一步的，所有所述子晶体管的温度达到均一采用方法如下：
若子晶体管在单晶硅片的分布中间稀疏、四周密集，使得子晶体管在单晶硅片的散热 速度一致，子晶体管的基极串联限流电阻的阻值相同，发射极串联限流电阻的阻值也相同，所有子晶体管的电流均流，这样就可以使得晶体管中所有子晶体管的温度均一。
进一步的，每个子晶体管基极串联一限流电阻，将在同一块单晶硅片上的子晶体管的基极连接在一起作为晶体管整体的基极；每个子晶体管发射极串联一限流电阻，将在同一块单晶硅片上的子晶体管的发射极连接在一起作为晶体管整体的发射极；将在同一块单晶硅片上的子晶体管的集电极连接在一起作为晶体管整体的集电极。
进一步的，为了缓解晶体管发射极电流的集边效应问题，使所有所述子晶体管的温度达到均一，采用方法如下：
在子晶体管发射极区通过开孔或开槽的办法，改变发射区的分布扩散电阻，以及发射极电流的分布，从而改善发射极电流的集边效应，使子晶体管的电流在发射极的各个区域分布均匀。
本发明采用以上技术方案，与现有技术相比，具有如下技术效果：
1、本发明所述的晶体管显著增大了晶体管的有效芯片面积，改善了晶体管大电流时的电流放大倍数、线性度、和频率相应；
2、本发明所述的晶体管的发射极及集电极电流在整个芯片上均匀分布，消除芯片局部热点，降低芯片最热点的结温，即使晶体管工作在图2中C点以下的集电极-发射极电压V CE，晶体管工作寿命也得到了延长，晶体管及电子设备的工作可靠性也显著提高；
3、在同样半导体芯片面积的条件下，根据本发明设计的晶体管要比现在业界晶体管的二次击穿耐量大几倍到几十倍，晶体管的安全工作区大大扩展；
4、根据本专利技术优化设计的晶体管，二次击穿限制曲线可以在最大允许功耗曲线以外，从而缓解甚至完全消除晶体管二次击穿对晶体管安全工作区的限制；
5、现代硅材料大功率晶体管，线性集电极-发射极有效工作电压V CE受二次击穿问题的限制一般被限制在100V之内，否则晶体管将工作于受二次击穿严重受限的工作区，器件及电子系统的可靠性大打折扣。而利用本发明专利技术设计生产的大功率晶体管，线性工作电压可以扩展到300V以上，显著拓宽了硅材料大功率晶体管的应用范围；
6、本发明设计的晶体管，整个芯片的有效发射极面积、工作可靠性、和结温一致性，显著优于传统设计，针对一些对成本比较敏感的应用，我们可以用较小的芯片面积，达到与一般晶体管相当或更好的性能，从而降低了器件成本，提高了产品的市场竞争力；
7、本发明适用于所有元素半导体材料和化合物半导体材料，如锗、硅、砷化镓、碳化硅等，制造的晶体管；适用于同质结(homojunction)晶体管和异质结(heterojunction)结构的晶体管。
8、本发明也适用于改善其他功率器件，如MOS管、IGBT、可控硅等，工作于线性区的电流均匀性，消除芯片局部热点，延长功率器件工作寿命，提高功率器件(电子设备)可靠性。
下面结合附图和实施例对本发明进行详细说明。
附图说明
图1为本发明背景技术中NPN晶体三极管的结构示意图；
图2为本发明背景技术中晶体三极管直流安全工作区(DC SOA)图；
图3为本发明背景技术中晶体三极管矩形基极和发射极结构的顶视图及剖面图；
图4为本发明背景技术中晶体三极管矩形基极和叉指发射极结构的顶视图及剖面图；
图5为本发明背景技术中晶体三极管的剖面结构示意图；
图6为本发明实施例1-6中子晶体管在单晶硅片上方形小块的矩阵排列图；
图7为本发明实施例1-6中子晶体管在单晶硅片上圆形小块的蜂窝式排列图；
图8为本发明实施例1-2中晶体管基极区分块的示意图；
图9为本发明实施例1-2中晶体管基极区分块，并且加基极隔离电阻的等效电路图；
图10为本发明实施例3-4中晶体管发射极区分块的示意图；
图11为本发明实施例3-4中晶体管发射极区分块，并且加发射极隔离电阻的等效电路图；
图12为本发明实施例5-6中晶体管基极区分块，并且加基极和发射极隔离电阻的示意图；
图13为本发明实施例1-6中晶体管温度分布图；
图14为本发明实施例1、3、5中子晶体管均匀分布和晶体管温度的分布图；
图15为本发明实施例2、4、6中子晶体管中间稀疏、四周密集分布和晶体管温度的分布图；
图16为本发明实施例7中晶体管基极区分块，或者发射极区分块，并且没有加隔离电阻的等效电路图；
图17为本发明实施实例7中，在子晶体管发射极区开槽，改善电流在子晶体管发射极的集边效应。
具体实施方式
实施例1，高性能、宽安全工作区、高可靠性晶体管，包括若干个相互独立的子晶体管，子晶体管是由原大晶体管整体分割间隔而成，原大晶体管被分割为若干个小的子晶体管，分割采用电方面的分隔，即这些分割成的小子晶体管在电方面是分隔的，没有相互连接导电，但在物理形态上还是一个整体。分割成的子晶体管的数量可根据性能需要和生产技术设置，几十到几千都可；在每个子晶体管实现晶体管整体总电流的分割，使得晶体管整体各部分的温度均一，晶体管局部电流过度增长被有效抑制。
如图3所示，n-标注的地方是晶体管的集电极，p标注的地方是晶体管的基极，n+标注的地方是晶体管的发射极，基极是在集电极里的岛，发射极又是在基极里的岛，并且不能接触最外层的集电极，其四周都是基极。且如图3和图4所示，一般的晶体管只有一个基极区域，基极区域又有一个较大的发射极区域。
如图8和图9所示，每个子晶体管实现晶体管整体总电流的分割的方法如下：
将晶体管的基极区进行分块，基极区分块后会有多个基极岛，这样发射极区也就必须分开，每个基极岛里有一个发射极岛，所以晶体管基极区分块的同时晶体管整体发射区也进行分块，基极和发射极分块后的子晶体管之间并联在一起，在子晶体管的基极皆串联限流电阻来对基极区小块间进行分隔，通过在子晶体管的基极串联限流电阻实现了晶体管整体总电流的分割，达到晶体管中所有子晶体管的温度均一的目的。
所述限流电阻可采用多晶硅电阻、薄膜电阻、结型场效应管JFET、绝缘栅场效应 (IGFET/MOSFET)等具有阻性的电子元器件代替。
如图6和图7所示，多个所述子晶体管排列在一块单晶硅片上，子晶体管在单晶硅片可以为矩阵排列方式，也可采用蜂窝状的排列方式，以及其他排列方式，在单晶硅片上的每个子晶体管可采用方形、圆形等形状，也可以为三角形、长方形、五边形、六边形、八边形、椭圆形、镂空图案、以及不规则形状等。
所述子晶体管在单晶硅片的排列次序可以采用规则的排列方式，也可采用不规则排列方式。
每个子晶体管基极串联一限流电阻，限流电阻的下端接子晶体管的基极，所有基极限流电阻的上端连接在一起作为晶体管整体的基极；将在同一块单晶硅片上的子晶体管的发射极连接在一起作为晶体管整体的发射极；将在同一块单晶硅片上的子晶体管的集电极连接在一起作为晶体管整体的集电极。
如图13所示，若子晶体管在单晶硅片均匀分布，子晶体管的基极串联限流电阻的阻值相同，所有子晶体管的电流均流，则单晶硅片上中间子晶体管温度高、四周子晶体管温度低，因单晶硅片上子晶体管中间散热慢、四周子晶体管散热快，这样晶体管中所有子晶体管的温度不能达到均一。
所有所述子晶体管的温度达到均一采用方法如下：
如图14所示，若子晶体管在单晶硅片均匀分布，子晶体管的基极串联限流电阻的阻值不相同，设置单晶硅片上中间子晶体管基极串联限流电阻的阻值高、四周子晶体管基极串联限流电阻的阻值低，使得单晶硅片上中间子晶体管的电流低、四周子晶体管的电流高，这样就可以使得晶体管中所有子晶体管的温度均一。
本发明制备的晶体管适用于各种材料制造的晶体管，本发明也适用于改善其他功率器件，如MOS管、IGBT、可控硅等温度均匀性，消除芯片局部热点，延长功率器件工作寿命，提高功率器件件及电子设备的可靠性。
实施例2，高性能、宽安全工作区、高可靠性晶体管，包括若干个相互独立的子晶体管，子晶体管是由原大晶体管整个分割间隔而成，原大晶体管被分割为若干个小的子晶体管，分割采用电方面的分隔，即这些分割成的小子晶体管在电方面是分隔的，没有相互连接导电，但在物理形态上还是一个整体。分割成的子晶体管的数量可根据性能需要和生产技术设置，几十到几千都可；在每个子晶体管实现晶体管整体总电流的分割，使得晶体管整体各部分的温度均一，晶体管局部电流过度增长被有效抑制。
如图3所示，n-标注的地方是晶体管的集电极，p标注的地方是晶体管的基极，n+标注的地方是晶体管的发射极，基极是在集电极里的岛，发射极又是在基极里的岛，并且不能接触最外层的集电极，其四周都是基极。如图3和图4所示，一般的晶体管只有一个基极区域，基极区域又有一个较大的发射极区域。
如图8和图9所示，每个子晶体管实现晶体管整体总电流的分割的方法如下：
将晶体管的基极区进行分块，基极区分块后会有多个基极岛，这样发射极区也就必须分开，每个基极岛里有一个发射极岛，所以晶体管基极区分块的同时晶体管整体发射区也进行分块，基极和发射极分块后的子晶体管之间并联在一起，在子晶体管的基极皆串联限流电阻来对基极区小块间进行分隔，通过在子晶体管的基极串联限流电阻实现了晶体管整 体总电流的分割，达到晶体管中所有子晶体管的温度均一的目的。
所述限流电阻可采用多晶硅电阻、薄膜电阻、结型场效应管JFET、绝缘栅场效应(IGFET/MOSFET)等具有阻性的电子元器件代替。
如图6和图7所示，多个所述子晶体管排列在一块单晶硅片上，子晶体管在单晶硅片可以为矩阵排列方式，也可采用蜂窝状的排列方式，以及其他排列方式，在单晶硅片上的每个子晶体管可采用方形、圆形等形状，也可以为三角形、长方形、五边形、六边形、八边形、椭圆形、镂空图案、以及不规则形状等。
所述子晶体管在单晶硅片的排列次序可以采用规则的排列方式，也可采用不规则排列方式。
每个子晶体管基极串联一限流电阻，限流电阻的下端接子晶体管的基极，所有基极限流电阻的上端连接在一起作为晶体管整体的基极；将在同一块单晶硅片上的子晶体管的发射极连接在一起作为晶体管整体的发射极；将在同一块单晶硅片上的子晶体管的集电极连接在一起作为晶体管整体的集电极。
如图13所示，若子晶体管在单晶硅片均匀分布，子晶体管的基极串联限流电阻的阻值相同，所有子晶体管的电流均流，则单晶硅片上中间子晶体管温度高、四周子晶体管温度低，因单晶硅片上子晶体管中间散热慢、四周子晶体管散热快，这样晶体管中所有子晶体管的温度不能达到均一。
所有所述子晶体管的温度达到均一采用方法如下：
如图15所示，若子晶体管在单晶硅片的分布中间稀疏、四周密集，使得子晶体管在单晶硅片的散热速度一致，子晶体管的基极串联限流电阻的阻值相同，所有子晶体管的电流均流，这样就可以使得晶体管中所有子晶体管的温度均一。
本发明制备的晶体管适用于各种材料制造的晶体管，本发明也适用于改善其他功率器件，如MOS管、IGBT、可控硅等温度均匀性，消除芯片局部热点，延长功率器件工作寿命，提高功率器件件及电子设备的可靠性。
实施例3，高性能、宽安全工作区、高可靠性晶体管，包括若干个相互独立的子晶体管，子晶体管是由原大晶体管整个分割间隔而成，原大晶体管被分割为若干个小的子晶体管，分割采用电方面的分隔，即这些分割成的小子晶体管在电方面是分隔的，没有相互连接导电，但在物理形态上还是一个整体。分割成的子晶体管的数量可根据性能需要和生产技术设置，几十到几千都可；在每个子晶体管实现晶体管整体总电流的分割，使得晶体管整体各部分的温度均一，晶体管局部电流过度增长被有效抑制。
如图3所示，n-标注的地方是晶体管的集电极，p标注的地方是晶体管的基极，n+标注的地方是晶体管的发射极，基极是在集电极里的岛，发射极又是在基极里的岛，并且不能接触最外层的集电极，其四周都是基极。如图3和图4所示，一般的晶体管只有一个基极区域，基极区域又有一个较大的发射极区域。
如图10和图11所示，每个子晶体管实现晶体管整体总电流的分割的方法如下：
将晶体管发射极区进行分块，晶体管发射极区分块的同时晶体管基极区可不进行分块，分块后的发射极区可共享一个基极区，发射极分块后的子晶体管之间并联在一起，在子晶体管的发射极皆串联限流电阻来对发射极区小块间进行分隔，通过在子晶体管的发射 极串联限流电阻实现了晶体管整体总电流的分割，达到晶体管中所有子晶体管的温度均一的目的。
所述限流电阻可采用多晶硅电阻、薄膜电阻、结型场效应管JFET、绝缘栅场效应(IGFET/MOSFET)等具有阻性的电子元器件代替。
如图6和图7所示，多个所述子晶体管排列在一块单晶硅片上，子晶体管在单晶硅片可以为矩阵排列方式，也可采用蜂窝状的排列方式，以及其他排列方式，在单晶硅片上的每个子晶体管可采用方形、圆形等形状，也可以为三角形、长方形、五边形、六边形、八边形、椭圆形、镂空图案、以及不规则形状等。
所述子晶体管在单晶硅片的排列次序可以采用规则的排列方式，也可采用不规则排列方式。
将在同一块单晶硅片上的子晶体管的基极连接在一起作为晶体管整体的基极；每个子晶体管发射极串联一限流电阻，限流电阻的上端接子晶体管的发射极，限流电阻的下端连接在一起作为晶体管整体的发射极；将在同一块单晶硅片上的子晶体管的集电极连接在一起作为晶体管整体的集电极。
如图13所示，若子晶体管在单晶硅片均匀分布，子晶体管的发射极串联限流电阻的阻值相同，所有子晶体管的电流均流，则单晶硅片上中间子晶体管温度高、四周子晶体管温度低，因单晶硅片上子晶体管中间散热慢、四周子晶体管散热快，这样晶体管中所有子晶体管的温度不能达到均一。
所有所述子晶体管的温度达到均一采用方法如下：
如图14所示，若子晶体管在单晶硅片均匀分布，子晶体管的发射极串联限流电阻的阻值不相同，设置单晶硅片上中间子晶体管发射极串联限流电阻的阻值高、四周子晶体管基极串联限流电阻的阻值低，使得单晶硅片上中间子晶体管的电流低、四周子晶体管的电流高，这样就可以使得晶体管中所有子晶体管的温度均一。
本发明制备的晶体管适用于各种材料制造的晶体管，本发明也适用于改善其他功率器件，如MOS管、IGBT、可控硅等温度均匀性，消除芯片局部热点，延长功率器件工作寿命，提高功率器件件及电子设备的可靠性。
实施例4，高性能、宽安全工作区、高可靠性晶体管，包括若干个相互独立的子晶体管，子晶体管是由原大晶体管整个分割间隔而成，原大晶体管被分割为若干个小的子晶体管，分割采用电方面的分隔，即这些分割成的小子晶体管在电方面是分隔的，没有相互连接导电，但在物理形态上还是一个整体。分割成的子晶体管的数量可根据性能需要和生产技术设置，几十到几千都可；在每个子晶体管实现晶体管整体总电流的分割，使得晶体管整体各部分的温度均一，晶体管局部电流过度增长被有效抑制。
如图3所示，n-标注的地方是晶体管的集电极，p标注的地方是晶体管的基极，n+标注的地方是晶体管的发射极，基极是在集电极里的岛，发射极又是在基极里的岛，并且不能接触最外层的集电极，其四周都是基极。如图3和图4所示，一般的晶体管只有一个基极区域，基极区域又有一个较大的发射极区域。
如图10和图11所示，每个子晶体管实现晶体管整体总电流的分割的方法如下：
将晶体管发射极区进行分块，晶体管发射极区分块的同时晶体管基极区可不进行分 块，分块后的发射极区可共享一个基极区，发射极分块后的子晶体管之间并联在一起，在子晶体管的发射极皆串联限流电阻来对发射极区小块间进行分隔，通过在子晶体管的发射极串联限流电阻实现了晶体管整体总电流的分割，达到晶体管中所有子晶体管的温度均一的目的。
所述限流电阻可采用多晶硅电阻、薄膜电阻、结型场效应管JFET、绝缘栅场效应(IGFET/MOSFET)等具有阻性的电子元器件代替。
如图6和图7所示，多个所述子晶体管排列在一块单晶硅片上，子晶体管在单晶硅片可以为矩阵排列方式，也可采用蜂窝状的排列方式，以及其他排列方式，在单晶硅片上的每个子晶体管可采用方形、圆形等形状，也可以为三角形、长方形、五边形、六边形、八边形、椭圆形、镂空图案、以及不规则形状等。
所述子晶体管在单晶硅片的排列次序可以采用规则的排列方式，也可采用不规则排列方式。
将在同一块单晶硅片上的子晶体管的基极连接在一起作为晶体管整体的基极；每个子晶体管发射极串联一限流电阻，限流电阻的上端接子晶体管的发射极，限流电阻的下端连接在一起作为晶体管整体的发射极；将在同一块单晶硅片上的子晶体管的集电极连接在一起作为晶体管整体的集电极。
如图13所示，若子晶体管在单晶硅片均匀分布，子晶体管的发射极串联限流电阻的阻值相同，所有子晶体管的电流均流，则单晶硅片上中间子晶体管温度高、四周子晶体管温度低，因单晶硅片上子晶体管中间散热慢、四周子晶体管散热快，这样晶体管中所有子晶体管的温度不能达到均一。
所有所述子晶体管的温度达到均一采用方法如下：
如图15所示，若子晶体管在单晶硅片的分布中间稀疏、四周密集，使得子晶体管在单晶硅片的散热速度一致，子晶体管的发射极串联限流电阻的阻值相同，所有子晶体管的电流均流，这样就可以使得晶体管中所有子晶体管的温度均一。
本发明制备的晶体管适用于各种材料制造的晶体管，本发明也适用于改善其他功率器件，如MOS管、IGBT、可控硅等温度均匀性，消除芯片局部热点，延长功率器件工作寿命，提高功率器件件及电子设备的可靠性。
实施例5，高性能、宽安全工作区、高可靠性晶体管，包括若干个相互独立的子晶体管，子晶体管是由原大晶体管整个分割间隔而成，原大晶体管被分割为若干个小的子晶体管，分割采用电方面的分隔，即这些分割成的小子晶体管在电方面是分隔的，没有相互连接导电，但在物理形态上还是一个整体。分割成的子晶体管的数量可根据性能需要和生产技术设置，几十到几千都可；在每个子晶体管实现晶体管整体总电流的分割，使得晶体管整体各部分的温度均一，晶体管局部电流过度增长被有效抑制。
如图3所示，n-标注的地方是晶体管的集电极，p标注的地方是晶体管的基极，n+标注的地方是晶体管的发射极，基极是在集电极里的岛，发射极又是在基极里的岛，并且不能接触最外层的集电极，其四周都是基极。如图3和图4所示，一般的晶体管只有一个基极区域，基极区域又有一个较大的发射极区域。
如图8和图12所示，每个子晶体管实现晶体管整体总电流的分割的方法如下：
将晶体管的基极区进行分块，基极区分块后会有多个基极岛，这样发射极区也就必须分开，每个基极岛里有一个发射极岛，所以晶体管基极区分块的同时晶体管整体发射区也进行分块，基极和发射极分块后的子晶体管之间并联在一起。通过在子晶体管的发射极和基极皆串联限流电阻实现晶体管整体总电流的分割，达到晶体管中所有子晶体管的温度均一的目的。
所述限流电阻可采用多晶硅电阻、薄膜电阻、结型场效应管JFET、绝缘栅场效应(IGFET/MOSFET)等具有阻性的电子元器件代替。
如图6和图7所示，多个所述子晶体管排列在一块单晶硅片上，子晶体管在单晶硅片可以为矩阵排列方式，也可采用蜂窝状的排列方式，以及其他排列方式，在单晶硅片上的每个子晶体管可采用方形、圆形等形状，也可以为三角形、长方形、五边形、六边形、八边形、椭圆形、镂空图案、以及不规则形状等。
所述子晶体管在单晶硅片的排列次序可以采用规则的排列方式，也可采用不规则排列方式。
每个子晶体管基极串联一限流电阻，将在同一块单晶硅片上的子晶体管的基极连接在一起作为晶体管整体的基极；每个子晶体管发射极串联一限流电阻，将在同一块单晶硅片上的子晶体管的发射极连接在一起作为晶体管整体的发射极；将在同一块单晶硅片上的子晶体管的集电极连接在一起作为晶体管整体的集电极。
如图13所示，若子晶体管在单晶硅片均匀分布，子晶体管的基极串联限流电阻的阻值相同，发射极串联限流电阻的阻值也相同，所有子晶体管的电流均流，则单晶硅片上中间子晶体管温度高、四周子晶体管温度低，因单晶硅片上子晶体管中间散热慢、四周子晶体管散热快，这样晶体管中所有子晶体管的温度不能达到均一。
所有所述子晶体管的温度达到均一采用方法如下：
如图14所示，若子晶体管在单晶硅片均匀分布，子晶体管的基极和/或发射极串联限流电阻的阻值不相同，设置单晶硅片上中间子晶体管基极和/或发射极串联限流电阻的阻值高、四周子晶体管基极和/或发射极串联限流电阻的阻值低，即设置单晶硅片上中间子晶体管发射极和基极串联限流电阻的阻值皆高、四周子晶体管发射极和基极串联限流电阻的阻值皆低；或设置单晶硅片上子晶体管发射极串联限流电阻的阻值相同，单晶硅片上中间子晶体管基极串联限流电阻的阻值高、四周子晶体管基极串联限流电阻的阻值低；也可设置单晶硅片上子晶体管基极串联限流电阻的阻值相同，单晶硅片上中间子晶体管发射极串联限流电阻的阻值高、四周子晶体管发射极串联限流电阻的阻值低，使得单晶硅片上中间子晶体管的电流低、四周子晶体管的电流高，这样就可以使得晶体管中所有子晶体管的温度均一。
本发明制备的晶体管适用于各种材料制造的晶体管，本发明也适用于改善其他功率器件，如MOS管、IGBT、可控硅等温度均匀性，消除芯片局部热点，延长功率器件工作寿命，提高功率器件件及电子设备的可靠性。
实施例6，高性能、宽安全工作区、高可靠性晶体管，包括若干个相互独立的子晶体管，子晶体管是由原大晶体管整个分割间隔而成，原大晶体管被分割为若干个小的子晶体管，分割采用电方面的分隔，即这些分割成的小子晶体管在电方面是分隔的，没有相互连 接导电，但在物理形态上还是一个整体。分割成的子晶体管的数量可根据性能需要和生产技术设置，几十到几千都可；在每个子晶体管实现晶体管整体总电流的分割，使得晶体管整体各部分的温度均一，晶体管局部电流过度增长被有效抑制。
如图3所示，n-标注的地方是晶体管的集电极，p标注的地方是晶体管的基极，n+标注的地方是晶体管的发射极，基极是在集电极里的岛，发射极又是在基极里的岛，并且不能接触最外层的集电极，其四周都是基极。如图3和图4所示，一般的晶体管只有一个基极区域，基极区域又有一个较大的发射极区域。
如图8和图12所示，每个子晶体管实现晶体管整体总电流的分割的方法如下：
将晶体管的基极区进行分块，基极区分块后会有多个基极岛，这样发射极区也就必须分开，每个基极岛里有一个发射极岛，所以晶体管基极区分块的同时晶体管整体发射区也进行分块，基极和发射极分块后的子晶体管之间并联在一起。通过在子晶体管的发射极和基极皆串联限流电阻实现晶体管整体总电流的分割，达到晶体管中所有子晶体管的温度均一的目的。
所述限流电阻可采用多晶硅电阻、薄膜电阻、结型场效应管JFET、绝缘栅场效应(IGFET/MOSFET)等具有阻性的电子元器件代替。
如图6和图7所示，多个所述子晶体管排列在一块单晶硅片上，子晶体管在单晶硅片可以为矩阵排列方式，也可采用蜂窝状的排列方式，以及其他排列方式，在单晶硅片上的每个子晶体管可采用方形、圆形等形状，也可以为三角形、长方形、五边形、六边形、八边形、椭圆形、镂空图案、以及不规则形状等。
所述子晶体管在单晶硅片的排列次序可以采用规则的排列方式，也可采用不规则排列方式。
每个子晶体管基极串联一限流电阻，将在同一块单晶硅片上的子晶体管的基极连接在一起作为晶体管整体的基极；每个子晶体管发射极串联一限流电阻，将在同一块单晶硅片上的子晶体管的发射极连接在一起作为晶体管整体的发射极；将在同一块单晶硅片上的子晶体管的集电极连接在一起作为晶体管整体的集电极。
如图13所示，若子晶体管在单晶硅片均匀分布，子晶体管的基极串联限流电阻的阻值相同，发射极串联限流电阻的阻值也相同，所有子晶体管的电流均流，则单晶硅片上中间子晶体管温度高、四周子晶体管温度低，因单晶硅片上子晶体管中间散热慢、四周子晶体管散热快，这样晶体管中所有子晶体管的温度不能达到均一。
所有所述子晶体管的温度达到均一采用方法如下：
如图15所示，若子晶体管在单晶硅片的分布中间稀疏、四周密集，使得子晶体管在单晶硅片的散热速度一致，子晶体管的基极串联限流电阻的阻值相同，发射极串联限流电阻的阻值也相同，所有子晶体管的电流均流，这样就可以使得晶体管中所有子晶体管的温度均一。
本发明制备的晶体管适用于各种材料制造的晶体管，本发明也适用于改善其他功率器件，如MOS管、IGBT、可控硅等温度均匀性，消除芯片局部热点，延长功率器件工作寿命，提高功率器件件及电子设备的可靠性。
实施例7，采用实施例1-6所述的技术方案实现子晶体管之间的电流均流之后，每个 子晶体管的集电极电流I C_unit基本在I C_total/n左右，其集电极总电流I C_total是整个晶体管芯片的集电极电流，n为子晶体管的个数，在集电极电流在整个晶体管芯片上得到比较均匀的分布，然而，在集电极电流I C较大时，基极电流也比较大，由于基极电流横向流经基极横向分布电阻会产生电势差，发射极边缘部分的基极-发射极电压VBE会比发射极中心部分的高。因为发射极电流密度与VBE成指数关系，发射极电流就会发生集边效应，即发射极边缘部分的电流密度会远远大于发射极中心部分的电流密度，如图5所示。电流密度大的部分耗散功率密度及温度也都高，由于发射极电流的正温度系数(发射极电流与温度呈指数关系)，电流密度在比较高的发射极边缘会进一步增大。因此，在集电极-发射极电压V CE较高时，发射极电流的集边效应就更加严重。
为了缓解晶体管发射极电流的集边效应问题，本发明采取以下方法：
在发射极区通过开孔或开槽，改变发射区的分布扩散电阻电流的分布，发射极电流的集边效应得以改善，从而发射极电流在子晶体管的发射极的各个区域均匀分布，进一步提高整个晶体管的二次击穿耐量，改善晶体管的性能。
本实施实例解决发射极电流的集边效应的方法同样适用于在子晶体管的基极及发射极都没有串联电阻的条件下实施。
本发明的描述是为了示例和描述起见而给出的，而并不是无遗漏的或者将本发明限于所公开的形式。很多修改和变化对于本领域的普通技术人员而言是显然的。选择和描述实施例是为了更好的说明本发明的原理和实际应用，并且使本领域的普通技术人员能够理解本发明从而设计适于特定用途的带有各种修改的各种实施例。

Claims (14)

  1. 高性能、宽安全工作区、高可靠性晶体管，其特征在于：包括若干个相互独立的子晶体管，子晶体管是由原大晶体管整个分割间隔而成，在每个子晶体管实现晶体管整体总电流的分割，使得晶体管整体各部分的温度均一，晶体管局部电流过度增长被有效抑制，分割后多个子晶体管排列在一块单晶硅片上。
  2. 如权利要求1所述的高性能、宽安全工作区、高可靠性晶体管，其特征在于：每个所述子晶体管实现晶体管整体总电流的分割的方法如下：
    将晶体管基极区进行分块，晶体管基极区分块的同时晶体管发射区也进行分块，基极和发射极分块后的子晶体管之间并联在一起，在子晶体管的基极皆串联限流电阻来对基极区小块间进行分隔，通过在子晶体管的基极串联限流电阻实现了晶体管整体总电流的分割，达到晶体管中所有子晶体管的温度均一的目的。
  3. 如权利要求2所述的高性能、宽安全工作区、高可靠性晶体管，其特征在于：所有所述子晶体管的温度达到均一采用方法如下：
    若子晶体管在单晶硅片均匀分布，子晶体管的基极串联限流电阻的阻值不相同，设置单晶硅片上中间子晶体管基极串联限流电阻的阻值高、四周子晶体管基极串联限流电阻的阻值低，使得单晶硅片上中间子晶体管的电流低、四周子晶体管的电流高，这样就可以使得晶体管中所有子晶体管的温度均一。
  4. 如权利要求2所述的高性能、宽安全工作区、高可靠性晶体管，其特征在于：所有所述子晶体管的温度达到均一采用方法如下：
    若子晶体管在单晶硅片的分布中间稀疏、四周密集，使得子晶体管在单晶硅片的散热速度一致，子晶体管的基极串联限流电阻的阻值相同，所有子晶体管的电流均流，这样就可以使得晶体管中所有子晶体管的温度均一。
  5. 如权利要求2所述的高性能、宽安全工作区、高可靠性晶体管，其特征在于：每个所述子晶体管基极串联一限流电阻，限流电阻的下端接子晶体管的基极，所有基极限流电阻的上端连接在一起作为晶体管整体的基极；将在同一块单晶硅片上的子晶体管的发射极连接在一起作为晶体管整体的发射极；将在同一块单晶硅片上的子晶体管的集电极连接在一起作为晶体管整体的集电极。
  6. 如权利要求1所述的高性能、宽安全工作区、高可靠性晶体管，其特征在于：每个子晶体管实现晶体管整体总电流的分割的方法如下：
    将晶体管发射极区进行分块，晶体管发射极区分块的同时晶体管基极区可不进行分块，分块后的发射极区可共享一个基极区，发射极分块后的子晶体管之间并联在一起，在子晶体管的发射极皆串联限流电阻来对发射极区小块间进行分隔，通过在子晶体管的发射极串联限流电阻实现了晶体管整体总电流的分割，达到晶体管中所有子晶体管的温度均一的目的。
  7. 如权利要求6所述的高性能、宽安全工作区、高可靠性晶体管，其特征在于：所有所述子晶体管的温度达到均一采用方法如下：
    若子晶体管在单晶硅片均匀分布，子晶体管的发射极串联限流电阻的阻值不相同，设置单晶硅片上中间子晶体管发射极串联限流电阻的阻值高、四周子晶体管发射极串联限流电阻的阻值低，使得单晶硅片上中间子晶体管的电流低、四周子晶体管的电流高，这样就可以使得晶体管中所有子晶体管的温度均一。
  8. 如权利要求6所述的高性能、宽安全工作区、高可靠性晶体管，其特征在于：所有所述子晶体管的温度达到均一采用方法如下：
    若子晶体管在单晶硅片的分布中间稀疏、四周密集，使得子晶体管在单晶硅片的散热速度一致，子晶体管的发射极串联限流电阻的阻值相同，所有子晶体管的电流均流，这样就可以使得晶体管中所有子晶体管的温度均一。
  9. 如权利要求6所述的高性能、宽安全工作区、高可靠性晶体管，其特征在于：将在同一块单晶硅片上的子晶体管的基极连接在一起作为晶体管整体的基极；每个子晶体管发射极串联一限流电阻，限流电阻的上端接子晶体管的发射极，限流电阻的下端连接在一起作为晶体管整体的发射极；将在同一块单晶硅片上的子晶体管的集电极连接在一起作为晶体管整体的集电极。
  10. 如权利要求1所述的高性能、宽安全工作区、高可靠性晶体管，其特征在于：每个所述子晶体管实现晶体管整体总电流的分割的方法如下：
    将晶体管基极区和发射极区进行分块，基极和发射极分块后的子晶体管之间并联在一起，通过在子晶体管的发射极发射极和基极串联限流电阻实现了晶体管整体总电流的分割，达到晶体管中所有子晶体管的温度均一的目的。
  11. 如权利要求10所述的高性能、宽安全工作区、高可靠性晶体管，其特征在于：所有所述子晶体管的温度达到均一采用方法如下：
    若子晶体管在单晶硅片均匀分布，子晶体管的基极和/或发射极串联限流电阻的阻值不相同，设置单晶硅片上中间子晶体管基极和/或发射极串联限流电阻的阻值高、四周子晶体管基极和/或发射极串联限流电阻的阻值低，使得单晶硅片上中间子晶体管的电流低、四周子晶体管的电流高，这样就可以使得晶体管中所有子晶体管的温度均一。
  12. 如权利要求10所述的高性能、宽安全工作区、高可靠性晶体管，其特征在于：所有所述子晶体管的温度达到均一采用方法如下：
    若子晶体管在单晶硅片的分布中间稀疏、四周密集，使得子晶体管在单晶硅片的散热速度一致，子晶体管的基极串联限流电阻的阻值相同，发射极串联限流电阻的阻值也相同，所有子晶体管的电流均流，这样就可以使得晶体管中所有子晶体管的温度均一。
  13. 如权利要求10所述的高性能、宽安全工作区、高可靠性晶体管，其特征在于：每个子晶体管基极串联一限流电阻，将在同一块单晶硅片上的子晶体管的基极连接在一起作为晶体管整体的基极；每个子晶体管发射极串联一限流电阻，将在同一块单晶硅片上的子晶体管的发射极连接在一起作为晶体管整体的发射极；将在同一块单晶硅片上的子晶体管的集电极连接在一起作为晶体管整体的集电极。
  14. 如权利要求2-13任意一权利要求所述的高性能、宽安全工作区、高可靠性晶体管，其特征在于：为了缓解晶体管发射极电流的集边效应问题，使所有所述子晶体管的温度达到均一，采用方法如下：
    在子晶体管发射极区通过开孔或开槽的办法，改变发射区的分布扩散电阻，以及发射极电流的分布，从而改善发射极电流的集边效应，使子晶体管的电流在发射极的各个区域分布均匀。
PCT/CN2020/109798 2019-09-04 2020-08-18 高性能、宽安全工作区、高可靠性晶体管 WO2021042979A1 (zh)

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