CN111613667A - 绝缘栅极型半导体装置及其制造方法 - Google Patents

绝缘栅极型半导体装置及其制造方法 Download PDF

Info

Publication number
CN111613667A
CN111613667A CN202010000510.4A CN202010000510A CN111613667A CN 111613667 A CN111613667 A CN 111613667A CN 202010000510 A CN202010000510 A CN 202010000510A CN 111613667 A CN111613667 A CN 111613667A
Authority
CN
China
Prior art keywords
insulating film
gate
region
dummy
inspection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202010000510.4A
Other languages
English (en)
Inventor
石川隆正
野口晴司
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Publication of CN111613667A publication Critical patent/CN111613667A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0804—Emitter regions of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0821—Collector regions of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1004—Base region of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H01L29/7828—Vertical transistors without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising semiconducting material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66416—Static induction transistors [SIT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/7722—Field effect transistors using static field induced regions, e.g. SIT, PBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/8613—Mesa PN junction diodes

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

本发明提供一种绝缘栅极型半导体装置及其制造方法，能够抑制工时的增加、且能够与栅极沟槽的栅极绝缘膜相独立地进行虚设沟槽的栅极绝缘膜不良的筛查。包括以下工序：掘出栅极沟槽(51)和虚设沟槽(42)；隔着栅极绝缘膜(6)在虚设沟槽(42)中埋入虚设电极(72)，并且隔着栅极绝缘膜(6)在栅极沟槽(51)中埋入栅极电极(71)；以将虚设电极(72)上露出、且将栅极电极(71)覆盖的方式选择性地形成检查用绝缘膜(11)；在虚设电极(72)和检查用绝缘膜(11)上沉积检查用导电膜(20)；以及在检查用导电膜(20)与电荷输送区(1)之间施加电压，由此选择性地检查虚设沟槽(51)内的栅极绝缘膜(6)的绝缘特性。

Description

绝缘栅极型半导体装置及其制造方法
技术领域
本发明涉及一种具有沟槽栅极构造的绝缘栅极型半导体装置及其制造方法。
背景技术
在具有沟槽栅极构造的绝缘栅极型双极晶体管(IGBT)中，已知有以下构造：在多个沟槽中的一部分沟槽(虚设沟槽)中埋入虚设电极，并将虚设电极与发射极电极电连接，以使导致开关损耗的栅极-集电极间的电容降低等。
专利文献1公开了如下方法：在栅极沟槽与虚设沟槽在器件结构上分离之前，遍及沟槽整体地进行栅极绝缘膜不良的筛查以确保虚设沟槽的栅极绝缘膜的质量。
然而，在专利文献1的方法中，由于遍及沟槽整体地同时进行栅极绝缘膜的试验，因此在试验时需要施加比较大的电压，从而在不良元件破损时产生大量的微粒。因此，设为与虚设沟槽的栅极绝缘膜的要求耐性相匹配的筛查条件以抑制微粒的产生，然而要在制造流程完成后对栅极沟槽的栅极绝缘膜再次进行试验，栅极绝缘膜的时变击穿(TimeDependent Dielectric Breakdown：TDDB)耐性下降。
另一方面，在制造流程完成后不进行筛查的情况下，无法对制造中途的筛查后的流程损伤进行筛查。
现有技术文献
专利文献
专利文献1：日本专利第6304445号公报
发明内容
发明要解决的问题
鉴于上述问题，本发明的目的在于提供一种能够抑制工时的增加、且能够与栅极沟槽的栅极绝缘膜相独立地进行虚设沟槽的栅极绝缘膜不良的筛查的绝缘栅极型半导体装置及其制造方法。
用于解决问题的方案
本发明的一个方式的主旨是一种绝缘栅极型半导体装置，具备：(a)第一导电型的电荷输送区；(b)电荷输送区上的第二导电型的注入控制区；(c)注入控制区上的第一导电型的主电荷供给区；(d)虚设电极，其隔着栅极绝缘膜埋入于贯通主电荷供给区和注入控制区并到达电荷输送区的虚设沟槽；(e)栅极电极，其隔着栅极绝缘膜埋入于贯通主电荷供给区和注入控制区并到达电荷输送区的栅极沟槽；(f)栅极电极上的第一层间绝缘膜；以及(g)虚设电极上的第二层间绝缘膜，其中，第一层间绝缘膜具有多个绝缘膜的层叠构造，所述第一层间绝缘膜的绝缘膜比第二层间绝缘膜的绝缘膜多1层以上。
本发明的其它方式的主旨是一种绝缘栅极型半导体装置的制造方法，包括以下工序：(a)在第一导电型的电荷输送区上形成第二导电型的注入控制区；(b)在注入控制区上形成第一导电型的主电荷供给区；(c)以贯通主电荷供给区和注入控制区的方式掘出栅极沟槽和虚设沟槽；(d)隔着栅极绝缘膜在虚设沟槽中埋入虚设电极，并且隔着栅极绝缘膜在栅极沟槽中埋入栅极电极；(e)以将虚设电极上露出、且将栅极电极上覆盖的方式选择性地形成检查用绝缘膜；(f)在虚设电极和检查用绝缘膜上沉积检查用导电膜；以及(g)在检查用导电膜与电荷输送区之间施加电压，由此选择性地检查虚设沟槽内的栅极绝缘膜的绝缘特性。
发明的效果
根据本发明，能够提供一种能够抑制工时的增加、且能够与栅极沟槽的栅极绝缘膜相独立地进行虚设沟槽的栅极绝缘膜不良的筛查的绝缘栅极型半导体装置及其制造方法。
附图说明
图1是表示实施方式所涉及的绝缘栅极型半导体装置的一例的俯视图。
图2是从图1的A-A′方向观察而得到的截面图。
图3是从图1的B-B′方向观察而得到的截面图。
图4是表示实施方式所涉及的绝缘栅极型半导体装置的制造方法的一例的工序截面图。
图5是接着图4的表示实施方式所涉及的绝缘栅极型半导体装置的制造方法的一例的工序截面图。
图6是接着图5的表示实施方式所涉及的绝缘栅极型半导体装置的制造方法的一例的工序截面图。
图7是接着图6的表示实施方式所涉及的绝缘栅极型半导体装置的制造方法的一例的工序俯视图。
图8A是接着图7的表示实施方式所涉及的绝缘栅极型半导体装置的制造方法的一例的工序俯视图。
图8B是从图8A的A-A′方向观察而得到的工序截面图。
图9是接着图8A和图8B的表示实施方式所涉及的绝缘栅极型半导体装置的制造方法的一例的工序截面图。
图10是接着图9的表示实施方式所涉及的绝缘栅极型半导体装置的制造方法的一例的工序截面图。
图11是接着图10的表示实施方式所涉及的绝缘栅极型半导体装置的制造方法的一例的工序截面图。
图12是接着图11的表示实施方式所涉及的绝缘栅极型半导体装置的制造方法的一例的工序截面图。
图13是接着图12的表示实施方式所涉及的绝缘栅极型半导体装置的制造方法的一例的工序截面图。
图14是接着图13的表示实施方式所涉及的绝缘栅极型半导体装置的制造方法的一例的工序截面图。
图15是接着图14的表示实施方式所涉及的绝缘栅极型半导体装置的制造方法的一例的工序截面图。
图16是表示比较例所涉及的绝缘栅极型半导体装置的制造方法的工序截面图。
图17是接着图16的表示比较例所涉及的绝缘栅极型半导体装置的制造方法的工序截面图。
附图标记说明
1：半导体基板(电荷输送区)；2：注入控制区；3a、3b、3c、3d：主电荷供给区(发射极区)；3A、3B：电极区预定层；6：栅极绝缘膜；8：场截止层；9：主电荷接收区(集电极区)；10：主电荷接收电极(集电极电极)；11：检查用绝缘膜；12：连接用绝缘膜；13：上层绝缘膜；14：栅极表面布线；14a～14d：连接区；15：主电荷供给电极(发射极电极)；16：蚀刻保护膜；20：检查用导电膜；21：电源；22：台；23：探针；31a～31j、32a～32h：接触孔；41～44：虚设沟槽；51、52：栅极沟槽；71：栅极电极；72：虚设电极；100：半导体基板；101：栅极沟槽；102：虚设沟槽；103：栅极绝缘膜；104：导电膜；111：栅极电极；112：虚设电极；511、512、521、522：条部；513、523：连接部。
具体实施方式
下面，参照附图来说明实施方式。在下面的说明中所参照的附图的记载中，对同一或者类似的部分标注同一或者类似的标记。但是，应注意的是，附图是示意性的，厚度与平面尺寸之间的关系、各层的厚度的比率等与现实情况不同。因而，应参酌下面的说明来判断具体的厚度、尺寸。另外，在附图彼此之间也包括彼此的尺寸关系、比率不同的部分，这是不言而喻的。
在本说明书中，绝缘栅极型半导体装置的“主电荷供给区”是指用于供给构成主电流的载流子的区，在绝缘栅极型双极晶体管(IGBT)中指成为发射极区或者集电极区中的任一方的半导体区。在绝缘栅极型场效应晶体管(MISFET)、绝缘栅极型静电感应晶体管(MISSIT)中指成为源极区或者漏极区中的任一方的半导体区。另外，在MIS控制静电感应晶闸管(SI晶闸管)等绝缘栅极型晶闸管中指成为阳极区或者阴极区中的任一方的半导体区。“主电荷接收区”是指接收构成主电流的多数载流子的区，在MISFET、MISSIT中指成为源极区或者漏极区中的、未成为上述主电荷供给区的任一方的半导体区。在IGBT中指成为发射极区或者集电极区中的、未成为上述主电荷供给区的任一方的区。在MIS控制SI晶闸管等中指成为阳极区或者阴极区中的、未成为上述主电荷供给区的任一方的半导体区。此外，在如IGBT等那样进行双极动作的半导体装置中，有时从“主电荷接收区”供给具有与构成主电流的多数载流子相反的电荷的少数载流子。
像这样，如果“主电荷供给区”是源极区，则“主电荷接收区”指漏极区，“主电流”在主电荷供给区与主电荷接收区之间流通。例如在IGBT的情况下，集电极电流相当于主电流，如果“主电荷供给区”是发射极区，则“主电荷接收区”指集电极区。如果“主电荷供给区”是阳极区，则“主电荷接收区”指阴极区。存在如下情况：如果将偏置关系互换，则在MISFET等的情况下，能够将“主电荷供给区”的功能与“主电荷接收区”的功能互换。而且，将通过欧姆接触等来与主电荷供给区电连接的电极定义为“主电荷供给电极”，将通过欧姆接触等来与主电荷接收区电连接的电极定义为“主电荷接收电极”。此外，也可以在主电荷供给区与主电荷供给电极之间、在主电荷接收区与主电荷接收电极之间包含连接用的插塞(Plug)、硅化物层。
另外，在下面的说明中，例示性地说明第一导电型为n型、第二导电型为p型的情况。但是也可以将导电型选择为相反的关系，将第一导电型设为p型，将第二导电型设为n型。另外，附记于“n”、“p”的“+”、“-”分别是指相比于没有附记“+”和“-”的半导体区、为杂质浓度相对高或相对低的半导体区。但是，即使为标注了相同的“n”和“n”的半导体区，也并不意味着各个半导体区的杂质浓度严格相同。
另外，下面的说明中的上下等方向的定义仅是方便说明的定义，并不用于限定本发明的技术思想。例如，如果将对象旋转90°来观察，则上下变换为左右来读，如果旋转180°来观察，则将上下反转来读，这是不言而喻的。
<绝缘栅极型半导体装置>
作为实施方式所涉及的绝缘栅极型半导体装置，例示具有沟槽栅极构造的IGBT。实施方式所涉及的绝缘栅极型半导体装置例如可以是将IGBT和续流二极管(FWD)单片化而成的反向导通IGBT(RC-IGBT)。
如图1所示，实施方式所涉及的绝缘栅极型半导体装置具备栅极沟槽51、52和虚设沟槽41、42、43、44。在图1中，为了方便，省略了配置于栅极沟槽51、52和虚设沟槽41～44上的层间绝缘膜、主电荷供给电极(发射极电极)以及保护膜等。另外，在图1中，为了方便，用虚线示意性地示出位于检查用绝缘膜11的下层的栅极表面布线14、栅极沟槽51、52。另外，用虚线示意性地示出位于连接区14a、14b、14c、14d的下层的虚设沟槽41、42、43、44。
在图1中虽然省略了虚设沟槽41～44的下端，但是虚设沟槽41～44具有将彼此平行地延伸的2个条部的上端及下端彼此连接而成的扁平的O字状的平面图案。虚设沟槽41～44以虚设沟槽41～44的各个虚设沟槽的2个条部彼此平行地排列的方式被周期性地设置。此外，对虚设沟槽41～44的个数、宽度、条部的长度等没有特别限定。虚设沟槽41～44也可以具有I字状的平面图案来取代O字状的平面图案。
栅极沟槽51、52以包围虚设沟槽42、44的周围的方式具有扁平O字状的平面图案。栅极沟槽51具有与虚设沟槽41～44的条部平行地延伸的条部511、512、以及将邻接的条部511、512彼此连接起来的连接部513。栅极沟槽52具有与虚设沟槽41～44的条部平行地延伸的条部521、522、以及将邻接的条部521、522彼此连接起来的连接部523。
此外，对栅极沟槽51、52的个数、宽度、以及栅极沟槽51、52的条部511、512、521、522的长度等没有特别限定。栅极沟槽51、52的宽度可以与虚设沟槽41～44的宽度相同，也可以彼此不同。栅极沟槽51、52也可以构成在虚设沟槽41～44间蛇行地通过的曲折线来取代O字状的平面图案，该曲折线是U字状的平面图案反向连接而成的。
在栅极沟槽51、52的连接部513、523上配置有栅极表面布线14。在虚设沟槽41～44各自的端部上，以与栅极表面布线14分开的方式设置有连接区14a～14d。栅极表面布线14和连接区14a～14d例如由高杂质浓度地添加了磷(P)等杂质的多晶硅(掺杂多晶硅(DOPOS))等形成。
图2是从图1的A-A′方向观察而得到的截面图。如图2所示，实施方式所涉及的绝缘栅极型半导体装置具备第一导电型(n-型)的电荷输送区(漂移区)1。电荷输送区1是能够利用漂移电场来输送成为主电流的载流子(电子)的半导体区。在电荷输送区1的上部设置有作为第二导电型(p型)的体区的注入控制区(基区)2。注入控制区2是对向电荷输送区1注入的载流子进行控制的半导体区。在注入控制区2的上部设置有杂质浓度比电荷输送区1的杂质浓度高的n+型的主电荷供给区(发射极区)3a、3b、3c、3d。
此外，虽然省略图示，但是在注入控制区2的上部也可以以与主电荷供给区3a～3d相接的方式设置第二导电型(p+型)的接触区。例如，主电荷供给区3a～3d和接触区可以与图1示出的栅极沟槽51、52的条部511、512、521、522延伸的方向平行地周期性地交替设置。
如图2所示，以从主电荷供给区3a～3d的上表面起贯通主电荷供给区3a～3d和注入控制区2并到达电荷输送区1的上部的方式设置有虚设沟槽42和栅极沟槽51。虚设沟槽42和栅极沟槽51具有大致相同的深度。
在虚设沟槽42和栅极沟槽51的底面及侧面设置有栅极绝缘膜6。作为栅极绝缘膜6，除了能够采用氧化硅膜(SiO2膜)以外，还能够采用氮氧化硅(SiON)膜、锶氧化物(SrO)膜、硅氮化物(Si3N4)膜、铝氧化物(Al2O3)膜、镁氧化物(MgO)膜、钇氧化物(Y2O3)膜、铪氧化物(HfO2)膜、锆氧化物(ZrO2)膜、钽氧化物(Ta2O5)膜、铋氧化物(Bi2O3)膜中的任一单层膜、或者将这些单层膜中的多个单层膜层叠而成的复合膜等。
栅极沟槽51的栅极绝缘膜6作为如下的栅极膜发挥功能：在主电荷供给区3a～3d正下方的注入控制区2以静电方式控制沟道的表面电位。另一方面，虚设沟槽42的栅极绝缘膜6不作为栅极膜发挥功能，但是在元件的动作上需要确保一定的绝缘性。最被要求绝缘性的部分是电场集中的虚设沟槽42的底部区，在虚设沟槽42的栅极绝缘膜6中，与栅极沟槽51的栅极绝缘膜6同样，也需要确保对于随着时间的经过而发生绝缘击穿的TDDB现象的可靠性。通过电压施加来筛查虚设沟槽42及栅极沟槽51的形状异常、虚设沟槽42及栅极沟槽51与电极之间的栅极绝缘膜6的膜质劣化之类的不良状况，由此能够提高对于TDDB的可靠性。
隔着栅极绝缘膜6在虚设沟槽42的内侧埋入有虚设电极72。虚设电极72例如具有降低导致开关损耗的栅极-集电极间的电容的功能。隔着栅极绝缘膜6在栅极沟槽51的内侧埋入有栅极电极71。作为虚设电极72和栅极电极71的材料，例如能够使用DOPOS。此外，图2示出的虚设沟槽41、43～44也具有与虚设沟槽42同样的结构。另外，图2示出的栅极沟槽52也具有与栅极沟槽51同样的结构。
如图2所示，在栅极电极71上设置有层间绝缘膜(11、12、13)。栅极电极71上的层间绝缘膜(11、12、13)是具有检查用绝缘膜11、设置于检查用绝缘膜11上的连接用绝缘膜12、以及设置于连接用绝缘膜12上的上层绝缘膜13的3层构造。另一方面，在虚设电极72上设置有层间绝缘膜(12、13)。虚设电极72上的层间绝缘膜(12、13)是不具有检查用绝缘膜11、而具有连接用绝缘膜12以及设置于连接用绝缘膜12上的上层绝缘膜13的2层构造。即，栅极电极71上的层间绝缘膜(11、12、13)具有多个绝缘膜的层叠构造，栅极电极71上的层间绝缘膜(11、12、13)的绝缘膜比虚设电极72上的层间绝缘膜(12、13)的绝缘膜多1层以上。
例如，栅极电极71上的检查用绝缘膜11的膜厚度为50nm～100nm左右，栅极电极71和虚设电极72上的连接用绝缘膜12的膜厚度为50nm～100nm左右，栅极电极71和虚设电极72上的上层绝缘膜13的膜厚度为50nm～100nm左右。
此外，在栅极电极71和虚设电极72上也可以不必设置上层绝缘膜13。在不设置上层绝缘膜13的情况下，栅极电极71上的层间绝缘膜(11、12)成为具有检查用绝缘膜11、以及设置于检查用绝缘膜11上的连接用绝缘膜12的2层构造，另一方面，虚设电极72上的层间绝缘膜12成为具有连接用绝缘膜12的单层构造。
检查用绝缘膜11被设置为将图1示出的栅极沟槽51、52及栅极表面布线14上覆盖。在图1中省略了图2示出的连接用绝缘膜12和上层绝缘膜13的图示，但是图2示出的连接用绝缘膜12和上层绝缘膜13设置于半导体基板1的上表面的整个面。虽然在图1中省略了连接用绝缘膜12和上层绝缘膜13的图示，但是如图1中用单点划线示意性地示出的那样，在连接用绝缘膜12和上层绝缘膜13上开孔出接触孔31a～31j和接触孔32a～32h。
作为检查用绝缘膜11、连接用绝缘膜12以及上层绝缘膜13，能够采用高温氧化膜(HTO膜)、被称为“NSG”的不含磷(P)、硼(B)的非掺杂的氧化硅(SiO2)膜。另外，作为检查用绝缘膜11、连接用绝缘膜12以及上层绝缘膜13，也可以是添加了磷的氧化硅(PSG)膜、添加了硼的氧化硅(BSG)膜、添加了硼和磷的氧化硅(BPSG)膜、氮化硅(Si3N4)膜。另外，作为检查用绝缘膜11、连接用绝缘膜12以及上层绝缘膜13，也可以是这些能够采用的膜的层叠。检查用绝缘膜11、连接用绝缘膜12以及上层绝缘膜13的材料可以彼此相同，也可以彼此不同。例如，也可以是，检查用绝缘膜11和连接用绝缘膜12由HTO膜形成，上层绝缘膜13是能够回流的BPSG膜。
在上层绝缘膜13上配置有主电荷供给电极(发射极电极)15。主电荷供给电极15经由在连接用绝缘膜12和上层绝缘膜13上开孔出的接触孔31a～31j来与主电荷供给区3a～3d等电连接或者金属性地接合。
如图1所示，在虚设沟槽41～44的端部上配置有连接区14a、14b、14c、14d。虚设沟槽41～44经由在位于连接区14a～14d上的连接用绝缘膜12和上层绝缘膜13上开孔出的接触孔32a～32h，来与主电荷供给电极15电连接。在图1中，用单点划线示意性地示出接触孔32a～32h的位置。
在栅极沟槽51、52的连接部513、523上以与连接部513、523相接的方式配置有栅极表面布线14。栅极表面布线14与虚设沟槽41～44电绝缘分离，虚设沟槽41～44无助于沟道的形成。
图3是从图1的B-B′方向观察而得到的截面图。如图3所示，在注入控制区2上，栅极表面布线14与连接区14c分开地设置。以覆盖栅极表面布线14的方式设置有检查用绝缘膜11。在检查用绝缘膜11和连接区14c上设置有连接用绝缘膜12和上层绝缘膜13。
在图2示出的电荷输送区1下设置有n+型的场截止层(Field stop layer)8。此外，也可以是设置缓冲层来取代场截止层8的构造，还可以是没有场截止层8的非穿通构造。在场截止层8下配置有p+型的主电荷接收区(集电极区)9，在集电极区9下配置有主电荷接收电极(集电极电极)10。作为主电荷接收电极10，例如能够使用由金(Au)形成的单层膜、将Al、镍(Ni)、Au按该顺序层叠而成的金属膜。
在实施方式所涉及的绝缘栅极型半导体装置进行动作时，在向主电荷接收电极10施加正的电压的同时，在主电荷供给电极15接地的状态下向栅极电极71施加阈值以上的正的电压。由此，注入控制区2的面向栅极沟槽51的表面电位隔着栅极绝缘膜6被以静电方式进行控制，从而形成沟道，IGBT成为接通状态。在接通状态下，作为多数载流子的电子从主电荷供给区3a～3d被注入到电荷输送区1，作为少数载流子的空穴从集电极区9被注入到电荷输送区1。由于被注入到电荷输送区1内的空穴和电子而产生电导率调制，电荷输送区1内的电阻变小。此时，由于与栅极电极71相邻接地配置有虚设电极72，因此栅极-集电极电容(反馈电容)的一部分被置换为集电极-发射极间电容，因此反馈电容降低，开关速度提高。
另一方面，当施加到栅极电极71的电压小于阈值时，在注入控制区2中形成的电子的沟道消失，IGBT成为断开状态。在断开状态下，蓄积于电荷输送区1内的电子从集电极区9排出，蓄积于电荷输送区1内的空穴从接触区排出。
<绝缘栅极型半导体装置的制造方法>
接着，参照图4～图15来说明包括实施方式所涉及的绝缘栅极型半导体装置的筛查方法在内的实施方式所涉及的绝缘栅极型半导体装置的制造方法的一例。在此，主要着眼于图2示出的表现出虚设沟槽42和栅极沟槽51的截面来进行说明。
首先，准备由n-型的Si形成的半导体基板1来作为基体部(参照图2)。接着，向半导体基板1的上表面的整个面离子注入呈p型的杂质离子。之后，进行热处理，由此使呈p型的杂质离子活化而成为p型杂质，使p型杂质热扩散到作为注入控制区2所需的扩散深度。此外，注入控制区2也可以是在半导体基板1的上表面外延生长而成的。接着，在注入控制区2的上表面涂布光致抗蚀剂膜，并使用光刻技术将光致抗蚀剂膜形成图案。将形成图案后的光致抗蚀剂膜用作离子注入用掩模，向注入控制区2的上表面选择性地离子注入呈n型的杂质离子。之后，进行热处理，由此使呈n型的杂质离子活化并热扩散。其结果，如图4所示，在注入控制区2的上部形成n+型的电极区预定层3A、3B。
接着，通过化学气相沉积(CVD)法等在注入控制区2和电极区预定层3A、3B的上表面形成氧化膜等蚀刻保护膜16。然后，使用光刻技术和反应性离子蚀刻(RIE)等干蚀刻来将蚀刻保护膜16形成图案。将形成图案后的蚀刻保护膜16用作蚀刻用掩模(etching mask)，如图5所示，通过RIE等干蚀刻选择性地形成虚设沟槽42和栅极沟槽51。图4示出的电极区预定层3A、3B被分离为图5示出的主电荷供给区(发射极区)3a～3d。虚设沟槽42和栅极沟槽51贯通主电荷供给区3a～3d和注入控制区2并到达半导体基板1的上部。此时，与虚设沟槽42及栅极沟槽51同样地也形成图1示出的虚设沟槽41、43、44和栅极沟槽52。之后，去除蚀刻保护膜16。
接着，通过热氧化法或者CVD法等，在虚设沟槽42和栅极沟槽51的底面及侧面、以及注入控制区2和主电荷供给区3a～3d的上表面形成SiO2膜等栅极绝缘膜6。接着，通过CVD法等，以将虚设沟槽42和栅极沟槽51填埋的方式沉积DOPOS层(第一DOPOS膜)等导电膜(埋入用导电膜)。之后，通过凹蚀(etch back)或者化学机械研磨(CMP)等，来去除注入控制区2和主电荷供给区3a～3d的上表面的埋入用导电膜和栅极绝缘膜6，使注入控制区2和主电荷供给区3a～3d的上表面露出。其结果，如图6所示，隔着栅极绝缘膜6在虚设沟槽42和栅极沟槽51中埋入有由埋入用导电膜形成的虚设电极72和栅极电极71。
接着，通过CVD法等来沉积由新的DOPOS膜(第二DOPOS膜)等形成的图案形成导电膜。然后，使用光刻技术和RIE等干蚀刻来将图案形成导电膜形成图案，由此如图7所示形成栅极表面布线14和连接区14a～14d。连接区14a～14d以与虚设沟槽41～44相接的方式局部地形成在虚设沟槽41～44的端部上。栅极表面布线14形成为与连接区14a～14d分离，且在栅极沟槽51、52的连接部513、523上与连接部513、523相接。
接着，通过CVD法等，在虚设电极72、栅极电极71、注入控制区2以及主电荷供给区3a～3d的上表面沉积作为HTO膜等的检查用绝缘膜11。然后，通过光刻技术和干蚀刻将检查用绝缘膜11形成图案。其结果，如图8A所示，检查用绝缘膜11被形成为将栅极表面布线14和栅极沟槽51、52上覆盖。连接区14a～14d和虚设沟槽41～44的上表面从检查用绝缘膜11的开口部露出。
图8B是从图8A的A-A′方向观察而得到的工序截面图。如图8B所示，栅极电极71的上表面被检查用绝缘膜11所覆盖。虚设电极72上未被检查用绝缘膜11覆盖而露出。
接着，如图9所示，通过CVD法等，在虚设电极72、注入控制区2以及主电荷供给区3a～3d的上表面的整个面上形成由第三DOPOS膜等形成的检查用导电膜20。
接着，使用沉积于整个面的检查用导电膜20，来与栅极沟槽51的栅极绝缘膜6相独立地仅检查虚设沟槽42的栅极绝缘膜6的绝缘特性，由此仅对虚设沟槽42的栅极绝缘膜6进行筛查。具体地说，如图10所示，将半导体基板1的下表面配置于导电性的台22。然后，将电源21的负极侧与台22电连接，将与电源21的正极侧电连接的探针23的前端压接于检查用导电膜20。在该状态下，由电源在检查用导电膜20与半导体基板1的下表面之间施加比通常的动作时高的电压来进行虚设栅极冲击试验。虚设栅极冲击试验是用于评价TDDB现象的加速试验。虚设栅极冲击试验是在检查用导电膜20与半导体基板1的下表面之间施加比施加于虚设栅极-集电极间的通常的电压(例如2MV/cm左右)高的电压(例如4MV/cm左右)来进行的。之后，测量在检查用导电膜20与半导体基板1的下表面之间流过的电流。在检查用导电膜20与半导体基板1的下表面之间的漏电流为基准值以上的情况下，能够判定为栅极绝缘膜6产生了膜质劣化，因此能够检查栅极绝缘膜6的绝缘特性。
接着，去除检查用导电膜20。接着，如图11所示，通过CVD法等，在半导体基板1的上表面的整个面、即虚设电极72、检查用绝缘膜11、注入控制区2以及主电荷供给区3a～3d的上表面沉积作为HTO膜等的连接用绝缘膜12。连接用绝缘膜12的材料既可以与检查用绝缘膜11的材料相同，也可以不同。此外，也可以在沉积连接用绝缘膜12之前去除检查用绝缘膜11。
接着，如图12所示，通过CVD法等，在连接用绝缘膜12的上表面的整个面上沉积作为BPSG膜等的上层绝缘膜13。上层绝缘膜13的材料既可以与检查用绝缘膜11及连接用绝缘膜12的材料相同，也可以不同。此外，也可以不必形成上层绝缘膜13。
接着，通过光刻技术和干蚀刻，来选择性地去除连接用绝缘膜12和上层绝缘膜13的一部分。由此，在连接用绝缘膜12和上层绝缘膜13上开孔出接触孔，使主电荷供给区3a～3d的上表面露出。此外，在不形成上层绝缘膜13的情况下，也可以仅在连接用绝缘膜12上开孔出接触孔。另外，在连接用绝缘膜12和上层绝缘膜13上开孔出接触孔，使图8A示出的连接区14a～14d的上表面露出。
接着，通过溅射法或者蒸镀法等，在上层绝缘膜13、主电荷供给区3a～3d以及连接区14a～14d的整个面上沉积Al膜等金属层。然后，使用光刻技术和RIE等干蚀刻将Al膜等金属层形成图案，如图14所示，形成经由接触孔来与主电荷供给区3a～3d欧姆接触的主电荷供给电极15。
接着，通过CMP等来调整半导体基板1的厚度。然后，在半导体基板1的下表面，向半导体基板1的下表面离子注入呈p型的杂质离子。另外，向半导体基板1的下表面，以比呈p型的杂质离子的离子注入深的投影射程来离子注入呈n型的杂质离子。之后，通过热处理使注入的杂质离子活化并热扩散，由此如图15所示，形成n+型的场截止层8和p+型的集电极区9。此外，场截止层8和集电极区9也可以是在半导体基板1的下表面依次外延生长而成的。
接着，如图2所示，通过溅射法或者蒸镀法等，在集电极区9的下表面形成由Au等形成的主电荷接收电极10。之后，通过切割来将半导体晶圆分割为多个半导体芯片，实施方式所涉及的绝缘栅极型半导体装置完成。
之后，针对每个半导体芯片进行用于检查栅极沟槽51、52的栅极绝缘膜6的绝缘特性的栅极冲击试验，由此对栅极沟槽51、52的栅极绝缘膜6的不良进行筛查。该筛查成为对栅极沟槽51、52的栅极绝缘膜6的最初的栅极冲击试验。
根据实施方式所涉及的绝缘栅极型半导体装置的制造方法，通过检查虚设沟槽41～44的栅极绝缘膜6的绝缘特性，能够适当地保证虚设沟槽41～44的栅极绝缘膜6的质量。此时，通过由检查用绝缘膜11来将栅极沟槽51、52上覆盖，能够与栅极沟槽51、52的栅极绝缘膜6相独立地仅检查虚设沟槽41～44的栅极绝缘膜6的绝缘特性。由此，能够消除将会对栅极沟槽51、52的栅极绝缘膜6造成的影响。另外，虚设沟槽41～44的栅极绝缘膜6所被要求的绝缘特性比栅极沟槽51、52的栅极绝缘膜6所被要求的绝缘特性低，因此能够与虚设沟槽41～44的栅极绝缘膜6所被要求的耐性相匹配地使在筛查试验中施加的电压值缓和。因而，能够降低不良产生率，并且能够抑制不良产生时的微粒产生量，因此能够抑制对工序内环境的污染。另一方面，对于栅极沟槽51、52的栅极绝缘膜6，在流程完成后通过栅极冲击试验来检查栅极沟槽51、52的栅极绝缘膜6的绝缘特性，由此也能够筛查流程中途的损伤。
<比较例>
接着，说明比较例所涉及的绝缘栅极型半导体装置的筛查方法。在比较例所涉及的绝缘栅极型半导体装置的筛查方法中，如图16所示，在半导体基板100的上部形成栅极沟槽101和虚设沟槽102。之后，隔着栅极绝缘膜103在栅极沟槽101中埋入栅极电极111。隔着栅极绝缘膜103在虚设沟槽102中埋入虚设电极112。
接着，如图17所示，遍及栅极电极111和虚设电极112上的整个面地形成导电膜104。然后，将半导体基板100的下表面配置于导电性的台22。然后，将电源21的负极侧与台22电连接，将与电源21的正极侧电连接的探针23的前端压接于导电膜104。在该状态下，由电源在导电膜104与半导体基板1的下表面之间施加比通常的动作时高的电压来进行栅极冲击试验。即，遍及栅极沟槽101和虚设沟槽102的沟槽全体地同时进行栅极绝缘膜6的试验，因此需要在试验时施加比较大的电压，在不良元件破损时产生大量的微粒。与此相对，在本发明的实施方式所涉及的绝缘栅极型半导体装置的筛查方法中，由于检查用绝缘膜11将栅极沟槽51、52上覆盖，因此能够相独立地仅筛查虚设沟槽41～44的栅极绝缘膜6，能够抑制微粒的产生量。
(其它实施方式)
如上所述，通过实施方式对本发明进行了记载，但是不应理解为构成本公开的一部分的论述和附图用于限定本发明。根据本公开，本领域技术人员可以明确各种代替实施方式、实施例以及应用技术。
例如，作为实施方式所涉及的绝缘栅极型半导体装置，例示了沟槽栅极型的IGBT，但是不限定于此，能够应用于沟槽栅极型的MISFET等各种绝缘栅极型半导体装置。
另外，在实施方式所涉及的绝缘栅极型半导体装置的说明中，例示了使用Si的绝缘栅极型半导体装置。但是，除了能够应用于使用Si的绝缘栅极型半导体装置以外，也能够应用于使用碳化硅(SiC)、氮化镓(GaN)、金刚石或者氮化铝(AlN)等禁带宽度比Si的禁带宽度宽的半导体(宽带隙半导体)材料的绝缘栅极型半导体装置。
像这样，本发明包括在此没有记载的各种实施方式等，这是不言而喻的。因而，本发明的技术范围仅通过根据上述的说明妥当地得出的权利要求书所涉及的发明特征来决定。

Claims (7)

1.一种绝缘栅极型半导体装置，其特征在于，具备：
第一导电型的电荷输送区；
所述电荷输送区上的第二导电型的注入控制区；
所述注入控制区上的第一导电型的主电荷供给区；
虚设电极，其隔着栅极绝缘膜埋入于贯通所述主电荷供给区和所述注入控制区并到达所述电荷输送区的虚设沟槽；
栅极电极，其隔着所述栅极绝缘膜埋入于贯通所述主电荷供给区和所述注入控制区并到达所述电荷输送区的栅极沟槽；
所述栅极电极上的第一层间绝缘膜；以及
所述虚设电极上的第二层间绝缘膜，
其中，所述第一层间绝缘膜具有多个绝缘膜的层叠构造，所述第一层间绝缘膜的绝缘膜比所述第二层间绝缘膜的绝缘膜多1层以上。
2.根据权利要求1所述的绝缘栅极型半导体装置，其特征在于，
所述第一层间绝缘膜由所述栅极电极上的检查用绝缘膜、所述检查用绝缘膜上的连接用绝缘膜以及所述连接用绝缘膜上的上层绝缘膜的层叠构造形成，
所述第二层间绝缘膜由所述虚设电极上的所述连接用绝缘膜和所述上层绝缘膜的层叠构造形成。
3.根据权利要求2所述的绝缘栅极型半导体装置，其特征在于，
所述检查用绝缘膜和所述连接用绝缘膜由彼此相同的材料形成。
4.一种绝缘栅极型半导体装置的制造方法，其特征在于，包括以下工序：
在第一导电型的电荷输送区上形成第二导电型的注入控制区；
在所述注入控制区上形成第一导电型的主电荷供给区；
以贯通所述主电荷供给区和所述注入控制区的方式掘出栅极沟槽和虚设沟槽；
隔着栅极绝缘膜在所述虚设沟槽中埋入虚设电极，并且隔着所述栅极绝缘膜在所述栅极沟槽中埋入栅极电极；
以将所述虚设电极上露出、且将所述栅极电极覆盖的方式选择性地形成检查用绝缘膜；
在所述虚设电极和所述检查用绝缘膜上沉积检查用导电膜；以及
在所述检查用导电膜与所述电荷输送区之间施加电压，由此选择性地检查所述虚设沟槽内的所述栅极绝缘膜的绝缘特性。
5.根据权利要求4所述的绝缘栅极型半导体装置的制造方法，其特征在于，
在所述检查的工序后，还包括去除所述检查用导电膜的工序。
6.根据权利要求5所述的绝缘栅极型半导体装置的制造方法，其特征在于，
在去除所述检查用导电膜的工序后，还包括以下工序：
以覆盖所述检查用绝缘膜的方式沉积连接用绝缘膜；
在所述连接用绝缘膜上开孔出接触孔；以及
形成经由所述接触孔来与所述主电荷供给区电连接的主电荷供给电极。
7.根据权利要求5所述的绝缘栅极型半导体装置的制造方法，其特征在于，
在去除所述检查用导电膜的工序后，还包括以下工序：
以覆盖所述检查用绝缘膜的方式沉积连接用绝缘膜；
以覆盖所述连接用绝缘膜的方式沉积上层绝缘膜；
在所述连接用绝缘膜和所述上层绝缘膜上开孔出接触孔；以及
形成经由所述接触孔来与所述主电荷供给区电连接的主电荷供给电极。
CN202010000510.4A 2019-02-25 2020-01-02 绝缘栅极型半导体装置及其制造方法 Pending CN111613667A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2019-031543 2019-02-25
JP2019031543A JP7272004B2 (ja) 2019-02-25 2019-02-25 絶縁ゲート型半導体装置及びその製造方法

Publications (1)

Publication Number Publication Date
CN111613667A true CN111613667A (zh) 2020-09-01

Family

ID=72142051

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010000510.4A Pending CN111613667A (zh) 2019-02-25 2020-01-02 绝缘栅极型半导体装置及其制造方法

Country Status (3)

Country Link
US (1) US11081576B2 (zh)
JP (1) JP7272004B2 (zh)
CN (1) CN111613667A (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114093930A (zh) * 2021-11-18 2022-02-25 南京芯长征科技有限公司 能抑制开关震荡的功率半导体器件及其制备方法
CN117747612A (zh) * 2024-02-19 2024-03-22 合肥晶合集成电路股份有限公司 半导体器件以及半导体器件的制作方法

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7210342B2 (ja) * 2019-03-18 2023-01-23 株式会社東芝 半導体装置
US11101375B2 (en) 2019-03-19 2021-08-24 Kabushiki Kaisha Toshiba Semiconductor device and method of controlling same
KR20210130333A (ko) * 2020-04-21 2021-11-01 삼성디스플레이 주식회사 표시장치 및 그 검사방법

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102208367A (zh) * 2010-03-30 2011-10-05 三美电机株式会社 半导体装置的制造方法
JP2012142628A (ja) * 2012-04-26 2012-07-26 Mitsubishi Electric Corp 電力用半導体装置
CN104685613A (zh) * 2012-10-02 2015-06-03 三菱电机株式会社 半导体装置、半导体装置的制造方法
CN107078061A (zh) * 2015-03-16 2017-08-18 富士电机株式会社 半导体装置的制造方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5634318B2 (ja) * 2011-04-19 2014-12-03 三菱電機株式会社 半導体装置
JP2016025124A (ja) * 2014-07-16 2016-02-08 株式会社デンソー 半導体装置およびその製造方法
US10580708B2 (en) * 2017-02-17 2020-03-03 Ablic Inc. Method of manufacturing a semiconductor device and semiconductor device
JP6729452B2 (ja) * 2017-03-06 2020-07-22 株式会社デンソー 半導体装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102208367A (zh) * 2010-03-30 2011-10-05 三美电机株式会社 半导体装置的制造方法
JP2012142628A (ja) * 2012-04-26 2012-07-26 Mitsubishi Electric Corp 電力用半導体装置
CN104685613A (zh) * 2012-10-02 2015-06-03 三菱电机株式会社 半导体装置、半导体装置的制造方法
CN107078061A (zh) * 2015-03-16 2017-08-18 富士电机株式会社 半导体装置的制造方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114093930A (zh) * 2021-11-18 2022-02-25 南京芯长征科技有限公司 能抑制开关震荡的功率半导体器件及其制备方法
CN117747612A (zh) * 2024-02-19 2024-03-22 合肥晶合集成电路股份有限公司 半导体器件以及半导体器件的制作方法
CN117747612B (zh) * 2024-02-19 2024-05-24 合肥晶合集成电路股份有限公司 半导体器件以及半导体器件的制作方法

Also Published As

Publication number Publication date
JP7272004B2 (ja) 2023-05-12
US20200273971A1 (en) 2020-08-27
JP2020136601A (ja) 2020-08-31
US11081576B2 (en) 2021-08-03

Similar Documents

Publication Publication Date Title
CN111613667A (zh) 绝缘栅极型半导体装置及其制造方法
JP7351086B2 (ja) 絶縁ゲート型半導体装置及びその製造方法
JP5045441B2 (ja) 半導体装置およびその製造方法
US7700971B2 (en) Insulated gate silicon carbide semiconductor device
JP7283107B2 (ja) 絶縁ゲート型半導体装置及びその製造方法
US8723259B2 (en) Silicon carbide semiconductor device
US8269272B2 (en) Semiconductor device and method for manufacturing the same
US20130270577A1 (en) Grid-umosfet with electric field shielding of gate oxide
US9318565B2 (en) Power semiconductor device with dual field plate arrangement and method of making
JP2019071313A (ja) 半導体装置
JP5878331B2 (ja) 半導体装置及びその製造方法
WO2022137788A1 (ja) 絶縁ゲート型半導体装置
US10593792B2 (en) Semiconductor device and method for manufacturing the same
CN111725304A (zh) 绝缘栅极型半导体装置
US20240170569A1 (en) Semiconductor device and method of manufacturing the same
CN111834448A (zh) 碳化硅半导体装置
JP6804690B2 (ja) 半導体装置
JP2021150405A (ja) 炭化珪素半導体装置
KR100703231B1 (ko) 반도체장치 및 그 제조방법
US20240194745A1 (en) Semiconductor device having a shielding layer and a method of fabricating the semiconductor device
WO2022137789A1 (ja) 絶縁ゲート型半導体装置
US20240021723A1 (en) Silicon carbide semiconductor device
JP7113386B2 (ja) 半導体装置
JP2022184484A (ja) 半導体装置
CN118263324A (zh) 碳化硅mos场效应晶体管及其制造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination