CN111477542A - 一种含超级结的3C-SiC外延结构及其制备方法 - Google Patents
一种含超级结的3C-SiC外延结构及其制备方法 Download PDFInfo
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Abstract
本发明公开了一种含超级结的3C‑SiC外延结构及其制备方法,所述制备方法包括以下步骤:在衬底上生长N型外延层;由N型外延层的表面向下刻蚀沟槽;向沟槽内填充P型外延层;CMP抛光,抛去在填充的过程中台面顶部过生长的外延层,直至得到表面光滑的N型、P型交替的外延层表面;在表面光滑的N型、P型交替的外延层表面上生长3C‑SiC外延层。本发明通过在3C‑SiC外延层之下设置超级结结构,补偿了3C‑SiC器件耐压低的劣势。
Description
技术领域
本发明属于半导体技术领域,具体涉及一种含超级结的3C-SiC外延结构及其制备方法。
背景技术
SiC作为第三代宽禁带半导体材料的典型代表,具有宽禁带宽度、高临界击穿场强、高热导率及高载流子饱和速率等特性。上述材料优势使得SiC功率半导体器件在新能源汽车、轨道交通、光伏、智能电网等中高耐压等级应用领域具有广阔的发展前景。
SiC的一个显著特点是具有多种同质异型体,SiC的晶体结构按对称性可分为三大类型:立方、六方和菱形。4H-SiC、6H-SiC、3C-SiC、15R-SiC等晶型是SiC众多同质异晶型结构中常见的几种。在SiC的同质异型体中,3C-SiC是唯一具有闪锌矿结构的半导体,称为β-SiC。而具有六方或菱形结构的同质异晶型,如:4H-SiC、6H-SiC、15R-SiC,称为α-SiC。
目前4H-SiC器件已经广泛应用于电动汽车领域,然而3C-SiC材料的潜力尚未挖掘。对比3C-SiC和4H-SiC材料特性,3C-SiC饱和电子漂移速度(2.5×107cm/s)是4H-SiC(2.0×107cm/s)的1.25倍,电子迁移率(1000cm2/V·s)比4H-SiC(947cm2/V·s)高,热导率(5W/cm·℃)比4H-SiC(4.9W/cm·℃)高,较高的饱和电子漂移速度和迁移率决定了3C-SiC器件具有优良的微波特性,高的热导率有利于器件散热,这使得3C-SiC在高温高频场效应晶体管器件方面具有广泛的应用前景。
但3C-SiC的禁带宽度(2.3eV)比4H-SiC(3.2eV)低0.9eV,临界击穿场强(2.1MV/cm)比4H-SiC(3.2MV/cm)低1.1eV。较低的禁带宽度意味着3C-SiC在相同的辐照条件下产生更多的电子空穴对,当本征激发所产生的载流子浓度超过掺杂浓度时,会导致半导体器件的失效。较低的临界击穿场强意味着对于击穿电压相同的器件,3C-SiC器件所需的耗尽区宽度更宽,掺杂区的掺杂浓度更低,以阻断高压,从而导致器件的导通电阻大幅度的增加。其中,功率半导体器件的理论阻断电压和比导通电阻之间存在一维极限关系:Ron,sp∝BV2.3~2.5。而3C-SiC临界击穿场强较低,限制了其在高压领域的应用。
发明内容
为解决上述技术问题,本发明提供了一种含超级结的3C-SiC外延结构及其制备方法,通过在3C-SiC外延层之下设置超级结结构,补偿了3C-SiC器件耐压低的劣势。
并进一步在向沟槽内填充P型外延层之前,在沟槽内续长了本征4H-SiC缓冲层,以缓解晶格失配,提高晶体质量。
并在3C-SiC外延层生长之前,在表面光滑的N型、P型交替的外延层表面上进行了图形化处理,以生长缺陷较少的3C-SiC薄膜,抑制界面缺陷向薄膜内传播,获得表面平整的3C-SiC薄膜。
本发明采取的技术方案为:
一种含超级结的3C-SiC外延结构制备方法,所述制备方法包括以下步骤:
(1)在衬底上生长N型外延层;
(2)由N型外延层的表面向下刻蚀沟槽;
(3)向沟槽内填充P型外延层;
(4)CMP抛光,抛去在填充的过程中台面顶部过生长的外延层,直至得到表面光滑的N型、P型交替的外延层表面;
(5)在表面光滑的N型、P型交替的外延层表面上生长3C-SiC外延层。
进一步地,所述步骤(2)和步骤(3)之间还包括在沟槽内生长本征缓冲层的步骤,和/或,所述步骤(4)和步骤(5)之间还包括对表面光滑的N型、P型交替的外延层表面进行图形化处理的步骤。
进一步地,所述本征缓冲层的厚度为10~100nm;N的原子半径比C和Si原子半径小,Al的原子半径比C和Si原子半径大,在N型4H-SiC外延层和P型4H-SiC外延层之间插入晶格常数在N型4H-SiC外延层与P型4H-SiC外延层之间的本征4H-SiC,缓解晶格失配,提高晶体质量。
进一步地,反复重复所述步骤(1)-步骤(4)继续在光滑的N型、P型交替的外延层表面上生长N型外延层、刻蚀沟槽并进行填充,并保持步骤(2)中沟槽刻蚀位置不变但后续刻蚀深度为整个N型外延层厚度,进一步实现15μm以上的深沟槽的刻蚀与填充,提升3C-SiC外延结构的耐压能力。
进一步地,步骤(2)中,沟槽深度5-15μm,沟槽侧壁倾角86~90°,沟槽底部与顶部宽度一致,均为2~2.5μm。
进一步地,所述N型外延层的厚度为5~20μm;所述本征缓冲层的厚度为10~100nm;所述本征缓冲层为4H-SiC本征缓冲层。
所述3C-SiC外延层的厚度为3~10μm,所述3C-SiC外延层的掺杂浓度为3×1014cm-3~9×1016cm-3。3C-SiC厚度越厚,晶体质量越差,厚度越薄增加栅氧工艺的难度,此厚度下,晶体质量较好且工艺难度较小。
进一步地,所述N型外延层为N型4H-SiC外延层;所述P型外延层为P型4H-SiC外延层。
步骤(3)中,所述P型外延层的填充工艺为:向外延腔中通入H2、含氯的硅源气体、碳源、HCl和Al掺杂剂,在1600~1700℃、400~600mbar压力下进行沟槽填充,直至沟槽填满。
进一步地,所述H2、含氯的硅源气体、碳源、HCl和Al掺杂剂的流量分别为50~150slm、50~100sccm、50~100sccm、1000~5000sccm和500~1000sccm,并且控制Cl/Si=20~50。
进一步地,图形化处理时,采用光刻、反应离子刻蚀工艺刻蚀平均分布的图形,图形可以为正方形、长方形、菱形或六边形;通过对P型外延层表面进行图形化处理以生长缺陷较少的3C-SiC薄膜,抑制界面缺陷向薄膜内传播,获得表面平整的3C-SiC薄膜。
图形深度为1-2μm,图形尺寸为3-20μm,图形间隔为3-20μm;图形深度、尺寸和间隔越大,图形完整性较容易的保持,但结合成膜可能需要更长时间,才能获得表面平整的3C-SiC薄膜,因此需要将本发明中的光刻图形尺寸限定在上述范围内,以在保持图形完整性的同时获得较为平整的3C-SiC薄膜。
步骤(5)中,所述3C-SiC外延层的生长工艺为:向外延腔中通入H2、含氯的硅源气体、碳源、和N2掺杂剂,在1400~1550℃、50~600mbar压力下生长3C-SiC外延层。
进一步地,所述H2、含氯的硅源气体、碳源、和N2掺杂剂的流量为50~200slm,100~500sccm、100~500sccm和50~100sccm。
所述含氯的硅源气体为SiCl4,SiHCl3,SiH2C12或SiH3Cl。
与现有技术相比,本发明具有以下优点:
1.在3C-SiC外延层之下设置了超级结结构,补偿了3C-SiC器件耐压低的劣势,由于3C-SiC临界击穿场强较低,限制了其在高压领域的应用,而超级结结构宏观上可以看作为高阻半导体层,将传统的漂移层改为超级结结构,可补偿3C-SiC器件耐压低的劣势。
2.在向沟槽内填充P型外延层之前,在沟槽内续长了晶格常数在N型4H-SiC外延层与P型4H-SiC外延层之间的本征4H-SiC缓冲层,以缓解晶格失配,提高晶体质量。
3.在3C-SiC外延层生长之前,在表面光滑的N型、P型交替的外延层表面上进行了图形化处理,通过制作图形的方式引入有取向生长的台阶,控制薄膜初期的生长方向,使界面处晶向上的面缺陷随着薄膜厚度增加而自我消失,以生长缺陷较少的3C-SiC薄膜,抑制界面缺陷向薄膜内传播,获得表面平整的3C-SiC薄膜。
附图说明
图1为实施例1、3、4、6制备的含超级结的3C-SiC外延结构的示意图;
图2为实施例2、5制备的含超级结的3C-SiC外延结构的示意图;
图3为实施例3、6中对P型4H-SiC外延层的表面进行图形化处理后的六边形图形形状;
图4为实施例3、6中对P型4H-SiC外延层的表面进行图形化处理后的正方形图形形状;
图5为实施例3、6中对P型4H-SiC外延层的表面进行图形化处理后的长方形图形形状;
图6为实施例3、6中对P型4H-SiC外延层的表面进行图形化处理后的菱形图形形状;
图7为实施例1和比较例1中的外延结构按照常规方法制备成MOSFET器件,击穿电压VS导通电阻数据;
图中1-衬底、2-含超级结结构的N型4H-SiC外延层、3-P型4H-SiC外延层、4-3C-SiC外延层、5-本征4H-SiC缓冲层。
具体实施方式
下面结合实施例对本发明进行详细说明。
实施例1
一种含超级结的3C-SiC外延结构制备方法,包括以下步骤:
1)N型4H-SiC外延层生长:在外延炉生长5~20μm,掺杂浓度3×1014cm-3~9×1016cm-3N型4H-SiC外延层,取出,清洗;
2)沟槽刻蚀:沿<11-20>晶向刻蚀深度5-15μm,沟槽侧壁倾角86~90°,底部宽度与台面顶部宽度一致,均为2~2.5μm,刻蚀完去掉掩膜;再一次清洗,烘干,送入外延炉中;
3)填充P型4H-SiC外延层:分别以50~150slm、50~100sccm、50~100sccm、1000~5000sccm和500~1000sccm的流量通入H2、含氯的硅源气体、碳源、HCl和Al掺杂剂,控制Cl/Si=20~50,掺杂浓度3×1014cm-3~9×1016cm-3,,填充速率在5~8μm/h,于1600~1700℃温度和400~600mbar压力下,填满沟道;
4)CMP抛光:使用标准工艺进行化学机械抛光,抛去台面顶部过生长的4H-SiC,得到上表面光滑的交替排列的p型和n形区域。
5)在抛光后的P型4H-SiC外延层上生长3C-SiC外延层:分别以50~200slm,100~500sccm、100~500sccm和50~100sccm的流量通入载气H2,含氯的硅源气体、碳源和N2掺杂剂,在温度1400~1550℃和压力50~600mbar条件下,生长厚度3~10μm,掺杂浓度3×1014cm-3~9×1016cm-3 3C-SiC外延层。
实施例2
其他同实施例1,只是在步骤2)和步骤3)之间还进行了续长本征4H-SiC缓冲层的步骤,具体为:关闭N2掺杂剂,使用生长N型4H-SiC外延层的条件生长10~100nm厚的本征SiC外延层做为缓冲层,具体为:分别以20~100slm、20~100sccm、50~100sccm和1000~5000sccm的流量通入H2、含氯的硅源气体、碳源和HCl,控制Cl/Si=20~50,填充速率在1~5μm/h,于1600~1700℃温度和300~600mbar压力下生长。
实施例3
其他同实施例1或2,只是在步骤4)和步骤5)之间还进行了P型4H-SiC外延层表面图形化的步骤,具体为:CMP抛光之后,上表面采用光刻、反应离子刻蚀等工艺刻蚀平均分布的图形,图形可以为正方形、长方形、菱形或六边形等。图形深度约1-2μm,图形尺寸3-20μm,图形间隔3-20μm。最后步骤5)中在图形化后的P型4H-SiC外延层上生长3C-SiC外延层。
实施例4
一种含超级结的3C-SiC外延结构制备方法,包括以下步骤:
1)N型4H-SiC外延层生长:在外延炉生长5~20μm,掺杂浓度3×1014cm-3~9×1016cm-3N型4H-SiC外延层,取出,清洗;
2)深沟槽刻蚀:沿<11-20>晶向刻蚀深度5-15μm,沟槽侧壁倾角86~90°,底部宽度与台面顶部宽度一致,均为2~2.5μm,刻蚀完去掉掩膜;再一次清洗,烘干,送入外延炉中;
3)填充P型4H-SiC外延层:分别以50~150slm、50~100sccm、50~100sccm、1000~5000sccm和500~1000sccm的流量通入H2、含氯的硅源气体、碳源、HCl和Al掺杂剂,控制Cl/Si=20~50,掺杂浓度3×1014cm-3~9×1016cm-3,,填充速率在5~8μm/h,于1600~1700℃温度和400~600mbar压力下,填满沟道;
4)CMP抛光:使用标准工艺进行化学机械抛光,抛去台面顶部过生长的4H-SiC,得到上表面光滑的交替排列的p型和n形区域。
5)多次重复步骤(2)~步骤(4),直至完成200μm深沟槽的填充;
6)在抛光后的P型4H-SiC外延层上生长3C-SiC外延层:分别以50~200slm,100~500sccm、100~500sccm和50~100sccm的流量通入载气H2,含氯的硅源气体、碳源和N2掺杂剂,在温度1400~1550℃和压力50~600mbar条件下,生长厚度3~10μm,掺杂浓度3×1014cm-3~9×1016cm-3 3C-SiC外延层。
实施例5
其他同实施例4,只是在步骤2)和步骤3)之间还进行了续长本征4H-SiC缓冲层的步骤,具体为:关闭N2掺杂剂,使用生长N型4H-SiC外延层的条件生长10~100nm厚的本征SiC外延层做为缓冲层。
实施例6
其他同实施例4或5,只是在步骤5)和步骤6)之间还进行了P型4H-SiC外延层表面图形化的步骤,具体为:CMP抛光之后,上表面采用光刻、反应离子刻蚀等工艺刻蚀平均分布的图形,图形可以为正方形、长方形、菱形、六边形等。图形深度约1-2μm,图形尺寸3-20μm,图形间隔3-20μm。最后步骤6)中在图形化后的P型4H-SiC外延层上生长3C-SiC外延层。
比较例1
一种3C-SiC外延结构制备方法,直接在衬底上生长实施例1中的步骤(5),生长厚度为实施例1中的沟槽深度与3C-SiC外延层厚度之和。
将上述实施例1和比较例1中的外延结构按照常规方法制备成MOSFET器件,击穿电压VS导通电阻数据如图7所示。
上述参照实施例对一种含超级结的3C-SiC外延结构及其制备方法进行的详细描述,是说明性的而不是限定性的,可按照所限定范围列举出若干个实施例,因此在不脱离本发明总体构思下的变化和修改,应属本发明的保护范围之内。
Claims (10)
1.一种含超级结的3C-SiC外延结构的制备方法,其特征在于,所述制备方法包括以下步骤:
(1)在衬底上生长N型外延层;
(2)由N型外延层的表面向下刻蚀沟槽;
(3)向沟槽内填充P型外延层;
(4)CMP抛光,抛去在填充的过程中台面顶部过生长的外延层,直至得到表面光滑的N型、P型交替的外延层表面;
(5)在表面光滑的N型、P型交替的外延层表面上生长3C-SiC外延层。
2.根据权利要求1所述的制备方法,其特征在于,所述步骤(2)和步骤(3)之间还包括在沟槽内生长本征缓冲层的步骤,和/或,所述步骤(4)和步骤(5)之间还包括对表面光滑的N型、P型交替的外延层表面进行图形化处理的步骤。
3.根据权利要求1或2所述的制备方法,其特征在于,反复重复所述步骤(1)-步骤(4)继续在光滑的N型、P型交替的外延层表面上生长N型外延层、刻蚀沟槽并进行填充,并保持步骤(2)中沟槽刻蚀位置不变但后续刻蚀深度为整个N型外延层厚度,进一步实现15μm以上的深沟槽的刻蚀与填充。
4.根据权利要求1或2所述的制备方法,其特征在于,步骤(2)中,沟槽深度5-15μm,沟槽侧壁倾角86~90°,沟槽底部与顶部宽度一致,均为2~2.5μm。
5.根据权利要求1或2所述的制备方法,其特征在于,所述N型外延层的厚度为5~20μm;所述本征缓冲层的厚度为10~100nm;所述3C-SiC外延层的厚度为3~10μm。
6.根据权利要求1或2所述的制备方法,其特征在于,步骤(3)中,所述P型外延层的填充工艺为:向外延腔中通入H2、含氯的硅源气体、碳源、HCl和Al掺杂剂,在1600~1700℃、400~600mbar压力下进行沟槽填充,直至沟槽填满。
7.根据权利要求6所述的制备方法,其特征在于,所述H2、含氯的硅源气体、碳源、HCl和Al掺杂剂的流量分别为50~150slm、50~100sccm、50~100sccm、1000~5000sccm和500~1000sccm,并且控制Cl/Si=20~50。
8.根据权利要求2所述的制备方法,其特征在于,图形化处理时,图形深度为1-2μm,图形尺寸为3-20μm,图形间隔为3-20μm。
9.根据权利要求1或2所述的制备方法,其特征在于,步骤(5)中,所述3C-SiC外延层的生长工艺为:向外延腔中通入H2、含氯的硅源气体、碳源和N2掺杂剂,在1400~1550℃、50~600mbar压力下生长3C-SiC外延层;所述H2、含氯的硅源气体、碳源、和N2掺杂剂的流量为50~200slm,100~500sccm、100~500sccm和50~100sccm。
10.如权利要求1-9任意一项所述的制备方法制备的得到的含超级结的3C-SiC外延结构。
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