CN111373530A - 用于微电子装置的工业芯片级封装 - Google Patents

用于微电子装置的工业芯片级封装 Download PDF

Info

Publication number
CN111373530A
CN111373530A CN201880075335.6A CN201880075335A CN111373530A CN 111373530 A CN111373530 A CN 111373530A CN 201880075335 A CN201880075335 A CN 201880075335A CN 111373530 A CN111373530 A CN 111373530A
Authority
CN
China
Prior art keywords
pillar
layer
trench
head
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201880075335.6A
Other languages
English (en)
Inventor
S·K·科杜里
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of CN111373530A publication Critical patent/CN111373530A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/033—Manufacturing methods by local deposition of the material of the bonding area
    • H01L2224/0331—Manufacturing methods by local deposition of the material of the bonding area in liquid form
    • H01L2224/03318—Manufacturing methods by local deposition of the material of the bonding area in liquid form by dispensing droplets
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05006—Dual damascene structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05007—Structure comprising a core and a coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05025—Disposition the internal layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/05186—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05558—Shape in side view conformal layer on a patterned surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05562—On the entire exposed surface of the internal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1131—Manufacturing methods by local deposition of the material of the bump connector in liquid form
    • H01L2224/11312—Continuous flow, e.g. using a microsyringe, a pump, a nozzle or extrusion
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H01L2224/11472—Profile of the lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H01L2224/1191—Forming a passivation layer after forming the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13012—Shape in top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H01L2224/13017—Shape in side view being non uniform along the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H01L2224/13018—Shape in side view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13113—Bismuth [Bi] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/1356—Disposition
    • H01L2224/13562—On the entire exposed surface of the core
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/1357—Single coating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/13618—Zinc [Zn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13657—Cobalt [Co] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13664—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13666—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13669—Platinum [Pt] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/1368—Molybdenum [Mo] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13681—Tantalum [Ta] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13684—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401—Structure
    • H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/1605—Shape
    • H01L2224/16057—Shape in side view
    • H01L2224/16058—Shape in side view being non uniform along the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171—Disposition
    • H01L2224/17104—Disposition relative to the bonding areas, e.g. bond pads
    • H01L2224/17106—Disposition relative to the bonding areas, e.g. bond pads the bump connectors being bonded to at least one common bonding area
    • H01L2224/17107—Disposition relative to the bonding areas, e.g. bond pads the bump connectors being bonded to at least one common bonding area the bump connectors connecting two common bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/32227—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83193—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

一种微电子装置(100)包含具有输入/输出I/O端子(104)的管芯(102)和所述管芯(102)上的介电层(106)。所述微电子装置(100)包含导电支柱(110)，所述导电支柱电耦接到所述I/O端子(104)并且延伸穿过所述介电层(106)到达所述微电子装置(100)的外部。每个支柱(110)包含柱状物(112)和头部(114)，所述柱状物电耦接到所述I/O端子(104)之一，所述头部在所述柱状物(112)的与所述I/O端子(104)相对的一端处接触所述柱状物(112)。所述头部(114)在至少一个侧向方向上侧向地延伸超过所述柱状物(112)。

Description

用于微电子装置的工业芯片级封装
本公开总体上涉及微电子装置，并且更具体地涉及微电子装置中的芯片级封装。
背景技术
微电子装置的尺寸和成本正在不断减小。此外，微电子装置中的组件的密度正在增加。随着尺寸的减小，功率和电流密度通过输入/输出(I/O)结构(如凸块接合结构)而增大。这导致温度更高，并且冒着由于电迁移而导致的故障的风险。同时满足可靠性目标和成本目标对于封装设计来说一直具有挑战性。
发明内容
在所描述的实例中，一种微电子装置具有带有输入/输出(I/O)端子的管芯、所述管芯上的介电层以及电耦接到所述I/O端子并延伸穿过所述介电层到达所述微电子装置的外部的支柱。所述支柱是导电的。每个支柱包含柱状物和头部，所述柱状物电耦接到所述I/O端子之一，所述头部在所述柱状物的与所述I/O端子相对的一端处接触所述柱状物。所述头部在至少一个侧向方向上侧向地延伸超过所述柱状物。
附图说明
图1是示例微电子装置的横截面。
图2A到图2L是在示例形成方法的阶段中所描绘的微电子装置的横截面。
图3A到图3F是在另一种示例形成方法的阶段中所描绘的微电子装置的横截面。
图4A到图4F是在另一种示例形成方法的阶段中所描绘的微电子装置的横截面。
图5A到图5G是在另一种示例形成方法的阶段中所描绘的微电子装置的横截面。
具体实施方式
附图未按比例绘制。本说明书不受所展示的动作或事件顺序的限制，因为一些动作或事件可以以不同的顺序发生和/或与其它动作或事件同时发生。此外，一些所展示的动作或事件对于实施根据本说明书的方法是任选的。
微电子装置具有带有输入/输出(I/O)端子的管芯。管芯可以表现为例如集成电路、分立半导体装置或微机电系统(MEMS)装置。I/O端子可以包含例如接合焊盘、重新分布层(RDL)的接合区域或顶部互连层的接合区域。微电子装置包含管芯上的介电层。介电层可以包含例如有机聚合物、硅酮聚合物或无机介电材料。微电子装置进一步包含电耦接到I/O端子的支柱。支柱可以直接接触I/O端子或可以通过导电材料电耦接到I/O焊盘。支柱延伸穿过介电层到达微电子装置的外部。所述支柱是导电的。每个支柱包含电耦接到所述I/O端子中的至少一个I/O端子的至少一个柱状物。每个支柱进一步包含接触所述至少一个柱状物的头部。头部定位于所述支柱的与所述I/O端子相对的一端上。所述头部在至少一个侧向方向上侧向地延伸超过所述柱状物。介电层从管芯延伸到头部，并且侧向地围绕柱状物。在本说明书中，术语“侧向”和“侧向地”是指平行于I/O端子定位于其上的管芯的表面的平面的方向。
而且，在本说明书中，如顶部、之上和上方等术语不应被解释为限制结构或元件的位置或朝向，而应被用于提供结构或元件之间的空间关系。
在本说明书中，如果元件被称为连接到、耦接到、位于另一个元件上或与其接触，则所述元件可以直接连接到、直接耦接到、直接位于其它元件上或直接与其接触，或可以存在中间元件。而且，在本说明书中，如果元件被称为直接连接到、直接耦接到、直接位于另一个元件上或直接与其接触，则不存在其它有意安置的中间元件。用于描述元件之间关系的其它术语应该以类似的方式进行解释，例如，在……之间与直接在……之间、邻近与直接邻近等。
图1是示例微电子装置的横截面。微电子装置100包含管芯102。管芯102可以含有具有半导体衬底和互连区域的至少一个集成电路。可替代地，管芯102可以含有至少一个分立半导体装置，如功率晶体管。进一步地，管芯102可以含有MEMS装置，如加速度传感器。管芯102的其它表现形式也在本实例的范围内。管芯102包含I/O端子104。I/O端子104可以是电耦接到微电子装置的互连的接合焊盘。可替代地，I/O端子104可以是定位于微电子装置的互连的之上并电耦接到其的RDL的接合区域。进一步地，I/O端子104可以是微电子装置的有源区上接合(bond-over-active，BOAC)结构中的凸块焊盘。I/O端子104的其它表现形式也在本实例的范围内。I/O端子104的尺寸可以跨管芯102变化，或其尺寸可以是均匀的。
微电子装置100包含管芯102上的介电层106。介电层106可以包含例如有机聚合物，如环氧树脂、交联聚异戊二烯、聚酰亚胺或甲基丙烯酸酯。可替代地，介电层106可以包含硅酮聚合物。进一步地，介电层106可以包含无机介电材料，如二氧化硅、氮化硅、氮氧化硅或氧化铝。介电层106的厚度108可以为例如5微米到100微米。
微电子装置100包含电耦接到I/O端子104的支柱110。支柱110延伸穿过介电层106到达微电子装置100的外部。每个支柱110包含电耦接到I/O端子104之一的柱状物112。如图1所描绘的，柱状物112可以直接接触I/O端子104。可替代地，柱状物112可以通过导电材料(如用于电镀操作的晶种层)电耦接到I/O端子104。柱状物112是导电的。柱状物112可以具有例如由柱状物衬里侧向地围绕的铜芯，所述柱状物衬里减少铜从铜芯扩散到介电层106中。可替代地，柱状物112可以包含其它金属，如镍、铂、铝、钨或金，或其它导电材料，如石墨烯或碳纳米管。
支柱110进一步包含柱状物112上的头部114。柱状物112中的每个柱状物被头部114中的至少一个头部接触，并且头部114中的每个头部接触柱状物112中的至少一个柱状物。头部114可以直接接触柱状物112，或可以通过导电材料(如扩散阻挡层或晶种层的一部分)接触柱状物112。头部114的组成可以类似于或不同于柱状物112的组成。I/O端子104耦接到柱状物112的第一端，并且头部114接触柱状物112的第二端，所述第二端定位成与所述第一端相对。头部114中的每个头部在至少一个侧向方向上并且可能地在侧向方向上侧向地延伸超过由头部114接触的柱状物112。柱状物112和头部114可以具有任何配置，并且可以包含于2018年7月9日提交的共同转让的专利申请序列号US 16/030,371中所公开的任何材料，所述专利申请通过引用并入本文，但是所述专利申请不被承认是现有技术。
支柱110可以包含头部114上的阻挡层116。举例来说，阻挡层116可以包含镍、钯、铂、钛、钽、钴、钨、钼或锌。阻挡层116可以有利地减少头部114的氧化或污染。
支柱110可以进一步包含阻挡层116上或头部114上(在阻挡层116被省略的情况下)的焊料层118。焊料层118定位于微电子装置100的外部处。举例来说，焊料层118可以包含锡、银、铋或其它金属。阻挡层116可以有利地减少金属间化合物的形成。
介电层106从管芯102延伸到头部114，并且可以任选地进一步延伸到阻挡层116或焊料层118。支柱110从I/O端子104延伸穿过介电层106到达微电子装置100的外部。介电层106可以有利地为支柱110提供支撑，并且在随后的组装和封装操作期间为管芯102提供保护。
图2A到图2L是在示例形成方法的阶段中所描绘的微电子装置的横截面。参考图2A，微电子装置200包含管芯202。管芯202可以是半导体晶圆或MEMS衬底的一部分。半导体晶圆或MEMS衬底可以含有类似于管芯202的另外的管芯(在图2A中未示出)。可替代地，管芯202可以与其它管芯分离，例如作为将管芯202从半导体晶圆或MEMS衬底单切下来的结果。
管芯202包含I/O端子204。I/O端子204可以主要包含铝或铜，并且可以具有镍、钯、铂、金或其它金属的覆盖层或凸块下金属化(UBM)层。I/O端子204可以通过管芯202中的通孔220或其它导电结构电耦接到管芯202中的组件。
在管芯202上形成沟槽材料层222，所述沟槽材料层覆盖I/O端子204。沟槽材料层222可以包含光敏聚合物材料，例如，含有聚异戊二烯的光致抗蚀剂、光敏聚酰亚胺、如SU-8等光敏环氧树脂或含有甲基丙烯酸酯的光致抗蚀剂。沟槽材料层222可以包含有机树脂，如对电子束辐射敏感的聚甲基丙烯酸甲酯(PMMA)。沟槽材料层222可以例如通过旋涂工艺或通过作为干膜施加而形成。
沟槽材料层222暴露于图案化辐射224，如来自光刻工具的紫外线(UV)辐射。图案化辐射224具有与I/O端子204的空间分布对齐的空间分布。在本实例的一个版本中，其中沟槽材料层222中的光敏聚合物材料具有负色调，图案化辐射224可以暴露随后形成的柱状物沟槽子层226的区域中的沟槽材料层222，如图2B所示。返回参考图2A，如图2A所描绘的，图案化辐射224可以与I/O端子204之上的柱状物沟槽228的区域阻隔。在本实例的替代性版本中，其中沟槽材料层222中的光敏聚合物材料具有正色调，图案化辐射224可以暴露柱状物沟槽228的区域中的沟槽材料层222，并且可以与随后形成的柱状物沟槽子层226的区域阻隔。
参考图2B，显影操作从图2A的沟槽材料层222去除柱状物沟槽228中的材料，以形成柱状物沟槽子层226。可以加热柱状物沟槽子层226以去除挥发性材料(如溶剂)，并且任选地增加柱状物沟槽子层226中的聚合物分子之间的交联，以提供更高的耐久性。柱状物沟槽子层226中的柱状物沟槽228暴露I/O端子204。
可替代地，可以通过激光烧蚀工艺，通过从图2A的沟槽材料层222中去除材料来形成柱状物沟槽子层226。使用激光烧蚀工艺使得能够由更宽范围的材料(包含不感光的材料)形成柱状物沟槽子层226，这可以有利地降低微电子装置200的制造成本。
参考图2C，在柱状物沟槽子层226上形成柱状物衬里230，所述柱状物衬里延伸到柱状物沟槽228中并接触I/O端子204。柱状物衬里230可以包含在柱状物沟槽228中直接接触柱状物沟槽子层226的粘合子层。粘合子层可以包含对柱状物沟槽子层226具有良好粘附性的金属，如钛或钛钨，并且可以通过溅射工艺形成。柱状物衬里230还可以包含有效地减少铜扩散到柱状物沟槽子层226的阻挡子层。阻挡子层可以包含例如氮化钛或氮化钽，并且可以通过反应性溅射工艺或原子层沉积(ALD)工艺形成。柱状物衬里230可以包含为随后的电镀操作提供合适的导电表面的晶种子层。晶种子层可以包含例如镍或铜，并且可以通过溅射工艺或蒸发工艺形成。
参考图2D，使用柱状物镀槽232的柱状物电镀工艺在柱状物衬里230上形成柱状物层234。柱状物层234填充柱状物沟槽228，并且在柱状物沟槽子层226之上邻近柱状物沟槽228延伸。柱状物层234可以主要包含铜，例如，大于90重量百分比的铜。柱状物层234还可以包含其它金属，如镍、银或金。柱状物镀槽232包含铜，例如呈硫酸铜的形式。柱状物镀槽232可以包含添加剂，如整平剂；抑制剂(suppressor)，有时称为抑制剂(inhibitor)；以及促进剂，有时称为增白剂，以在柱状物沟槽子层226之上邻近柱状物沟槽228提供所期望的低厚度的柱状物层234。
参考图2E，去除柱状物沟槽子层226之上邻近柱状物沟槽228的柱状物层234和柱状物衬里230，从而留下柱状物沟槽228中的柱状物衬里230和柱状物层234以提供柱状物212。柱状物衬里230绕每个柱状物212的侧向边界延伸。可以例如通过铜化学机械抛光(CMP)工艺去除柱状物沟槽子层226之上的柱状物层234，所述工艺使用抛光垫和去除铜的浆料。还可以通过铜CMP工艺或可以通过选择性湿法蚀刻工艺去除柱状物沟槽子层226之上的柱状物衬里230。如参考图2C到图2E所公开的用于形成柱状物212的方法有时被称为镶嵌工艺，具体地铜镶嵌工艺。
参考图2F，在柱状物沟槽子层226之上形成头部沟槽子层236。头部沟槽子层236具有暴露柱状物212的顶部的头部沟槽238。头部沟槽238中的每个头部沟槽在至少一个侧向方向上侧向地延伸超过由头部沟槽238暴露的柱状物212的顶部。头部沟槽子层236的组成可以类似于柱状物沟槽子层226的组成。此外，可以通过类似于参考图2A和图2B所公开的用于形成柱状物沟槽子层226的步骤的工艺顺序来形成头部沟槽子层236。
参考图2G，在头部沟槽子层236上形成头部衬里240，所述头部衬里延伸到头部沟槽238中并接触柱状物212。头部衬里240可以具有类似于柱状物衬里230的子层结构和组成的子层结构和组成，即包含钛或钛钨的粘合子层、包含氮化钛或氮化钽的阻挡子层以及包含镍或铜的晶种子层。头部衬里240的子层可以通过类似于用于形成柱状物衬里230的子层的工艺的工艺来形成，即溅射工艺、反应性溅射工艺或ALD工艺，以及溅射工艺或蒸发工艺。
使用头部镀槽242的头部电镀工艺在头部衬里240上形成头部层244。头部层244填充头部沟槽238，并且在头部沟槽子层236之上邻近头部沟槽238延伸。头部层244可以主要包含铜，并且可以具有类似于柱状物层234的组成。头部镀槽242包含铜，并且可以包含与图2D的柱状物镀槽232类似的添加剂，即，整平剂；抑制剂和促进剂，以在头部沟槽子层236之上邻近头部沟槽238提供所期望的低厚度的头部层244。
参考图2H，去除头部沟槽子层236之上邻近头部沟槽238的头部层244和头部衬里240，从而留下头部沟槽238中的头部衬里240和头部层244以提供头部214。头部衬里240绕每个头部214的侧向边界延伸。可以通过铜CMP工艺，任选地然后通过湿法蚀刻工艺从头部沟槽子层236之上去除头部层244和头部衬里240。头部214电连接到柱状物212。与头部214组合的柱状物212提供微电子装置200的支柱210。柱状物衬里230可以有利地减少铜从柱状物层234扩散到柱状物沟槽子层226中。类似地，头部衬里240可以有利地减少铜从头部层244扩散到头部沟槽子层236中。铜扩散到柱状物沟槽子层226中或扩散到头部沟槽子层236中可以降低微电子装置200的可靠性。
参考图2I，使用阻挡镀槽246的阻挡电镀工艺在头部214上形成阻挡层216。阻挡层216是支柱210的一部分。阻挡电镀工艺可以是无电镀工艺。阻挡层216可以具有如参考图1的阻挡层116所公开的组成。阻挡镀槽246可以包含呈硫酸镍形式的镍，并且可以包含呈金属盐形式的其它金属，以形成阻挡层216所期望的组成。阻挡层216是支柱210的组件。形成阻挡层216的其它方法也在本实例的范围内。
参考图2J，阻挡层216暴露于含有熔化的焊料的液体焊料源248中，所述熔化的焊料在阻挡层216上形成焊料层218。焊料层218是支柱210的一部分。液体焊料源248可以被泵送到微电子装置200上，以将阻挡层216暴露于熔化的焊料中。可替代地，可以将微电子装置200浸入液体焊料源248的熔化的焊料中，以将阻挡层216暴露于熔化的焊料中。焊料层218可以具有如参考图1的焊料层118所公开的组成，即，可以包含锡、银、铋或其它金属。焊料层218是支柱210的组件。
参考图2K，将微电子装置200组装到电路衬底250上。例如，电路衬底250可以表现为印刷电路板(PCB)或陶瓷布线衬底。电路衬底250具有定位于绝缘层254上的导电的焊盘252。焊盘252可以表现为电路衬底250的管芯焊盘、引线、迹线、布线或其它导电组件。焊盘252可以主要包含铜，并且可以任选地包含金、镍或其它金属，以提供用于焊点的合适表面。绝缘层254可以表现为玻璃纤维增强塑料(FRP)板、陶瓷衬底或其它绝缘介质。通过使焊料层218与焊盘252接触并且加热焊料层218以在支柱210与焊盘252之间形成焊料连接，将微电子装置200组装到电路衬底250上。
图2L描绘了被组装到电路衬底250上的微电子装置200。焊料层218提供支柱210与焊盘252之间的焊料连接。柱状物沟槽子层226和头部沟槽子层236的组合提供介电层206。柱状物沟槽子层226侧向地围绕柱状物212。头部沟槽子层236侧向地围绕头部214。本实例的介电层206从管芯202延伸到阻挡层216，侧向地围绕柱状物212和头部214。介电层206有利地为支柱210提供支撑，并且在组装到电路衬底250期间以及之后，在经过组装的微电子装置200的使用期间，为管芯202提供保护。
图3A到图3F是在另一种示例形成方法的阶段中所描绘的微电子装置的横截面。参考图3A，微电子装置300包含管芯302。管芯302可以是半导体晶圆或MEMS衬底的一部分，或可以是分立工件。管芯302包含I/O端子304。I/O端子304的组成可以类似于参考图2A的I/O端子204所公开的组成。管芯302可以包含将I/O端子304电耦接到管芯302中的一或多个组件的导电构件320。
在管芯302上形成介电层306。介电层306形成为具有暴露I/O端子304的柱状物沟槽328。介电层进一步形成为具有通向柱状物沟槽328的一或多个头部沟槽338。在本实例中，头部沟槽338通向两个柱状物沟槽328。
如图3A中所描绘的，可以通过第一增材工艺形成介电层306，所述第一增材工艺使用粘合剂喷射设备358在管芯302上安置介电材料356以形成介电层306的至少一部分。在本说明书中，增材工艺将介电材料356安置在所期望区域中，并且不将介电材料356安置在所期望区域之外，使得没有必要去除所安置的介电材料356的一部分，以产生介电层306的最终期望形状。增材工艺可以使得能够在没有光刻工艺的情况下形成介电层306，从而有利地降低制造成本和复杂性。适用于形成介电层306的增材工艺的实例包含粘合剂喷射、材料喷射、定向能量沉积、材料挤出、粉末床融化、薄片层压、还原光聚合(vatphotopolymerization)、直接激光沉积、静电沉积、激光烧结和光聚合挤出。
在本实例的一个版本中，介电层306可以包含有机聚合物，如环氧树脂、苯并环丁烯(BCB)、聚酰亚胺或丙烯酸。在另一个版本中，介电层306可以包含硅酮聚合物。在进一步的版本中，介电层306可以包含无机介电材料，如二氧化硅、氮化硅、氮化硼或氧化铝。可以将无机介电材料实施为经烧结的或具有聚合物粘合剂的无机材料的颗粒。
可以在安置介电材料356之后加热介电层306，以从介电层306中去除挥发性材料，或使介电层306中的聚合物材料交联。可以例如通过辐射加热工艺、通过热板加热工艺、通过炉加热工艺或通过强制空气对流加热工艺来加热介电层306。
参考图3B，在介电层306上形成支柱衬里360，所述支柱衬里延伸到头部沟槽338和柱状物沟槽328中并接触I/O端子304。支柱衬里360可以具有类似于参考图2C的柱状物衬里230所公开的层结构和组成的层结构和组成，即，包含钛或钛钨的粘合子层、包含氮化钛或氮化钽的阻挡子层以及包含镍或铜的晶种子层。支柱衬里360可以通过参考柱状物衬里230公开的工艺中的任何工艺形成，即溅射工艺、反应性溅射工艺或ALD工艺，以及溅射工艺或蒸发工艺。
参考图3C，在支柱衬里360上形成支柱层362，所述支柱层填充柱状物沟槽328和头部沟槽338并在支柱衬里360上邻近头部沟槽338延伸。支柱层362可以通过电镀工艺形成。支柱层362可以主要包含铜，即，大于90重量百分比的铜。支柱层362可以任选地包含其它金属，如镍、银或金。
参考图3D，去除介电层306之上邻近头部沟槽338的的支柱层362和支柱衬里360，从而留下柱状物沟槽328和头部沟槽338中的支柱层362和支柱衬里360，以分别提供支柱310的柱状物312和头部314。可以例如通过CMP工艺、回蚀刻工艺或其组合，从在介电层306之上邻近头部沟槽338去除支柱层362和支柱衬里360。如参考图3B到图3D所公开的用于形成柱状物312和头部314的方法有时被称为双镶嵌工艺。与形成支柱310的其它方法相比，双镶嵌工艺可以提供降低的制造成本和复杂性。
参考图3E，在头部314上形成阻挡层316。如果在微电子装置300中存在另外的头部314，则在所述另外的头部上形成另外的阻挡层316。阻挡层316可以具有如参考图1的阻挡层116所公开的组成，即，可以包含镍、钯、铂、钛、钽、钴、钨、钼或锌，并且可以如参考图2I的阻挡层216公开的那样形成。阻挡层316是支柱310的组件，即，通过使用阻挡镀槽的无电镀工艺。
在阻挡层316上形成焊料层318。焊料层318可以通过第二增材工艺形成，例如使用材料挤出设备366在阻挡层316上安置焊膏364的材料挤出工艺。可以加热焊料层318以去除挥发性材料或降低焊料层318与阻挡层316之间的电阻。焊料层318是支柱310的组件。在另外的阻挡层316上形成另外的焊料层318，如果在微电子装置300中存在的话。
参考图3F，将微电子装置300组装到电路衬底350上。电路衬底350具有定位于绝缘层354上的导电的焊盘352。通过使焊料层318与焊盘352接触并且加热焊料层318以在支柱310与焊盘352之间形成焊料连接，将微电子装置300组装到电路衬底350上。介电层306可以为微电子装置300带来与参考图2L公开的那些优点类似的优点，即，可以在组装到电路衬底350期间以及之后，在经过组装的微电子装置300的使用期间，为支柱310提供支撑并且为管芯302提供保护。
图4A到图4F是在另一种示例形成方法的阶段中所描绘的微电子装置的横截面。参考图4A，微电子装置400包含管芯402。管芯402可以是含有另外的装置的工件的一部分，或可以是仅含有管芯402的分立工件。管芯402包含至少一个I/O端子404。I/O端子404的组成可以类似于参考图2A的I/O端子204所公开的组成，即，可以主要包含铝或铜，并且可以具有镍、钯、铂、金或其它金属的覆盖层或UBM层。
在管芯402上形成介电层406。介电层406形成为具有暴露I/O端子404的柱状物沟槽428。介电层进一步形成为具有通向柱状物沟槽428的头部沟槽438。介电层406可以具有暴露另外的I/O端子(未示出)的另外的柱状物沟槽(未示出)，并且可以具有通向另外的柱状物沟槽的另外的头部沟槽(也未示出)。如图4A所描绘的，介电层406的至少一部分可以通过第一增材工艺形成，如使用定向能量设备458在管芯402上安置介电材料456的定向能量工艺。定向能量工艺通过惰性气流以微粒或纳米颗粒的形式将介电材料456递送到管芯402，并且使用定向热能(例如来自聚焦激光束的定向热能)使介电材料456融化在管芯402上。介电层406可以包含参考图3A的介电层306公开的材料中的任何材料，即，可以包含有机聚合物(如环氧树脂、BCB、聚酰亚胺或丙烯酸)，可以包含硅酮聚合物，或可以包含无机介电材料(如二氧化硅、氮化硅、氮化硼或氧化铝)，所述无机介电材料任选地被实施为烧结的或具有聚合物粘合剂的无机材料的颗粒。
参考图4B，导电材料468安置在柱状物沟槽428和头部沟槽438中，以形成支柱导体470的至少一部分。柱状物沟槽428中的支柱导体470提供微电子装置400的支柱410的柱状物412。头部沟槽438中的支柱导体470提供支柱410的头部414。如图4B所描绘的，可以通过第二增材工艺(如使用静电沉积设备472的静电沉积工艺)在柱状物沟槽428和头部沟槽438中安置导电材料468。可以使用其它增材工艺来形成柱状物412和头部414。导电材料468可以包含金属纳米颗粒，如铜、金、银或铝纳米颗粒。导电材料468可以包含碳纳米管、石墨烯或其它石墨材料。在本实例的一个版本中，柱状物412和头部414可以通过使用不同导电材料的单独增材工艺形成。可以加热柱状物412或头部414以去除挥发性材料(如溶剂或载液)，以将导电材料468的导电颗粒融化在一起，或熔化导电材料468中的金属以在柱状物412或头部414中形成合金。导电材料468中的金属纳米颗粒可以在显著低于具有相同组成的块体金属的熔化温度的温度下融化或熔化，这可以有利地降低微电子装置400的热降解。
参考图4C，在第一接触区域474和第二接触区域476中，在头部414上形成阻挡层416。阻挡层416的组成可以类似于图1的阻挡层116所公开的组成。如图4C所描绘的，阻挡层416可以通过第三增材工艺形成，如使用电化学沉积设备478的电化学沉积工艺。阻挡层416可以通过其它方法形成，如溅射阻挡金属的薄膜，然后进行掩膜和蚀刻。阻挡层416是支柱410的组件。
参考图4D，在头部414上，邻近阻挡层416形成隔离层480。隔离层480可以防止与头部414的非预期电接触。隔离层480可以包含例如有机聚合物材料、硅酮聚合物材料、无机材料或其组合。隔离层480可以通过第三增材工艺形成，如使用具有单体源482a和紫外线激光器482b的光聚合挤出设备482的光聚合挤出工艺。隔离层480是支柱410的组件。
参考图4E，可以在阻挡层416上形成焊料层418。焊料层418可以通过第四增材工艺形成，例如使用材料挤出设备466在阻挡层416上安置焊膏464的材料挤出工艺。如参考图3E所公开的，可以加热焊料层418以去除挥发性材料或降低焊料层418与阻挡层416之间的电阻。焊料层418是支柱410的组件。
参考图4F，将微电子装置400组装到电路衬底450上。电路衬底450具有绝缘层454和位于绝缘层454上的导电的焊盘452a、452b和452c。微电子装置400通过以下装配到电路衬底450上：使焊料层418与焊盘452a和452c接触并且加热焊料层418以分别在第一接触区域474和第二接触区域476中在焊盘452a和452c与支柱410之间形成焊料连接。隔离层480可以防止焊盘452b与头部414之间的电接触。介电层406可以为微电子装置400带来与参考图2L所公开的那些优点类似的优点，即，可以在组装到电路衬底450期间以及之后，在经过组装的微电子装置400的使用期间，为支柱410提供支撑并且为管芯402提供保护。
图5A到图5G是在另一种示例形成方法的阶段中所描绘的微电子装置的横截面。参考图5A，微电子装置500包含管芯502。管芯502包含I/O端子504。在管芯502之上形成晶种层584。晶种层584是导电的，并与I/O端子504电接触。晶种层584可以包含直接在管芯502上具有钛、钨或镍的粘合子层。晶种层584可以包含具有铜或镍的电镀表面子层，以提供用于电镀工艺的合适表面。
在晶种层584上形成电镀掩模586。电镀掩模586具有暴露在I/O端子504之上的晶种层584的柱状物开口588。柱状物开口588可以逐渐变细，以便在每个柱状物开口588的位于I/O端子504近侧的一端处更窄，并且在每个柱状物开口588的位于I/O端子504远侧的相对端处更宽。
在本实例的一个版本中，电镀掩模586可以包含有机聚合物，并且可以通过在晶种层584上形成有机聚合物的掩模层来形成。可以通过使用扫描激光烧蚀设备590的激光烧蚀工艺在掩模层中形成柱状物开口588。在完成柱状物开口588的形成之后，其余的掩模层提供电镀掩模586。形成具有图5A的锥形配置的柱状物开口588可以有利地为激光烧蚀工艺提供另外的工艺宽容度。
在另一个版本中，电镀掩模586可以包含光致抗蚀剂、光敏聚酰亚胺或光敏硅酮聚合物，并且可以通过光刻操作形成。形成具有锥形配置的柱状物开口588可以有利地为光刻操作提供另外的工艺宽容度。可替代地，电镀掩模586可以通过增材工艺或丝网印刷工艺形成。
参考图5B，通过使用晶种层584的电镀操作，在柱状物开口588中形成支柱导体570。支柱导体570可以包含例如铜、镍、金、银、钯、铂或钨。图5B描绘了处于通过电镀操作完成的半途的支柱导体570。
参考图5C，继续进行电镀操作以完成支柱导体570。本实例的支柱导体570在柱状物开口588上方延伸并侧向地超过所述柱状物开口。柱状物开口588中的支柱导体570的部分提供微电子装置500的支柱510的柱状物512。电镀掩模586上方的支柱导体570的部分提供支柱510的头部514。
参考图5D，在头部514上形成阻挡层516。阻挡层516可以例如通过使用晶种层584的一或多个电镀工艺、一或多个无电镀工艺、通过增材工艺或通过溅射阻挡金属的薄膜，然后通过进行掩模和蚀刻来形成。阻挡层516可以具有如参考图1的阻挡层116所公开的组成。阻挡层516是支柱510的组件。
参考图5E，去除图5D的电镀掩模586。电镀掩模586可以例如通过使用氧气的灰化工艺、臭氧工艺、使用有机溶剂的湿法清洗工艺或其组合来去除。在去除电镀掩模586之后，在由柱状物512暴露的地方去除晶种层584，从而留下柱状物512和I/O端子504之间的晶种层584。晶种层584可以例如通过等离子体蚀刻工艺、湿法蚀刻工艺、电化学蚀刻工艺(有时称为反向电镀工艺)或其组合来去除。柱状物512和I/O端子504之间的晶种层584的部分是支柱510的组件。
参考图5F，在管芯502上形成介电层506。介电层506可以包含参考图1的介电层106所公开的介电材料中的任何介电材料。介电层506从管芯502延伸到头部514，并且可以任选地向上延伸到头部514的侧面的一半。介电层506可以提供参考本文其它实例的介电层106、206、306和406公开的优点，即，可以在组装期间以及之后，在经过组装的微电子装置500的使用期间为支柱510提供支撑并且为管芯502提供保护。
介电层506可以通过压模工艺形成，其中介电材料安置在支柱510之间的管芯502上，并且随后使用压模板592将其模制成所期望的配置。用于形成介电层506的其它方法，如旋涂工艺，然后是回蚀刻工艺，也在本实例的范围内。
参考图5G，将微电子装置500组装到电路衬底550上。电路衬底550具有绝缘层554和焊盘552。焊盘552是导电的。焊料预成型件594可以安置在焊盘552上。如图5G所示，通过使支柱510和焊盘552与焊料预成型件594接触来组装微电子装置500。加热焊料预成型件594以使焊料预成型件594回流，从而在支柱510与焊盘552之间形成焊点。
本文所公开的实例的各种特征可以在示例集成电路的其它表现形式中组合。例如，可以通过参考图2A到图2L、图3A到图3F、图4A到图4F或图5A到图5F公开的方法中的任何方法形成图1的支柱110。类似地，可以通过参考图2A到图2L、图3A到图3F、图4A到图4F或图5A到图5F公开的方法中的任何方法形成图1的介电层106。参考本文中用于形成介电层206、306、406或506的示例方法公开的步骤可以与参考本文中用于形成柱状物212、312、412或512的其它实例公开的步骤组合，并且可以进一步与参考本文中用于形成头部214、314、414或514的进一步的实例公开的步骤组合。
在权利要求的范围内，可以对所描述的实施例进行修改，并且其它实施例是可能的。

Claims (20)

1.一种微电子装置，其包括：
管芯；
输入/输出I/O端子，所述I/O端子位于所述管芯上；
介电层，所述介电层位于所述管芯上；以及
支柱，所述支柱电耦接到所述I/O端子，所述支柱是导电的，所述支柱从所述I/O端子延伸穿过所述介电层到达所述微电子装置的外部，其中所述支柱包含：
柱状物，所述柱状物电耦接到所述I/O端子，所述柱状物是导电的；以及
头部，所述头部在所述柱状物的与所述I/O端子相对的一端处电耦接到所述柱状物，所述头部是导电的，所述头部在至少一个侧向方向上侧向地延伸超过所述柱状物，其中所述介电层从所述管芯延伸到所述头部。
2.根据权利要求1所述的微电子装置，其中所述介电层包含光敏聚合物材料。
3.根据权利要求1所述的微电子装置，其中：所述介电层包含柱状物沟槽子层和头部沟槽子层，所述柱状物沟槽子层侧向地围绕所述柱状物，所述头部沟槽子层侧向地围绕所述头部；所述柱状物包含铜；并且所述头部包含铜。
4.根据权利要求3所述的微电子装置，其中所述柱状物包含柱状物衬里，所述柱状物衬里是导电的，所述柱状物衬里绕所述柱状物的侧向边界延伸，并且所述头部包含头部衬里，所述头部衬里是导电的，所述头部衬里绕所述头部的侧向边界延伸。
5.根据权利要求3所述的微电子装置，其中所述支柱包含支柱衬里，所述支柱衬里是导电的，所述支柱衬里绕所述柱状物的侧向边界并且绕所述头部的侧向边界延伸。
6.根据权利要求1所述的微电子装置，其中所述支柱包含所述头部上的阻挡层，所述阻挡层包含选自由以下组成的组的金属：镍、钯、铂、钛、钽、钴、钨、钼和锌。
7.根据权利要求1所述的微电子装置，其中所述支柱包含所述头部上的焊料层，所述焊料层定位于所述微电子装置的所述外部处。
8.根据权利要求1所述的微电子装置，其中所述支柱包含晶种层定位于所述柱状物与电耦接到所述柱状物的所述I/O端子之间的一部分，所述晶种层是导电的。
9.一种形成微电子装置的方法，所述方法包括：
获得具有输入/输出I/O端子的管芯；
在所述管芯上形成介电层；以及
形成支柱，所述支柱是导电的，使得所述支柱电耦接到所述I/O端子，并且使得所述支柱从所述I/O端子延伸穿过所述介电层到达所述微电子装置的外部，其中形成所述支柱包含：
形成所述支柱的柱状物，使得所述柱状物是导电的，并且使得所述柱状物电耦接到所述I/O端子；以及
形成头部，所述头部在所述柱状物的与所述I/O端子相对的一端处电耦接到所述柱状物，使得所述头部是导电的，使得所述头部在至少一个侧向方向上侧向地延伸超过所述柱状物，并且使得所述介电层从所述管芯延伸到所述头部。
10.根据权利要求9所述的方法，其中：
形成所述介电层包含在所述管芯上形成柱状物沟槽子层，所述柱状物沟槽子层具有暴露所述I/O端子的柱状物沟槽；并且
形成所述柱状物包含：
在所述柱状物沟槽子层上形成柱状物衬里，所述柱状物衬里延伸到所述柱状物沟槽中并接触所述I/O端子；
在所述柱状物衬里上形成柱状物层，使得所述柱状物层填充所述柱状物沟槽并在所述柱状物沟槽子层之上邻近所述柱状物沟槽延伸；以及
从所述柱状物沟槽子层之上邻近所述柱状物沟槽去除所述柱状物层和所述柱状物衬里。
11.根据权利要求10所述的方法，其中形成所述柱状物层包含用于在所述柱状物衬里上电镀金属的电镀工艺。
12.根据权利要求10所述的方法，其中形成所述柱状物沟槽子层包含：
在所述管芯上形成沟槽材料层，所述沟槽材料层包含光敏聚合物材料；
使所述沟槽材料层暴露于图案化辐射，所述图案化辐射具有与所述I/O端子的空间分布对齐的空间分布；以及
使所述沟槽材料层显影以形成所述柱状物沟槽。
13.根据权利要求10所述的方法，其中：
形成所述介电层包含在所述柱状物沟槽子层上形成头部沟槽子层，所述头部沟槽子层具有暴露所述柱状物的头部沟槽；并且
形成所述头部包含：
在所述头部沟槽子层上形成头部衬里，所述头部衬里延伸到所述头部沟槽中并接触所述柱状物；
在所述头部衬里上形成头部层，使得所述头部层填充所述头部沟槽并在所述头部沟槽子层之上邻近所述头部沟槽延伸；以及
从所述头部沟槽子层之上邻近所述头部沟槽去除所述头部层和所述头部衬里。
14.根据权利要求9所述的方法，其中：
所述介电层包含柱状物沟槽和头部沟槽，所述柱状物沟槽暴露所述I/O端子，所述头部沟槽通向所述柱状物沟槽；并且
形成所述支柱包含：
在所述介电层上形成支柱衬里，所述支柱衬里延伸到所述头部沟槽中、延伸到所述柱状物沟槽中并接触所述I/O端子；
在所述支柱衬里上形成支柱层，使得所述支柱层填充所述柱状物沟槽和所述头部沟槽并且在所述介电层之上邻近所述头部沟槽延伸；以及
从所述介电层之上邻近所述头部沟槽去除所述支柱层和所述支柱衬里。
15.根据权利要求9所述的方法，其中形成所述介电层包含增材工艺，所述增材工艺在所述管芯上安置介电材料以形成所述介电层的至少一部分。
16.根据权利要求9所述的方法，其中形成所述支柱包含：
形成晶种层，所述晶种层电耦接到所述I/O端子，所述晶种层是导电的；
在所述晶种层上形成电镀掩模，所述电镀掩模包含暴露所述晶种层的柱状物开口；
通过电镀工艺在所述柱状物开口中形成所述柱状物；
去除所述电镀掩模；以及
在由所述柱状物暴露的地方去除所述晶种层。
17.根据权利要求16所述的方法，其中形成所述电镀掩模包含使用激光烧蚀工艺形成所述柱状物开口。
18.根据权利要求9所述的方法，其中形成所述支柱包含增材工艺，所述增材工艺在所述管芯上安置导电材料以形成所述支柱的至少一部分。
19.根据权利要求9所述的方法，其中形成所述介电层包含在所述管芯上绕所述支柱安置介电材料，并且使用压模工艺来模制所述介电层。
20.根据权利要求9所述的方法，其中形成所述支柱进一步包含在所述头部上形成阻挡层，所述阻挡层包含选自由以下组成的组的金属：镍、钯、铂、钛、钽、钴、钨、钼和锌。
CN201880075335.6A 2017-10-05 2018-10-04 用于微电子装置的工业芯片级封装 Pending CN111373530A (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201762568340P 2017-10-05 2017-10-05
US62/568,340 2017-10-05
US16/042,661 US11749616B2 (en) 2017-10-05 2018-07-23 Industrial chip scale package for microelectronic device
US16/042,661 2018-07-23
PCT/US2018/054422 WO2019071012A1 (en) 2017-10-05 2018-10-04 INDUSTRIAL CHIP LIGHT ENCLOSURE FOR MICROELECTRONIC DEVICE

Publications (1)

Publication Number Publication Date
CN111373530A true CN111373530A (zh) 2020-07-03

Family

ID=65993743

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201880075335.6A Pending CN111373530A (zh) 2017-10-05 2018-10-04 用于微电子装置的工业芯片级封装

Country Status (3)

Country Link
US (2) US11749616B2 (zh)
CN (1) CN111373530A (zh)
WO (1) WO2019071012A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10636758B2 (en) * 2017-10-05 2020-04-28 Texas Instruments Incorporated Expanded head pillar for bump bonds
US11776908B2 (en) * 2021-04-15 2023-10-03 Micron Technology, Inc. Semiconductor die edge protection for semiconductor device assemblies and associated systems and methods
CN115458474B (zh) * 2022-11-10 2023-03-28 合肥晶合集成电路股份有限公司 半导体结构的制作方法以及半导体结构

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101128931A (zh) * 2005-02-25 2008-02-20 德塞拉股份有限公司 具有顺应性的微电子组件
CN101383292A (zh) * 2007-09-05 2009-03-11 台湾积体电路制造股份有限公司 芯片封装体、其导电柱的制造及修改其上载球层的方法
JP2011035296A (ja) * 2009-08-05 2011-02-17 Fujikura Ltd 半導体パッケージ及びその製造方法、並びに電子装置
CN103219309A (zh) * 2012-01-23 2013-07-24 台湾积体电路制造股份有限公司 多芯片扇出型封装及其形成方法
CN103681606A (zh) * 2012-08-29 2014-03-26 台湾积体电路制造股份有限公司 三维（3d）扇出封装机制
CN106409782A (zh) * 2015-07-31 2017-02-15 台湾积体电路制造股份有限公司 扇出式封装件及其形成方法

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5804881A (en) * 1995-11-27 1998-09-08 Motorola, Inc. Method and assembly for providing improved underchip encapsulation
US6114187A (en) 1997-01-11 2000-09-05 Microfab Technologies, Inc. Method for preparing a chip scale package and product produced by the method
US6573173B2 (en) * 1999-07-13 2003-06-03 Motorola, Inc. Method for forming a copper interconnect using a multi-platen chemical mechanical polishing (CMP) process
US6576551B1 (en) * 1999-12-20 2003-06-10 Taiwan Semiconductor Manufacturing Company Chemical mechanical polish planarizing method with pressure compensating layer
TWI313507B (en) 2002-10-25 2009-08-11 Megica Corporatio Method for assembling chips
US20040130034A1 (en) 2001-06-13 2004-07-08 Advanpack Solutions Pte Ltd. Method for forming a wafer level chip scale package
US6547124B2 (en) 2001-06-14 2003-04-15 Bae Systems Information And Electronic Systems Integration Inc. Method for forming a micro column grid array (CGA)
US20030047339A1 (en) 2001-09-12 2003-03-13 Lutz Michael A. Semiconductor device with compliant electrical terminals, apparatus including the semiconductor device, and methods for forming same
US7099293B2 (en) 2002-05-01 2006-08-29 Stmicroelectronics, Inc. Buffer-less de-skewing for symbol combination in a CDMA demodulator
US7898083B2 (en) * 2008-12-17 2011-03-01 Texas Instruments Incorporated Method for low stress flip-chip assembly of fine-pitch semiconductor devices
US7915080B2 (en) * 2008-12-19 2011-03-29 Texas Instruments Incorporated Bonding IC die to TSV wafers
TWI478303B (zh) 2010-09-27 2015-03-21 Advanced Semiconductor Eng 具有金屬柱之晶片及具有金屬柱之晶片之封裝結構
US9425136B2 (en) * 2012-04-17 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Conical-shaped or tier-shaped pillar connections
US9646923B2 (en) 2012-04-17 2017-05-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices
US9111817B2 (en) * 2012-09-18 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structure and method of forming same
JP2015135869A (ja) 2014-01-16 2015-07-27 株式会社テラプローブ 半導体装置、及び半導体装置の製造方法
US9633965B2 (en) * 2014-08-08 2017-04-25 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method of the same
TWI570816B (zh) * 2014-09-26 2017-02-11 矽品精密工業股份有限公司 封裝結構及其製法
US10209466B2 (en) * 2016-04-02 2019-02-19 Intel IP Corporation Integrated circuit packages including an optical redistribution layer
CN106409728B (zh) 2016-10-31 2019-02-19 北京北方华创微电子装备有限公司 一种密封结构及一种半导体设备

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101128931A (zh) * 2005-02-25 2008-02-20 德塞拉股份有限公司 具有顺应性的微电子组件
CN101383292A (zh) * 2007-09-05 2009-03-11 台湾积体电路制造股份有限公司 芯片封装体、其导电柱的制造及修改其上载球层的方法
JP2011035296A (ja) * 2009-08-05 2011-02-17 Fujikura Ltd 半導体パッケージ及びその製造方法、並びに電子装置
CN103219309A (zh) * 2012-01-23 2013-07-24 台湾积体电路制造股份有限公司 多芯片扇出型封装及其形成方法
CN103681606A (zh) * 2012-08-29 2014-03-26 台湾积体电路制造股份有限公司 三维（3d）扇出封装机制
CN106409782A (zh) * 2015-07-31 2017-02-15 台湾积体电路制造股份有限公司 扇出式封装件及其形成方法

Also Published As

Publication number Publication date
US11749616B2 (en) 2023-09-05
US20190109093A1 (en) 2019-04-11
US20240162163A1 (en) 2024-05-16
WO2019071012A1 (en) 2019-04-11

Similar Documents

Publication Publication Date Title
US6852621B2 (en) Semiconductor device and manufacturing method therefor, circuit board, and electronic equipment
US7214615B2 (en) Method of manufacturing semiconductor device, semiconductor device, circuit substrate and electronic apparatus
JP4016984B2 (ja) 半導体装置、半導体装置の製造方法、回路基板、及び電子機器
TWI424512B (zh) 使用無遮罩背側校直於傳導通道之製造半導體元件之方法
US20200258856A1 (en) Expanded head pillar for bump bonds
TWI587462B (zh) 半導體裝置的製造方法
US20240162163A1 (en) Industrial chip scale package for microelectronic device
TW201631719A (zh) 半導體裝置及製造方法
TW201724460A (zh) 半導體元件以及製造方法
WO2013192054A1 (en) Semiconductor chip with expansive underbump metallization structures
JP2009147220A (ja) 半導体装置の製造方法及び半導体装置
CN109979903B (zh) 具有凸块结构的半导体器件和制造半导体器件的方法
JP2016512929A (ja) 相互接続部材をプレコーティングすることを含むフリップチップ組立方法
JP2005535122A (ja) 感温電気デバイスの高密度相互接続
JP6996823B2 (ja) 自己整列はんだバンプを備えた基板貫通ビアを含む半導体デバイスを製造する方法および半導体構造
JP3568869B2 (ja) 半導体集積回路装置及びその製造方法
TWI579996B (zh) 半導體元件及其製造方法
JP2005150578A (ja) 半導体装置及びその製造方法
TWI787075B (zh) 半導體封裝結構及其形成方法
US20240006371A1 (en) Semiconductor device interconnect structure
KR101671973B1 (ko) 다층 금속 범프 구조체 및 그 제조방법
JP7335036B2 (ja) 半導体パッケージの製造方法
KR20090048879A (ko) 반도체 패키지의 재배선 패턴 형성방법
JP2011108970A (ja) 半導体装置の製造方法
JP2011082409A (ja) 半導体装置および半導体装置の製造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination