CN111341753A - 一种埋入式封装器件 - Google Patents

一种埋入式封装器件 Download PDF

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CN111341753A
CN111341753A CN202010121636.7A CN202010121636A CN111341753A CN 111341753 A CN111341753 A CN 111341753A CN 202010121636 A CN202010121636 A CN 202010121636A CN 111341753 A CN111341753 A CN 111341753A
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bearing surface
chip
packaged device
substrate
groove
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李骏
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Nantong Fujitsu Microelectronics Co Ltd
Tongfu Microelectronics Co Ltd
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    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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Abstract

本申请公开了一种埋入式封装器件,包括:基板,具有电互连结构,包括相背设置的承载面和非承载面,所述承载面具有凹槽;至少一个芯片,倒装固定于所述凹槽内,且所述芯片与所述电互连结构电连接;焊料层,位于所述芯片远离所述非承载面一侧;散热片,位于所述焊料层上,且覆盖所述凹槽。通过上述方式,本申请能够有效降低封装器件的厚度。

Description

一种埋入式封装器件
技术领域
本申请涉及半导体领域,特别是涉及一种埋入式封装器件。
背景技术
随着集成电路技术的不断发展,电子产品越来越向小型化、智能化、高性能和可靠性方向发展。其中,FCBGA(倒装芯片焊球阵列)封装形式具有较高的布线密度,因此应用范围较为广泛。但是FCBGA封装形式的封装器件存在厚度较厚的问题。
发明内容
本申请主要解决的技术问题是提供一种埋入式封装器件,能够有效降低封装器件的厚度。
为解决上述技术问题,本申请采用的一个技术方案是:提供一种埋入式封装器件,所述封装器件包括:基板,具有电互连结构,包括相背设置的承载面和非承载面,所述承载面具有凹槽;至少一个芯片,倒装固定于所述凹槽内,且所述芯片与所述电互连结构电连接;焊料层,位于所述芯片远离所述非承载面一侧;散热片,位于所述焊料层上,且覆盖所述凹槽。
其中,所述芯片包括相背设置的功能面和非功能面,所述功能面朝向所述凹槽的底部设置,且所述功能面上的多个焊盘与对应位置处的从所述底部外露的所述电互连结构固定连接;其中,所述芯片的所述功能面与所述底部之间设置有围坝,所有所述焊盘位于所述围坝围设的区域内。
其中,所述围坝为底填胶,所述底填胶覆盖所述焊盘。
其中,所述散热片为平板状,所述散热片与至少部分所述承载面接触。
其中,所述散热片为门型结构,包括平板部以及自所述平板部的两端分别非平行延伸的两个延伸部,所述平板部覆盖所述承载面,所述延伸部分别与相邻的所述基板的至少部分外侧面接触。
其中,所述基板的所述外侧面上设置有凸起,所述延伸部面向所述非承载面的端侧与所述凸起接触。
其中,还包括:粘结层,设置于所述基板与所述散热片接触的至少部分区域上。
其中,还包括:被动元件,设置于所述基板内部,且与所述电互连结构电连接。
其中,所述被动元件设置于所述基板与所述凹槽相邻的侧壁内部。
其中,还包括:焊球,设置于所述非承载面上,所述焊球与所述电互连结构从所述非承载面露出的部分电连接。
区别于现有技术,本申请的有益效果是,本申请所采用的基板的承载面具有凹槽,芯片倒装固定于该凹槽内,芯片与基板所形成的总厚度与原先基板厚度差不多,从而可以有效降低最终形成的埋入式封装器件的厚度。
此外,焊料层在回流处理时,焊料层中的某些导电物质(例如,铟In等)会挥发、冷凝。而本申请中被动元件采用非外露的形式设置于基板内部,因此挥发冷凝的某些导电物质并不会附着于被动元件上,从而有效降低被动元件短路的概率,提高埋入式封装器件的可靠性。
附图说明
为了更清楚地说明本申请实施例中的技术方案,下面将对实施例描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本申请的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。其中:
图1为本申请埋入式封装方法一实施方式的流程示意图;
图2a为图1中步骤S101对应的一实施方式的结构示意图;
图2b为图1中步骤S102对应的一实施方式的结构示意图;
图2c为图1中步骤S103对应的一实施方式的结构示意图;
图3为图1中步骤S102对应的一实施方式的流程示意图;
图4为本申请埋入式封装器件一实施方式的结构示意图;
图5为本申请埋入式封装器件另一实施方式的结构示意图;
图6为本申请埋入式封装器件另一实施方式的结构示意图。
具体实施方式
下面将结合本申请实施例中的附图,对本申请实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本申请一部分实施例,而不是全部实施例。基于本申请中的实施例,本领域普通技术人员在没有做出创造性的劳动前提下所获得的所有其他实施例,都属于本申请保护的范围。
请参阅图1,图1为本申请埋入式封装方法一实施方式的流程示意图,该封装方法包括:
S101:提供具有电互连结构100的基板10,基板10包括相背设置的承载面102和非承载面104,承载面102具有凹槽106。
具体地,请参阅图2a,图2a为图1中步骤S101对应的一实施方式的结构示意图。该基板10上设置的凹槽106的个数可以为一个或者多个。基板10可由多层板层叠设置形成,凹槽106可以通过控制每层板的形状形成,即在多层板层叠设置时凹槽106即可同步形成。当然,也可在多层板层叠设置之后,挖除部分区域以形成该凹槽106。
此外,上述基板10内的电互连结构100可以由金属布线层、导电孔等导电结构形成,且该电互连结构100包括从承载面102和非承载面104露出的部分。
S102:将至少一个芯片12倒装固定于凹槽106内,且芯片12与基板10的电互连结构100电连接。
具体地,请参阅图2b,图2b为图1中步骤S102对应的一实施方式的结构示意图。在本实施例中,上述芯片12倒装固定于凹槽106之后,其非功能面126略低于凹槽106两侧的承载面102,即凹槽106的深度大于芯片12的非功能面126至凹槽106的底部1060之间的距离。请参阅图3,图3为图1中步骤S102对应的一实施方式的流程示意图,上述步骤S102具体包括:
S201:将至少一个芯片12的功能面120朝向凹槽106的底部1060。
具体地,芯片12的功能面120上可以设置有多个焊盘122,在上述步骤S201之前,本申请所提供的封装方法还包括:在芯片12的功能面120上形成第一再布线层(图未示),第一再布线层与焊盘122电连接,第一再布线层的结构可参见现有技术中任意一种,在此不再赘述;在第一再布线层上形成导电柱124,导电柱124与焊盘122一一对应。
S202:将功能面120上的多个焊盘122与对应位置处的从底部1060外露的电互连结构100固定连接。
具体地,在本实施例中,可以在上述芯片12上形成的导电柱124上植焊球,然后利用焊球和回流工艺使得导电柱124与对应位置处的电互连结构100固定连接,进而使得焊盘122与电互连结构100电连接。
S203:在功能面120与底部1060之间形成围坝14,所有焊盘122位于围坝14围设的区域内。
具体地,在本实施例中,围坝14可以进一步固定芯片12的位置,降低芯片12在后续过程中发生倾斜的概率,且该围坝14可以保护其内部的焊盘122对应的电路结构,降低其内部的焊盘122对应的电路结构发生短路的概率。
优选地,上述围坝14为底填胶,其可以通过成熟的底填工艺形成,底填胶覆盖焊盘122。当然,在其他实施例中,围坝14也可为环形,仅设置于功能面120的边缘与底部1060之间,并不覆盖焊盘122。此外,在非承载面104至承载面102方向上,围坝14的竖截面为梯形,该结构形式的围坝14较为稳固。
S103:在芯片12远离非承载面104一侧形成焊料层16。
具体地,如图2c所示,图2c为图1中步骤S103对应的一实施方式的结构示意图。上述芯片12远离非承载面104一侧(即芯片12的非功能面126),采用涂覆的方式形成焊料层16,焊料层16中可以包含导电物质,例如,铟In等。此时,焊料层16远离非承载面104一侧可以高于凹槽106两侧的承载面102,即焊料层16远离非承载面104一侧与底部1060之间的距离大于凹槽106的深度。该设计方式可以使得后续散热片18与芯片12之间固定较好。
S104:将散热片18固定设置于焊料层16上,且散热片18覆盖凹槽106。
具体地,在一个实施方式中,请参阅图4,图4为本申请埋入式封装器件一实施方式的结构示意图。上述散热片18的材质为金属,且可以为平板状,散热片18与至少部分承载面102接触。例如,散热片18和承载面102在非承载面104上的正投影完全重合。上述结构的散热片18结构较为简单,易于获得。
在又一个实施方式中,请参阅图5,图5为本申请埋入式封装器件另一实施方式的结构示意图。该散热片18a的材质为金属,其可为门型结构,包括平板部180a以及自平板部180a的两端分别非平行延伸(例如,垂直延伸等)的两个延伸部182a,平板部180a覆盖承载面102,延伸部182a分别与相邻的基板10的至少部分外侧面108接触。上述结构的散热片18a可以增大其与基板10的接触面积,进而增加散热。
在又一个实施方式中,请参阅图6,图6为本申请埋入式封装器件另一实施方式的结构示意图。该散热片18b为门型结构,包括平板部180b以及自平板部180b的两端分别非平行延伸(例如,垂直延伸等)的两个延伸部182b,平板部180b覆盖承载面102b,延伸部182b分别与相邻的基板10b的至少部分外侧面108b接触。且基板10b的外侧面108b上设置有凸起1080b,延伸部182b面向非承载面104b的端侧与凸起1080b接触。一方面,上述结构的散热片18b可以增大其与基板10b的接触面积,进而增加散热。另一方面,上述凸起1080b的设置可以更好地限制散热片18b的位置。
进一步,为了更好地固定散热片18的位置,上述步骤S104之前,本申请所提供的封装方法还包括:在基板10与散热片18接触的至少部分区域上设置粘结层(图未示)。
此外,请再次参阅图4,在本实施例中,埋入式封装器件中除了芯片12外,还可包括其他被动元件11,该被动元件11可以为电容、电阻等。为了降低被动元件11短路的概率,在上述进行步骤S101时包括:在基板10内部设置非外露的被动元件11,被动元件11与电互连结构100电连接。上述设计方式可以使得焊料层16在回流处理时,焊料层16中的某些挥发冷凝的导电物质(例如,铟In等)不会附着于被动元件11上,从而降低被动元件11短路的概率,提高埋入式封装器件的可靠性。
优选地,被动元件11可以设置于基板10与凹槽106相邻的侧壁(未标示)内部。
另外,为了将基板10的信号引出,请继续参阅图4,上述步骤S104之后,本申请所提供的封装方法还包括:在非承载面104上形成焊球13,焊球13与电互连结构100从非承载面104露出的部分电连接。
总而言之,本申请所采用的基板10的承载面102具有凹槽106,芯片12倒装固定于该凹槽106内,芯片12与基板10所形成的总厚度与原先基板10厚度差不多,从而可以有效降低最终形成的埋入式封装器件的厚度。
下面从结构的角度对采用上述埋入式封装方法形成的埋入式封装器件作进一步说明。请再次参阅图4,本申请所提供的封装器件包括:
基板10,具有电互连结构100,包括相背设置的承载面102和非承载面104,承载面102具有凹槽106。在本实施中,电互连结构100可以包括导电孔、金属布线层中至少一种,且电互连结构100包括从承载面102和非承载面104露出的部分。
至少一个芯片12,倒装固定于凹槽106内,且芯片12与电互连结构100电连接。在本实施例中,芯片12包括相背设置的功能面120和非功能面126,功能面120朝向凹槽106的底部1060设置,且功能面120上的多个焊盘122与对应位置处的从底部1060外露的电互连结构100固定连接;其中,芯片12的功能面120与底部1060之间设置有围坝14,所有焊盘122位于围坝14围设的区域内。优选地,上述围坝14为底填胶,底填胶覆盖焊盘122。当然,在其他实施例中,围坝14也可不覆盖焊盘122,仅位于功能面120的边缘与底部1060之间。
焊料层16,位于芯片12远离非承载面126一侧。焊料层16中可以包含导电物质,例如铟In等。
散热片18,位于焊料层16上,且覆盖凹槽106。
在一个实施方式中,散热片18的材质为金属,其可为平板状,散热片18与至少部分承载面102接触。例如,如图4所示,散热片18和承载面102在非承载面104上的正投影完全重合。上述结构的散热片18结构较为简单,易于获得。
在又一个实施方式中,请再次参阅图5,该散热片18a的材质为金属,其可为门型结构,包括平板部180a以及自平板部180a的两端分别非平行延伸(例如,垂直延伸等)的两个延伸部182a,平板部180a覆盖承载面102,延伸部182a分别与相邻的基板10的至少部分外侧面108接触。上述结构的散热片18a可以增大其与基板10的接触面积,进而增加散热。
在又一个实施方式中,请再次参阅图6,该散热片18b为门型结构,包括平板部180b以及自平板部180b的两端分别非平行延伸(例如,垂直延伸等)的两个延伸部182b,平板部180b覆盖承载面102b,延伸部182b分别与相邻的基板10b的至少部分外侧面108b接触。且基板10b的外侧面108b上设置有凸起1080b,延伸部182b面向非承载面104b的端侧与凸起1080b接触。一方面,上述结构的散热片18b可以增大其与基板10b的接触面积,进而增加散热。另一方面,上述凸起1080b的设置可以更好地限制散热片18b的位置。
进一步,为了更好地固定散热片18的位置,本申请所提供的封装器件还包括:粘结层(图未示),设置于基板10与散热片18接触的至少部分区域上。
此外,请再次参阅图4,在本实施例中,埋入式封装器件中除了芯片12外,还可包括其他被动元件11,该被动元件11可以为电容、电阻等。为了降低被动元件11短路的概率,被动元件11设置于基板10内部,被动元件11与电互连结构100电连接。上述设计方式可以使得焊料层16在回流处理时,焊料层中的某些挥发冷凝的导电物质(例如,铟In等)不会附着于被动元件11上,从而降低被动元件11短路的概率,提高埋入式封装器件的可靠性。
优选地,被动元件11可以设置于基板10与凹槽106相邻的侧壁(未标示)内部。
另外,为了将基板10的信号引出,请继续参阅图4,本申请所提供的埋入式封装器件还包括焊球13,设置于非承载面104上,焊球13与电互连结构100从非承载面104露出的部分电连接。

Claims (10)

1.一种埋入式封装器件,其特征在于,所述封装器件包括:
基板,具有电互连结构,包括相背设置的承载面和非承载面,所述承载面具有凹槽;
至少一个芯片,倒装固定于所述凹槽内,且所述芯片与所述电互连结构电连接;
焊料层,位于所述芯片远离所述非承载面一侧;
散热片,位于所述焊料层上,且覆盖所述凹槽。
2.根据权利要求1所述的封装器件,其特征在于,
所述芯片包括相背设置的功能面和非功能面,所述功能面朝向所述凹槽的底部设置,且所述功能面上的多个焊盘与对应位置处的从所述底部外露的所述电互连结构固定连接;
其中,所述芯片的所述功能面与所述底部之间设置有围坝,所有所述焊盘位于所述围坝围设的区域内。
3.根据权利要求2所述的封装器件,其特征在于,
所述围坝为底填胶,所述底填胶覆盖所述焊盘。
4.根据权利要求1所述的封装器件,其特征在于,
所述散热片为平板状,所述散热片与至少部分所述承载面接触。
5.根据权利要求1所述的封装器件,其特征在于,
所述散热片为门型结构,包括平板部以及自所述平板部的两端分别非平行延伸的两个延伸部,所述平板部覆盖所述承载面,所述延伸部分别与相邻的所述基板的至少部分外侧面接触。
6.根据权利要求5所述的封装器件,其特征在于,
所述基板的所述外侧面上设置有凸起,所述延伸部面向所述非承载面的端侧与所述凸起接触。
7.根据权利要求4-6任一项所述的封装器件,其特征在于,还包括:
粘结层,设置于所述基板与所述散热片接触的至少部分区域上。
8.根据权利要求1所述的封装器件,其特征在于,还包括:被动元件,设置于所述基板内部,且与所述电互连结构电连接。
9.根据权利要求8所述的封装器件,其特征在于,
所述被动元件设置于所述基板与所述凹槽相邻的侧壁内部。
10.根据权利要求1所述的封装器件,其特征在于,还包括:
焊球,设置于所述非承载面上,所述焊球与所述电互连结构从所述非承载面露出的部分电连接。
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