CN1112729C - 电子器件中的电连接结构和导体表面材料的形成方法 - Google Patents

电子器件中的电连接结构和导体表面材料的形成方法 Download PDF

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CN1112729C
CN1112729C CN93104636A CN93104636A CN1112729C CN 1112729 C CN1112729 C CN 1112729C CN 93104636 A CN93104636 A CN 93104636A CN 93104636 A CN93104636 A CN 93104636A CN 1112729 C CN1112729 C CN 1112729C
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layer
copper
conductor
surfacing
silicon
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CN1082770A (zh
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迈克尔·J·布雷迪
柯蒂斯·E·法雷尔
宋·K·坎
杰弗里·R·马里诺
唐纳德·J·米卡莱森
保罗·A·莫斯科维茨
尤金·J·奥沙利文
特雷塞·R·奥图尔
桑普阿西·帕鲁索塔曼
谢尔登·C·里利
乔治·F·沃克
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International Business Machines Corp
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Abstract

在电子器件中将含硅和锗的材料用作导体的表面。焊料可以非熔化地焊接，而且导线可以焊接在这些表面上。在集成电路芯片的封装中，这些材料可以用作引线框架的表面涂层。这些材料可以用移画印花工艺(decal)转印在导体的表面或者用非电的或电解的方法设置在导体的表面上。

Description

电子器件中的电连接结构和导体表面材料的形成方法
1992年1月6日在美国申请的尚未批准的题为“在室温下可以制造的铜一半导体化合物”、申请号为07/818,027的专利申请描述了将衬底保持在室温条件下，在硅(Si)或锗(Ge)的单晶半导体基片的表面上淀积铜膜。已经发现，这些材料在超过一个连续的时间周期后，自身将发生反应，结果形成铜的硅化物或铜的亚锗酸盐(ger-manide)的化合物界面。这种方法适用于制造集成电路的内部互连的金属化。但是在现有的超大规模集成电路(VLSI)的工艺方面，通常使用大约150℃的最少的合乎需要的温度参数条件，在大约20分钟内用加热的方法加速完成上述金属化。和铜总是在硅中扩散这种本领域的看法相反，已发现这样获得的界面结显示出优越的(接近理想状态)电流/电压特性，并被用作一种高温稳定的硅的欧姆/肖特基接触，或用作铜扩散阻挡层。所附的实施例包括在硅衬底上形成一锗层，在锗层之上形成一铜层；在硅基片上形成SixGe1-x层，在SixGe1-x层之上形成一铜层；以及利用钨(W)这样的耐熔金属作中间层。各种其他的超大规模集成电路的实施例也被公开了。
本发明涉及的电子器件中，其导电体具有包含硅和锗的材料的表面。具体地说，将引线焊接在这些表面上，而焊料未完全熔化地与这些表面接合。具体地是将含有硅和锗的材料用作许多金属层的中间层，并用作金属层和介质层间的中间层。更具体地说，本发明所用的材料是电学淀积和移画印花法转印(decal transferred)形成的。最特别的是本发明的材料是硅和锗的共价化合物。
金属铜具有很好的导电性能。因此，现在对在电子器件将来的封装中发展铜用作内部连接的金属化有着广泛的兴趣。超大规模集成电路(VLSI)的电路密度的增加，使得对芯片和与之电学互连的封装基片上的导电体有着愈来愈严格的要求。电路密度的增加对应着导体尺寸的减小，这就导致较高的阻抗和电流密度，从而增加信号的损耗并加速了电子器件和封装的导体的电迁移损坏。这个问题促进了高导电率的、基于金或铜的冶金学(metallurgics)的发展。增加电路密度需要多个内部互相连接的层，这需要完全的平面结构，这种结构是由复杂的工艺过程完成的。
需要新的材料来通过低的介电常数降低寄生电容，同时也降低残余应力，尽管对平面化很敏感。这些改进的材料和工艺与现有的导电材料不具有化学相容性，现有的导电材料能够加速导体上的腐蚀，特别是如果铜用作导电体时。这就使得随着尺寸的缩小，在施加保护层以防止腐蚀时要保持高的导电特性变得愈加困难，这是由于覆盖层占据了空间，从而减小了高导电率的铜所能使用的空间。
金属是一种常用的抗腐蚀材料。通常用金涂覆半导体芯片和封装基片上的导电体以避免腐蚀。然而金是一种昂贵的材料，若要降低电子器件和基片的成本，必须用低电阻率和高抗腐蚀能力的其他材料来替代。例如，引线框架具有多个用作半导体芯片压焊片和封装基片压焊片之间的内部互连的导电引线，这些引线框架通常由有金的镀层的铜构成。此外，申请号为07/583,621、申请日为1990年9月14日的美国申请(题目为“可弯曲的带状探针”)描述了测试探针的技术现状，它的教导在此作为参考，描述了测试半导体器件时使用的镀金的铜TAB引线框架。
申请人发现本发明的硅和锗材料是替代金的廉价的材料。金具有抗腐蚀性，暴露在大气环境中不会氧化，且是焊料可沾润的。本发明的硅和锗材料基本上和金一样抗腐蚀，而且表面不会形成氧化物，并且也是焊料可沾润的。
此外，金是常用的半导体芯片或封装基片压焊片上的表面金属化，通过导线焊接和超声键合使导线与压焊片电连接。非常惊奇的是，已经发现本发明的硅和锗材料提供的表面就象金一样适合于引线键合。
另外，金是常用的用于半导体芯片或封装基片压焊片的金属化的表面，以便提供一种焊料，特别是铅/锡(lead/tin)焊料可以用来焊接的表面。金是焊料可沾润的表面。令人惊奇的是，已发现本发明的硅和锗材料也是焊料可沾润的。
本发明的含硅和锗材料的特性和金相类似。这些材料在多层金属结构中用作中间层，如半导体芯片和半导体芯片封装基片上的导电的压焊片是有用的。
由于本发明的材料是抗氧化的，而且对氧起到扩散阻挡层的作用，它们也可作为中间阻挡层以防止氧化。
本发明提供了一种在电子器件中提供电学连接的结构，其特征在于包括：一个基片；设置在所述基片上、由导电材料构成的导体；形成在所述导体的表面上、用于形成电学连接的部位的一种不同于所述导电材料的表面材料，其中，所述表面材料包含有第一材料和第二材料的组合；所述第一材料为硅或锗或者它们的组合；所述第二材料为选自Cu、Ni及其组合物的一种金属。
本发明的电学连接结构的表面材料为所述第一材料和第二材料的共价化合物。
本发明还提供了一种在导体表面上形成表面材料的方法，所述导体表面为选自Cu、Ni或其组合物的金属表面，该方法包括下列步骤：提供一具有第一和第二侧面的支撑基片，其第一侧面带有选自Si、Ge或其组合物的一种；把所述支撑基片带有材料的第一侧放在所述表面上使所述材料与该表面接触；在所述支撑基片的第二侧朝着所述表面方向加压；对所述材料加热以使其粘着在所述表面上；冷却所述粘着在一起的材料；以及从所述表面上移走所述支撑基片，所述的材料粘着在所述表面上，形成表面材料。
本发明的方法中，所述加热温度最好低于300℃；所述表面材料和所述构成导体的导电材料的表面相结合形成共价化合物；所述共价化合物选自由Cu3Ge、Cu3Si、Ni3Ge、Ni3Si、这些二元化合物的其他相以及它们的组合构成的一组材料。
通过下面较详细的描述以及附图和权利要求，将使得本发明的这些和其它的目的、特征和优点更加清楚。
图1为具有一含Si和Ge材料的顶面的压焊片的侧视图。
图2为具有多个表面层的图1所示结构的另一个实施例的侧视图。
图3是压焊片另一个实施例的侧视图，这里，和压焊片导电连接的导体是一多层结构。
图4是一个具有含Si和Ce的表面的压焊片的侧视图，压焊片上有一个焊料点。
图5-7表示制造图1所示结构的方法的侧视图。
图8是一个压焊片的侧视图，该压焊片具有含Si和Ge材料的表面，在其上焊接有导线。
图9是引线框架的透视图，此框架上选择的区域有本发明的Si和Ge的材料。
图10是使用了图9所示引线框架的芯片封装的透视图。
图11是使用了图9中的引线框架的芯片封装的透视图。
图12和13表示了使用本发明的含Si和Ge材料作为两个导体之间的焊接材料的方法。
图14、14.1和14.2表示了用于制造本发明的含硅和锗的材料的移画印花转印的方法。
图15和16表示了使用本发明的含Si和Ge的材料作为冶金学的结构中的中间层。
为了使得带有要连接到基片上去的焊料点(如C4)的芯片能够连接到封装基片上象压焊片这样的基片上，需要压焊片具有用于焊接的焊料可粘润的表面冶金特性。铝/铜(Al/4％Cu)是硅芯片或封装基片的典型的最后的布线层。C4不能直接焊接到Al/Cu表面层上。正如这里所说的，在用焊料焊接的压焊片下面有一上部金层，该层覆盖在中间粘合层和阻挡层上。例如，Cr/Cu/Au是典型的可用焊料焊接的表面冶金结构，其中，Cr层是一个粘合层，而Cu是阻挡层，阻挡金层和铬层之下的金属层间的相互扩散。如果使用铜就有两个问题。铜层必须厚到足以允许以后的返工循环，而且铜要能和金互相扩散并溶解在焊料中。返工一个焊接结构，就要把整个结构加热到焊料的熔融温度。在这些温度下能够发生相互扩散。
金的作用是阻止铜的氧化，并给测试探针和焊接提供一个好的表面。然而，经过长时间的贮存或温度变化的影响，Cu和Au可能会相互扩散并使铜到达表面而发生氧化。该氧化的表面将妨碍芯片C4和基片压焊片适当的再流动连接。氧化还将导致测试检查时产生高接触阻抗。一种除去连接的表面氧化物的解决方案是通过另外的熔化步骤处理晶片或基片，在芯片连接工序或测试之前除去氧化物，不过这将既费时又费钱。
这个问题的一种解决方案是使用本发明的含锗或硅的材料。这些材料的示例有下列共价化合物：Cu3Ge，Ni3Ge，Cu3Si和Ni3Si。我们在此叙述了将本发明的含硅和锗的材料用于封装应用，例如，用于芯片的连接。我们也描述了生产这种用于如图1所示的作为压焊片的顶部表面冶金(TSM)的含硅和锗的材料的简化工艺。
图1示出作为一种电子器件，例如半导体芯片或封装基片的基片2，该基片具有安置在基片2的表面6上的导体4。导体4可以是一个压焊片或者引线，这二者典型地有Al/Cu材料。围绕导体4是钝化层8，其上留出了导体4的一个暴露区域10。钝化层8可以是有机的或无机的材料，例如聚酰亚胺、SiO2或Si3N4。设置一层含硅或锗的材料12与区域10接触。层12的厚度可以从大约1,000至10,000埃()。
本发明具有低电阻率的含硅或锗的材料的选择淀积图形可以利用下述工艺来实现。例如，可以用标准的半导体工艺在基片上产生一光刻胶或脱去模板，或者可在基片上放置一个钼掩膜。可以用射频(RF)溅射或离子束从压焊片表面上清洗氧化铝或氧化铜这类氧化物。例如，在室温下真空淀积800埃数量级的锗的薄膜，随后淀积约1,200的铜膜。然后，把该主基片加热至100℃、一个小时。允许固态反应生成合金Cu3Ge。再将该基片冷却至室温，从真空中取出，并用丙酮去除光刻胶膜，或是若使用了掩膜工艺就去除铜掩膜。这样得到的欧姆接触是未氧化的，其标称电阻率为5-12微欧厘米。虽然这种材料的电阻率比纯铜略高一些(＞2微欧厘米)，在Cu3Ge中的铜是稳定的，而且不扩散到硅基片中去。对于较厚或较薄的膜，可以调整上述值来达到所希望的厚度。厚度为1,000至10,000的亚锗酸铜膜是最佳的。万一基片上有严重氧化的压焊片，可以考虑在结构上加上1,000的Cr或Ti薄层。在淀积锗以前和在射频溅射或离子束清洗之后，在压焊片表面上淀积Cr或Ti。Cu和Ge的淀积的顺序可以颠倒。
也可能需要在Cu3Ge合金生成后，在该合金的上部表面淀积一薄层Au，以便为测试探针提供较软的接触面。
图2表示出图1所示结构的另一个实施例。图1和图2所用的共用的参考数字代表相同的东西。在压焊片4的区域10上，安排了一个可选择的层14，它是由厚度为200至2,000的Cr或Ti构成的。层14是粘结层。在层14上安排了层16，层16是由本发明的含硅或锗的材料构成的，其厚度约为1,000至10,000。在层16上安排了一个可选择的层18，它是由厚度大约为2,000的Au，Ag，In，Sn或Pb这样的软材料构成的。
图3示出了本发明的另一个实施例，它使用本发明的含硅和锗材料在具有Cu或Cr/Cu/Cr布线的基片上制造基片的顶部表面冶金(TSM)，图1、2、3中的共用的数字代表相同的东西。压焊片4是由Cr构成的底层20、Cu构成的中间层22和Cr构成的顶层24构成的。这种情况下，假如使用Cu3Ge，如前所述，可以通过从顶层金属24的表面23上清洗任何铜的氧化物来制造，或者使用常用的光刻技术在Cr/Cu/Cr结构4的Cr构成的顶层24上开出窗口以暴露出窗口26处的Cu层22的方法来制造。例如，把锗层28淀积到的1,600的厚度，随后淀积厚约1,200的铜层30。如前所述，然后如图4所示那样由层28和层30形成亚锗酸铜层32。图4另外还示出焊接在亚锗酸铜层32上的焊料点34。该由Cu3Ge组成的TSM层比通常的Cr/Cu/Au结构具有一些优点。它和Cr/Cu/Au一样是焊料可以粘润的，而长时间暴露在室温和高于室温的大气中，Cu3Ge顶层的可沾润性并不降低。因此，当基片经过芯片连接工序时，覆盖有本发明的含锗或者硅的材料的压焊片将不会被氧化。在芯片连接以前不需要加焊剂到含锗或硅的层上或者将其暴露在一个加热炉中加热处理以除去氧化物。这种材料也能用于芯片的连接和返工过程而极少有Cu3Ge溶解进入焊料中，因此不需要蒸发较厚的铜。
通常在一排芯片压焊片上设置C4焊料点(通常用通过一个钼掩蔽层的蒸发工艺形成)。再将其上带有焊料点的芯片设置在一个有一排相应的压焊片的基片上。这些基片上的压焊片可以有含锗或硅的TSM层，以防止基片压焊片的表面产生氧化，同时还可以避免在C′4与含锗或硅的TSM层的连接焊点上使用熔剂。C4焊接法已在美国专利第3,429,040和3,401,126号中作了详细说明。这里结合这两个专利中的教导进行描述。
通过在一个淀积在硅上的铝覆盖膜上沉积一层Cu3Ge覆盖膜测量出Cu3Ge的电阻。该铝膜已在其上腐蚀出一个5mm的带而隔开。然后将Cu3Ge沉积在该铝膜上，并在100℃条件下退火。铝膜厚为300A，Cu3Ge厚为1870。所测得的Cu3Ge的电阻率是13微欧姆厘米。
如上所述，在硅半导体器件中使用铝/铜(典型的为Al-40％的Cu)接触金属薄膜(metallurgy)时所碰到的问题是：在淀积后的热处理过程中，可能出现硅从接触区域向邻近的铝互连金属薄膜内扩散。为了解决这个可能引起很大的漏电或短路的问题，应在铝薄膜内加入重量百分比为1.0％-1.5％的硅，这个量超过硅在铝中的溶解度所要求的0.5％重量百分比。
所存在的问题是在一个铝接触金属薄膜上蒸发形成的硅层常常并不完全扩散进入铝内。在铝表面上残留的硅或硅的氧化物可以在将引线焊接到铝金属薄膜上时导致虚焊连接(no-stick connec-tion)。
消除这些残留的硅或硅氧化物的技术是在硅扩散步骤之后对压焊片表面进行RIE处理。然而，其结果是在进行完RIB处理之后，往往还残留有硅和硅氧化物，而且在表面上还可能形成由硅、铜、氧、碳和氟构成的金属中间层。
解决这种不希望的表面残留物问题的发明是一种新的接触金属薄膜结构，这种结构将锗或硅材料置于铝金属薄膜的上部表面之上。已经发现引线可以直接焊接在这种其中扩散有硅、并且覆盖有一层本发明的扩散得到的含锗和硅材料层的Al/Cu导体上，图5、6和7示出了制作具有本发明的含锗和硅的化合物的上部表面的结构。图5、6和7中同样的编号代表同样的东西。
图7所示的结构可以使用标准的铝/铜接触金属薄膜以及其它的金属薄膜，例如，单独的铜。在图5中，1微米厚的铝/铜层42淀积在基片40上。硅层44是蒸发淀积在层42上的。薄铜层46蒸发在层44的上部表面。根据本发明，必须蒸发足够的硅以便形成一个铜/硅材料层，并留下足够的硅(约200厚)，用以扩散进入铝/铜层42，使满足溶解度的要求。在蒸发完约300A的硅后，再淀积一层150A的铜。当淀积铜层之后，对图5所示结构进行热处理，温度从100℃到300℃，通常较理想的方法是在温度为200℃时，热处理的时间可从10分钟到60分钟。制作图6所示结构，最好热处理30分钟。这种方法在金属冶金结构50的上部表面52形成约250的铜/硅材料层48。在层48下面，有一硅层54。将图6所示结构在350℃到450℃的条件下热处理30至60分钟，以便保证使层54中的硅扩散进入铝/铜夹层42，从而满足溶解度的要求。根据本发明，最佳实施例的处理过的结构包括约1.0微米的铝/铜(其中铝占4％)，铜内扩散有0.5％的硅，并覆盖一层数百的铜/硅材料。该铜/硅材料具有很小的电阻，数量级约60微欧姆-厘米，并且形成很好的适合于引线焊接的表面。
对于图7所示的结构中，硅通常用于硅器件，锗通常用于锗器件。
图8示出在图7的结构的表面上带有焊接引线56的表面层48。这里可以使用任何通常的导线，如铝，铜或金导线，并可使用通常的导线焊接技术，如：热压焊，超声焊，热声(thermosonic)焊接，以及激光焊接等。
图9所示的是一个引线框架130、可作为α-粒子阻挡层的介电膜132和半导体芯片134的分解示意图，表示出本发明一个实施例的这些元件的空间相互关系。引线框架130是由金属薄板、可自动焊接带TAB(tape automated bonding)及可弯曲的带等制成，并带有定位孔136。该引线框架可以是铜、铜合金、合金42(42％镍，58％铁)，不胀铜(36％镍，64％铁)、铝或其他适合的材料。引线框架130由多根作为引线的导体138构成，每一根引线有一个内端139。
在半导体芯片134之上延伸的那部分导体138由绝缘膜132与半导体芯片134隔离。至少内部的那部分138用含本发明的含锗和硅材料覆盖，以实现以下叙及的导线焊接。
介质膜132是一种聚合物膜，其熔化温度超过175℃，而且不含有钠、钾、磷的活性金属及卤化物之类的可电离的元素。美国专利号为4,426,657、发明人为Abiru，Sugimoto和Inomata的专利建议使用聚酰亚胺膜作为绝缘介质膜。一种聚酰亚胺膜是DupontKapton。
半导体芯片134由一个粘性层(图中未示出)粘附在引线框架130上。可以将带粘性的薄层加在引线框架导体1或芯片134的上部有源表面154上。该上部表面154是芯片134的主表面之一。为了避免在芯片上发生短路的可能性，尽管通常在芯片上覆盖有钝化材料或绝缘材料，最好还是使用介质插入物。该介质插入物最好是插在导体与芯片之间的一个作为α粒子阻挡层的介质膜132。然后把粘性层加到α粒子阻挡层的两个表面上，各个表面使用不同的粘结材料。
为了使介质膜132既可有效地起到小粒子阻挡层的作用，又可以进行有效的热传导，其厚度应在1.5至2密耳(10-3英寸)之间。
半导体芯片134用第一粘性层粘附在介质膜132上。该第一粘性层可以是选自环氧树脂、丙烯酸盐、带有硅铜的聚酰亚胺和硅铜中的一种，这些材料较理想，因为它们具有抗腐蚀作用。
第二层粘性层将介质膜132粘附在导体138上，该粘性层也选自环氧树脂、丙烯酸盐、硅铜和聚酰亚胺。理想的第二层粘性层应选自于环氧树脂和丙烯酸盐，因为这些材料可以确保导体138充分粘附在介质膜132上，从而可以改进半层体芯片134和导体138间的热传导特性，并可牢固地将引线框架的导体138固定在半导体芯片134上。
在引线框架130的导体138之间设置有十字形构件140，以使引线框架130具有一定的刚度，并在半导体芯片134、介质膜132和导体138被封装时，限制封装材料的流动。
图10示出了一个封装后的包含一半导体芯片134的管壳142，其中去除了一部分封装材料146。封装后，图9所示的引线框架的多余部分148以及十字形构件140被除去。可按要求形成伸出外壳142的导体138。去掉的十字形构件部分示于图10的140′处。
导体138的厚度应尽量减小，以便保证顶部到底部最大的密封剂密封。线156所示的部分的最大的密封剂粘合(Knitting)增强了抗裂性。为了保证导体在封装材料中的密封性，需要约0.5至1毫米的最小的通路长度。
在引线框架导体138封装固定时，需要将导体138作成带有如图10中弯折处150所示的锐角状。由于引线框架导体带有这样的弯角，本发明的封装允许半导体组件在保持很好的机械特征的同时减小其宽度。这是因为封装材料内部的引线长度不再受芯片与外壳边缘之间距离的限制。
导体138应将半导体芯片134表面区域覆盖住30％到80％，覆盖的百分比越大越好。应避免导体138与半导体芯片134上引线端压焊片相接触。最大的覆盖面积可保证有效地冷却半导体芯片134，并可保证将导体138可靠地焊接在半导体芯片134的表面上。粘附到和到达芯片134上的导体138越长，从管壳外部到引线连接处形成的路径(D)就越长，由此增强了抵抗可引起腐蚀和提前失效的环境污染的能力。
在完成这种封装的半导体芯片的现有工艺后，从含有终端压焊片152的半导体芯片134的有源层154排出热量比现有技术中对已封装好的半导体芯片从其背面排出热量更有效。
终端压焊片152经导线158与导体138相连接。导体138的形状最好是导线158长度不超过30密耳。使导线158的长度减至最小可改善封装后的半导芯片的电学性能。
图10的结构安装在一个基片上(未示出)，而且导体138的外端162也用焊料焊接到基片上的压焊片上。图10示出导体138的外端162由外壳142向外弯曲延伸。这些外端也可在外壳142下面向内弯曲。这种引线通常称之为J型引线。图11示出与图10类似的一种结构的横截面图。图11中，引线框架170带有连接在芯片180上的压焊片178和引线170的内引线端172以及174之间的导线176。用一种模注化合物182将芯片和内部引线端172和174密封起来，以形成封装好的芯片结构186。引线170的外端184向封装体186内部弯曲。弯曲的引线端184可连到基片的压焊片或通过焊料192与基片190上的连接部位188上。基片190可以是一个印刷线路板、一个金属化的封装陶瓷基片或一个可弯曲的带等。
综上所述，图9、10和11的发明包括一引线框架，它可以用铜或其它材料制成，其上覆盖有一层合适的含锗或硅材料，如Cu3Ge、Ni3Ge、Ni3Si以及Cu3Si或这些二元化合物的其它相。形成这种含锗和硅的材料的工艺过程使它能够覆盖任何适合的引线框架材料。引线框架不一定非得用铜制造。这种覆盖层可加在压焊片的位置处(可采用点镀或涂镀的方法)，也可覆盖全部引线框架。用蒸发或电镀法可以制作含锗或硅的材料，并在之后对其进行热处理。例如，可以蒸发Cu3Ge和Ni3Ge，Cu3Ge也可以用电解装置进行电镀。要注意的是Cu3Si在250℃以上温度条件下形成表面氧化物。Ni3Ge可以采用非电的方法镀覆。
本发明的含锗和硅材料的独有特性是这种锗和硅在焊料焊接时可使用另一种焊接技术。由于电子或机械连接工艺过程中材料所能到达的温度，计算机封装元件通常需考虑材料的限制。然而，计算机封装工艺需要高强度、高导电率和高导热性的连接。焊料连接通常用于连接导体。但使用焊料一般需要使用焊剂，并且随后需要将其清除掉。当然在不需要好的热或电传导特性时，可用有机环氧树脂连接两个元件。不过采用这种方法时，环氧树脂被限制在它们的温度范围内。对于那些工作在热条件下的元件，例如供电元件，就需要一种能经受高温的连接介质。
根据本发明的一种结构包括两个或多个元件，这些元件可以是印刷线路板，可弯曲的电路或机械零件，它们根据需要用本发明的含锗和硅的材料(如Cu3Ge)构成的媒介，进行机械、热的和电的连接，这里Cu3Ge是作为粘附和传导媒介。在该连接结构中，每一个机械元件都要有一个Cu3Ge与之完全接触的铜表面。为了制作这种结构，需将每一个元件的待连接表面作成铜表面。印刷电路板和弹性电缆一般就采用这种方法制作。如果表面不是铜材料，则应使用适当的方法加上铜，如电镀或蒸发。然后用适合的方法：如电镀或蒸发，至少在其中一个表面上加上一层锗。清洗铜表面并使其在适中的温度及压力下与锗紧密接触，典型的压力为10千磅/英寸2(Kpsi)，典型的温度为100℃到200℃。其结果是形成图12所示的结构。
如图12，在基片200上面有一个金属冶金结构202，其具有一个Cu或Ni表面204，另外一个Cu或Ni层206，图9中的导体138的内端139，通过其间的锗或硅层208与表面204相邻。在加压加热之后，形成图13的结构。图12与图13中相同参考标号表示同样的东西。图12中的层208变成了层210，该层是本发明的含锗或硅的化合物。
这里还有一些使用新的连接技术的实例。其中第一个是将锗镀在一个铜/聚酰亚胺柔性电缆的接触上。先清洗一个配对的铜印刷电路板，然后在160℃下以20kpsi压力加压所述电缆。由此而制成一个具有Cu/Cu3Ge/Cu/聚酰亚胺金属冶金结构的印刷电路板。为了试验粘接聚酰亚胺和用于供电应用的钼元件的可行性，结构按如下制作：(1)在钼(Mo)基片上蒸发200厚的铬，然后蒸发1.0微米(μm)的铜；(2)在25μm厚的Upilex(聚酰亚胺也是合适的)层上蒸发由厚200的铬、厚1.0μm的铜、厚2,000的锗构成的层。清洗铜表面，并如上所述那样将其压在锗表面上。由此形成叠层结构：Mo/Cr/Cu/Cu3Ge/Cu/Cr/Upilex。在此结构样品上进行拉伸度测量，施加的强度为30克/毫米(g/mm)。
在构件206或204表面上沉积锗或硅层208的方法是移画印花(decal)工艺，这种方法是一个用于将锗或硅转移到一个导体上(如铜或镍)上的干燥的工艺过程。采用这种移画印花工艺可以在铜层上形成一个钝化层。
参照图14，移画印花工艺形成的213有一个薄的挠性共形基片212，它可以是如Upilex或聚酰亚胺等聚合材料。在基片212上有一很薄的锗或硅层214，其厚度范围为500到5,000，最佳厚度为1,000。制作214夹层可以采取在加入晶种后蒸发、溅射、电镀或其它合适的方法。
该工艺过程第一步是清洗导体218的表面216。如218是铜材料，就使用铜清洗槽液，如硫酸。然后使表面216与移画印花213的锗或硅214接触，再用适当的力加压使这两个表面形成紧密接触，图14中箭头220表示压力的方向。一种适当的加压是液压。在二者加压力的同时，把温度从100℃升至300℃，较好为230℃，一直到在铜线218的表面216上形成含锗或硅的材料层，如铜-锗，较理想的是Cu3Ge。时间约几分钟就足够了。然后将部件从液压机中移走，如图14-1所示，该移画印花从铜表面216剥起，见215箭头所示，其中在铜表面216上有一个锗或硅覆盖层214。图14-2示出所形成的结构，该结构带有一个设置在铜表面216上的锗层214。如前所述，可以提供热来形成本发明含锗或硅的材料。这种新的结构包括铜之类的导体，该导体覆盖有一层，本发明的含锗或硅材料的层。
本工艺适用于任何平面型的或可弯折的铜基片，如陶瓷、硅或其他基片薄膜再分布图形。具有铜表面的印刷电路板或部分印刷电路板也可以采用这种工艺涂覆，由于是用铜作导体的可塑性的电路(弯曲或TAB)(自动焊接带)。在连续的铜表面上制作有图案的覆盖层前可以将移画印花薄膜做图案。也可以通过挤压两个滚筒间的薄铜板而以连续的方式施加此涂覆层。
如果含聚酰亚胺作介电材料的结构中使用铜导体，可以将铜导线表面钝化，以便防止受到在制作另一聚酰亚胺绝缘层时所用的聚酰胺酸的腐蚀。钝化的方法如前所述。这种结构是由带有聚酰亚胺绝缘层的铜导体组成的，其中，铜引线上部表面用本发明的含硅或锗材料进行钝化。
图15示出结构210，该结构具有埋在介质体216内的导体212和214。导体212和214分别具有用本发明的含硅和锗材料制成的上部层218和220。另外，在介质体216的表面222上设置有一聚酰胺酸(polyamic acid)(PAA)层217。层217有窗口224和226，并在窗口分别露出层218和220，由于有层218和220的存在，层217不与导体212和214接触。
218和220层起着阻挡层的作用，以防止铜原子与PAA层217接触。铜原子与PAA接触则形成络合物，当对层PAA进行加热使聚酰亚胺固化时，所形成的络合物释放出铜氧化物。这种铜氧化物粒子是不需要的，因为它们增加了聚酰亚胺的介电常数。在美国专利5,053,272中，详述了这种铜氧化物分子在PAA中的形成。
图15中的结构210可用来作为半导体芯片封装基片或者用作这样一种基片的上部金属化层或者半导体芯片上的上部金属化层。
图15中的空间224和226可填充图16所示的导电材料225和227。在烧结的PAA层217变成聚酰亚胺后，如果基片216是聚酰亚胺，则图15中的表面222就不再看得清楚了。所以图16中所示的表面222用虚线表示之。如果两个聚酰亚胺层被层叠或者粘合在一起，它们就保持清楚的各个层。图16中，层218是导体212与215之间的中间层，而夹层220是导体214和227之间的中间层。
本发明的硅和锗材料适合作为中间层，起到互扩散阻挡层或抗腐蚀层。这对于埋在聚合物中的导体特别有用，这些聚合物有含有残留水的聚酰亚胺等，其中的水起到不同金属间的电镀效应中电解液的作用。电镀效应会对Cr/Cu/Cr或Cr/Cu/Ti/Au的金属冶金结构产生腐蚀。
本发明的含硅和锗的材料，例如铬和铜，的相互界面之间的Cu3Ge，主要用来消除腐蚀。在此我们介绍一种结构，在这种结构中，铜或镍层由覆盖有本发明的含锗或硅材料的铜或镍金属替代。另一种结构是用这些材料整体上替代铜层。例如，用一个新结构Cr/Cu3Ge/Cu/Cu3Ge/Cr来替代结构为Cr/Cu/Cr的压焊片(其中Cr层厚200，Cu层厚3.5μm)，新结构的各层厚度是：两层Cr都是200，两层Cu3Ge都是5,000，Cu为2.5μm。另外一个新结构是Cr/Cu3Ge/Cr，其中两个Cr均为200，Cu3Ge为3.5μm。
可以用一种新结构Cr/Cu3Ge/Cu/Ti/Au(其中Cr厚200，Cu3Ge厚5,000，Cu厚5.5μm，Au厚1μm)替代结构Cr/Cu3Ge/Cu/Ti/Au(其中Cr层为200，Cu层为6μm，Ti层为1μm，Au层为1μm)，另外一种新结构是Cr/Cu3Ge/Ti/Au，其中，Cr为200，Cu3Ge不6μm，Ti为1μm，Au为1μm。
这里有两种较好的淀积本发明的含锗和硅材料层(如Cu3Ge)作为中间层的方法。可采用通常的钼掩膜工艺进行这两种淀积工艺。第一种制作Cu3Ge层的方法是按顺序蒸发Cr，Ge，Cu，Ge，Cr，锗层厚约为2,500，铜层厚约为3.0μm。将该结构就地于200至300℃退火15-30分钟。也可以用一种已经制作好的材料源直接淀积Cu3Ge。一种淀积顺序是：Cr，Cu3Ge，Cu，Cu3Ge，Cr。
用Cu3Ge代替铜的所有具体实施例都可以用直接淀积Cu3Ge的方法，或轮流淀积Ge和Cu层，然后退火处理的方法来进行。
另外，图9中所示的具有本发明的含Si或Ge材料的引线框架可以用下述非电淀积的方法制造，介绍的是在Cu上淀积Cu3Ge的方法，但并不限于这种材料的选择。
我们介绍了表面包含形成在铜上的Cu3Ge层的一种电接触。铜可以是一个很薄的层，或者是电接触的一个整体材料，这种接触的整体材料可以是铜或者是其它在其上能够镀铜的适当的材料，如BeCu，或CuNi或黄铜等。这种接触可以是弹簧形式的，可以是粘在一个挠性基片上一部分导体的，或可以是能被用于测试的独立式探针。
这里介绍制作上述结构的方法。若接触的整体材料不是铜，则首先在其表面上镀厚约1,200的一层铜，然后用电学方法在整体铜或者在整体材料上的薄铜层上面镀上一层锗，其厚度约为800(与铜层厚度的2/3)。我们发现恒压的电镀装置比恒流的装置更适合于未定区域的电镀表面。将这种结构在200℃下退火处理30分钟，结果在表面上形成一个Cu3Ge层。电镀所用的工艺条件如下：镀槽内丙二醇(propylene glycol)中含7％的GeCl4，温度为65℃，且电镀在恒压条件下进行，用固体锗作为阳极。图1所示的电接触是通过电镀制的，电镀条件为35伏，时间短于5分钟。而对于精密调节的测试探针用3.5伏电压，时间为4分钟，电流应控制在1安培左右。
如前所述那样将此结构退火。用X光衍射分析样品，确认形成了Cu3Ge。
这种结构和工艺适合于所有用铜制作的或由在其上可镀铜的材料制成的接触点或探针结构。这一结构的主要优点是比镀金便宜，而它所形成的表面硬度比金要硬。专利申请号为07/583,261(申请日1990、9、14)的未决专利申请中介绍了使用引线框架作为测试探针，可供参考。
在电子器件的封装中使用锗化合物，以便降低制作的工艺成本，而且理想的涂覆的方法是非电的。而另一种可以替代的电镀则要求有一个公共电极，这就限制了它的可行性。淀积工艺需使用昂贵的设备和较长的时间，而非电涂覆法解决了这个问题。
这里我们将介绍一种在适当的基片上非电涂覆锗化合物所用的镀液。尤其介绍在铜上涂覆镍-锗(Ni3Ge)。我们还介绍了一种与砷化镓器件的接触，这种接触包括一个镍层以及在其上面的用非电涂覆制成的镍-锗层。
镀液包括以下溶液：
准备一个500毫升水溶液，其中包含3克/升的硫酸镍七水合物，9克/升的柠檬酸三钠二水合物，20克/升的无水次磷酸钠。
准备50毫升第二水溶液，其中含有50克/升的四氯化锗，135克/升的柠檬酸钠，48克/升的柠檬酸。
把第二水溶液加入第一水溶液内。在85℃温度下通过蒸发使550毫升溶液减至500毫升。把铜片放入此电镀液中进行电镀。通过无电涂覆将镍-锗涂覆在适当的基片上，生产出前面所述的、图中所示的结构。
测试镍-锗表面以用于进行焊接。在该表面上很容易进行导线连接和焊料接触。
可以理解，上述实施例只是简单地描述了本发明的构思，本领域的熟练技术人员很容易完成本发明构思的各种改进和变化，这些都应属于本发明的构思范围之中。

Claims (15)

1.一种在电子器件中提供电学连接的结构，其特征在于包括：
一个基片；
设置在所述基片上、由导电材料构成的导体；
形成在所述导体的表面上、用于形成电学连接的部位的一种不同于所述导电材料的表面材料，
其中，所述表面材料包含有第一材料和第二材料的组合；
所述第一材料为硅或锗或者它们的组合；以及
所述第二材料为选自Cu、Ni及其组合物的一种金属。
2.根据权利要求1的电学连接结构，其特征在于：所述表面材料是所述第一材料和第二材料的共价化合物。
3.根据权利要求1或2的电学连接结构，其特征在于：所述导体是具有多根引用的引线框架上的引线。
4.根据权利要求1或2的电学连接结构，其特征在于：所述导体是半导体芯片上的压焊片。
5.根据权利要求1或2的电学连接结构，其特征在于：所述导体是印刷电路板上的一个待连接部分。
6.根据权利要求3的电学连接结构，其特征在于还包括：粘结到所述表面材料上的焊料。
7.根据权利要求4的电学连接结构，其特征在于还包括：粘结到所述表面材料上的焊料。
8.根据权利要求5的电学连接结构，其特征在于还包括：粘结到所述表面材料上的焊料。
9.根据权利要求3的电学连接结构，其特征在于：所述表面材料在所述引线的内端上。
10.根据权利要求2的电学连接结构，其特征在于：所述共价化合物选自Cu3Ge、Cu3Si、Ni3Ge和Ni3Si以及这些二元化合物的其它相中选择出的一种构成的一组材料。
11.根据权利要求1的电学连接结构，其特征在于：所述表面材料选自由硅化物的化合物、亚锗酸盐的化合物及其组合形成的一组材料。
12.一种在导体表面上形成表面材料的方法，所述导体表面为选自Cu、Ni或其组合物的金属表面，该方法包括下列步骤：
提供一具有第一和第二侧面的支撑基片，其第一侧面带有选自Si、Ge或其组合物的一种材料；
把所述支撑基片带有所述材料的第一侧面放在所述导体表面上，使所述材料与该表面接触；
在所述支撑基片的第二侧面朝着所述表面方向加压；
对所述材料加热，以使其粘着在所述表面上；
冷却；以及
从所述表面上移走所述支撑基片，所述的材料粘着在所述表面上，形成表面材料。
13.根据权利要求12的方法，其特征在于：所述加热温度低于300℃。
14.根据权利要求12或13的方法，其特征在于：所述材料和所述表面相结合形成共价化合物。
15.根据权利要求14的方法，其特征在于：所述共价化合物选自由Cu3Ge、Cu3Si、Ni3Ge、Ni3Si、这些二元化合物的其他相以及它们的组合构成的一组材料。
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