ES2131080T3 - Metodo de deposicion de material que contiene si o ge sobre una superficie de cu o ni. - Google Patents

Metodo de deposicion de material que contiene si o ge sobre una superficie de cu o ni.

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Publication number
ES2131080T3
ES2131080T3 ES93105142T ES93105142T ES2131080T3 ES 2131080 T3 ES2131080 T3 ES 2131080T3 ES 93105142 T ES93105142 T ES 93105142T ES 93105142 T ES93105142 T ES 93105142T ES 2131080 T3 ES2131080 T3 ES 2131080T3
Authority
ES
Spain
Prior art keywords
material containing
deposition method
electrolytically
germanium
packages
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES93105142T
Other languages
English (en)
Inventor
Michael John Brady
Curtis Edward Farrell
Sung Kwon Kang
Jeffrey Robert Marino
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of ES2131080T3 publication Critical patent/ES2131080T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53271—Conductive materials containing semiconductor material, e.g. polysilicon
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
    • C23C18/48—Coating with alloys
    • C23C18/50—Coating with alloys with alloys based on iron, cobalt or nickel
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    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D3/00—Electroplating: Baths therefor
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    • C25D3/54—Electroplating: Baths therefor from solutions of metals not provided for in groups C25D3/04 - C25D3/50
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S428/00—Stock material or miscellaneous articles
    • Y10S428/901—Printed circuit
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
    • Y10T428/24917—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including metal layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • General Chemical & Material Sciences (AREA)
  • Electrochemistry (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Other Surface Treatments For Metallic Materials (AREA)
  • Chemically Coating (AREA)
  • Chemical Treatment Of Metals (AREA)

Abstract

SE DESCRIBEN CIERTOS MATERIALES QUE CONTIENEN SILICIO Y GERMANIO,UTILES EN LA SUPERFICIE DE CONDUCTORES DE DISPOSITIVOS ELECTRONICOS.LA SOLDADURA PUEDE SER LLEVADA A CABO DE FORMA DESAGREGADA Y LOS HILOS PUEDEN ENLAZARSE EN TALES SUPERFICIES.ESTOS MATERIALES SE UTILIZAN COMO REVESTIMIENTOS SUPERFICIALES DE ARMAZONES DE PLOMO PARA PAQUETES DE CHIPS DE CIRCUITOS INTEGRADOS.ESTOS MATERIALES PUEDEN SER TRANSFERIDOS SOBRE SUPERFICIES CONDUCTORAS O DISPUESTOS SOBRE ELLAS ELECTRONICA Y ELECTROLITICAMENTE.
ES93105142T 1992-04-24 1993-03-29 Metodo de deposicion de material que contiene si o ge sobre una superficie de cu o ni. Expired - Lifetime ES2131080T3 (es)

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US87330792A 1992-04-24 1992-04-24

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US (1) US5855993A (es)
EP (1) EP0566901B1 (es)
JP (1) JP2526007B2 (es)
KR (1) KR0135739B1 (es)
CN (1) CN1112729C (es)
AT (1) ATE180357T1 (es)
BR (1) BR9301497A (es)
CA (1) CA2089791C (es)
DE (1) DE69324959T2 (es)
ES (1) ES2131080T3 (es)
MY (1) MY134716A (es)
TW (1) TW217459B (es)

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US6622907B2 (en) * 2002-02-19 2003-09-23 International Business Machines Corporation Sacrificial seed layer process for forming C4 solder bumps
US6703291B1 (en) * 2002-12-17 2004-03-09 Intel Corporation Selective NiGe wet etch for transistors with Ge body and/or Ge source/drain extensions
JP3674927B2 (ja) * 2003-06-13 2005-07-27 Ｔｄｋ株式会社 電子部品の製造方法および電子部品
US20060147683A1 (en) * 2004-12-30 2006-07-06 Harima Chemicals, Inc. Flux for soldering and circuit board
DE102005028906A1 (de) * 2005-06-22 2006-12-28 Giesecke & Devrient Gmbh Vorrichtung für die Prüfung von Banknoten
US20070117475A1 (en) * 2005-11-23 2007-05-24 Regents Of The University Of California Prevention of Sn whisker growth for high reliability electronic devices
US7659200B2 (en) * 2007-01-05 2010-02-09 International Business Machines Corporation Self-constrained anisotropic germanium nanostructure from electroplating
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JP5042894B2 (ja) * 2008-03-19 2012-10-03 松田産業株式会社 電子部品およびその製造方法
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US9988713B2 (en) 2013-03-12 2018-06-05 Arizona Board Of Regents On Behalf Of Arizona State University Thin film devices and methods for preparing thin film devices
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Publication number Publication date
DE69324959T2 (de) 1999-12-02
CN1112729C (zh) 2003-06-25
TW217459B (es) 1993-12-11
CA2089791C (en) 1998-11-24
EP0566901A2 (en) 1993-10-27
DE69324959D1 (de) 1999-06-24
ATE180357T1 (de) 1999-06-15
JPH0621140A (ja) 1994-01-28
EP0566901A3 (es) 1994-01-26
CA2089791A1 (en) 1993-10-25
MY134716A (en) 2007-12-31
EP0566901B1 (en) 1999-05-19
CN1082770A (zh) 1994-02-23
KR930022536A (ko) 1993-11-24
KR0135739B1 (ko) 1998-04-24
US5855993A (en) 1999-01-05
JP2526007B2 (ja) 1996-08-21
BR9301497A (pt) 1993-10-26

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