CN111162052B - 一种半导体封装结构及其键合压合方法 - Google Patents
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Abstract
本发明涉及一种半导体封装结构及其键合压合方法,所述方法包括与以下步骤:取一引线框架,所述引线框架基岛与内引脚左右两侧开设有开槽,在引线框架基岛表面通过焊料贴装芯片,左右两侧的键合压爪从侧面插入开槽内,从而完成对引线框架的非表面压合固定,再进行铝线键合作业。本发明一种半导体封装结构及其键合压合方法,它利用一种边缘侧面开槽开孔的框架,键合压爪从侧面斜插或侧面直插后垂直压合,以完成键合时引线框架的固定。
Description
技术领域
本发明涉及种半导体封装结构及其键合压合方法,属于半导体封装技术领域。
背景技术
在半导体封装行业中如何高度集成提高封装比,一直是行业的发展方向。封装比提高后,产品的电性指标不受限制,产品的最终设计功率同样会得到提升。
在传统功率器件封装中铝线键合工艺是一种常规技术,在焊接时依靠高强度或高密度的键合压爪在引线框架的边缘压住引线框架,通过焊头将铝线焊接在芯片和引线框架上,如图3所示,在此过程中如果芯片在装片过程中发生旋转或位置偏移,会被键合压爪压伤,因此在产品的封装设计过程中,在引线框架基岛区域需要预留键合压爪的压合位置和安全距离,以防止键合压爪在压合过程中损伤芯片,在引线框架的管脚区域同样考虑键合压爪的占位间距和空间以保证足够的焊接空间。
所以键合压爪在焊接时在引线框架基岛和管脚占用了大量的焊接空间,限制了功率器件铝线键合封装比的进一步提高。
发明内容
本发明所要解决的技术问题是针对上述现有技术提供一种半导体封装结构及其键合压合方法,它利用一种边缘侧面开槽开孔的框架,键合压爪从侧面斜插或侧面直插后垂直压合,以完成焊接时引线框架的固定。
本发明解决上述问题所采用的技术方案为:一种半导体封装结构,包括基岛、引脚、与塑封料,所述基岛左右两侧设置有基岛侧边槽,所述引脚包括中间引脚和两侧引脚,所述中间引脚直接与基岛连接,所述两侧引脚位于中间引脚两侧,所述两侧引脚包括内引脚和外引脚,所述内引脚远离中间引脚的一侧设置有引脚侧边槽,所述基岛上通过焊料设置有芯片,所述芯片通过焊线与内引脚电性连接,所述芯片、基岛、内引脚、焊线及部分中间引脚包覆在塑封料之内,所述基岛侧边槽和所述引脚侧边槽内填充有所述塑封料。
一种半导体封装结构的键合压合方法,所述方法包括与以下步骤:
取一引线框架,所述引线框架基岛与内引脚左右两侧开设有开槽,在基岛表面通过焊料贴装芯片,左右两侧的键合压爪从侧面插入开槽内,从而完成对引线框架的非表面压合固定,再进行铝线键合作业。
优选的,侧面的开槽为斜坡式结构。
优选的,侧面的开槽为方形结构。
优选的,键合压爪斜向插入斜坡式开槽内。
优选的,键合压爪先横向直插如方形开槽内,再垂直向下压合。
与现有技术相比,本发明的优点在于:
1、本发明利用引线框架基岛与内引脚侧面的开槽,采用非表面压合方式,从而在封装设计时无须考虑键合压爪的预留空间和安全距离,使传统封装可以装载尺寸更大的芯片,突破传统封装的封装比;
2、本发明利用引线框架基岛与内引脚侧面的开槽,采用非表面压合方式,键合压爪不会有压伤芯片的风险,降低产品的失效风险,同时装片工序的装片角度可以有更多种类的选择;
3、本发明利用引线框架基岛与内引脚侧面的开槽,采用非表面压合方式,内引脚无须考虑键合压爪的预留空间,可以在内引脚焊接更粗线径的铝线,以提高产品的电性参数;
4、本发明采用的引线框架基岛与内引脚侧面均有开槽,塑封料填充入开槽,可以有效提升塑封料与基岛和引脚的结合牢度,降低该封装的分层风险。
附图说明
图1为本发明一种半导体封装结构的俯视图。
图2为图1沿AA’方向的剖视图
图3为本发明一种斜插式非表面压合方式的示意图。
图4为本发明一种直插式非表面压合方式的示意图。
图5为传统铝线键合压爪压合方式示意图。
芯片1
焊料2
斜坡式开槽31
方形的开槽32
斜插式键合压爪41
直插式键合压爪42
传统键合压爪43
基岛5
引脚6
中间引脚61
两侧引脚62
内引脚621
外引脚622
焊线7
塑封料8
基岛侧边槽9
引脚侧边槽10。
具体实施方式
以下结合附图实施例对本发明作进一步详细描述。
如图1、图2所示,本发明涉及的一种半导体封装结构:包括基岛5与引脚6,所述基岛5左右两侧设置有基岛侧边槽9,所述引脚6包括中间引脚61和两侧引脚62,所述中间引脚61直接与基岛连接,所述两侧引脚62位于中间引脚61两侧,所述两侧引脚62包括内引脚621和外引脚622,所述内引脚621远离中间引脚61的一侧设置有引脚侧边槽10,所述基岛5上通过焊料2设置有芯片1,所述芯片1通过焊线7与内引脚621电性连接,所述芯片1、基岛5、内引脚621、焊线7及部分中间引脚61包覆在塑封料8之内,所述基岛侧边槽9和所述引脚侧边槽10内填充有所述塑封料8。
如图3所示,本发明涉及的一种半导体封装结构的键合斜插式压合方法,所述方法包括以下步骤:
取一引线框架3,所述引线框架基岛与内引脚左右两侧开设有斜坡式开槽31,在基岛表面通过焊料2贴装芯片1,左右两侧的斜插式键合压爪41从侧面斜向插入斜坡式开槽31内,从而完成铝线键合时键合压爪的斜插式非表面压合固定框架。
如图4所示,发明涉及的一种半导体封装结构的键合直插式压合方法,所述方法包括以下步骤:
取一引线框架,所述引线框架基岛与内引脚左右两侧开设有方形开槽32,在引线框架表面通过焊料2贴装芯片1,左右两侧的直插式键合压爪42从侧面直插入方形开槽32内,再垂直向下压合从而完成铝线键合时键合压爪的直插式非表面压合固定框架。
上述实施例外,本发明还包括有其他实施方式,凡采用等同变换或者等效替换方式形成的技术方案,均应落入本发明权利要求的保护范围之内。
Claims (6)
1.一种半导体封装结构,其特征在于:其包括基岛(5)、引脚(6)与塑封料(8),所述基岛(5)左右两侧设置有基岛侧边槽(9),所述引脚(6)包括中间引脚(61)和两侧引脚(62),所述中间引脚(61)直接与基岛(5)连接,所述两侧引脚(62)位于中间引脚(61)两侧,所述两侧引脚(62)包括内引脚(621)和外引脚(622),所述内引脚(621)远离中间引脚(61)的一侧设置有引脚侧边槽(10),所述基岛(5)上通过焊料(2)设置有芯片(1),所述芯片(1)通过焊线(7)与内引脚(621)电性连接,所述芯片(1)、基岛(5)、内引脚(621)、焊线(7)及部分中间引脚(621)包覆在塑封料(8)之内,所述基岛侧边槽(9)和所述引脚侧边槽(10)内填充有所述塑封料(8),左右两侧的键合压爪从侧面插入基岛侧边槽、引脚侧边槽内,从而完成铝线键合时键合压爪的非表面压合固定框架。
2.一种半导体封装结构的键合压合方法,其特征在于所述方法包括与以下步骤:
取一引线框架,所述引线框架基岛与内引脚左右两侧开设有开槽,在基岛表面通过焊料贴装芯片,左右两侧的键合压爪从侧面插入开槽内,从而完成铝线键合时键合压爪的非表面压合固定框架。
3.根据权利要求2所述的一种半导体封装结构的键合压合方法,其特征在于:侧面的开槽为斜坡式结构。
4.根据权利要求3所述的一种半导体封装结构的键合压合方法,其特征在于:键合压爪斜向插入斜坡式开槽内。
5.根据权利要求2所述的一种半导体封装结构的键合压合方法,其特征在于:侧面的开槽为方形结构。
6.根据权利要求5所述的一种半导体封装结构的键合压合方法,其特征在于:键合压爪先横向直插入方形开槽内,再垂直向下压合。
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CN102324391A (zh) * | 2011-09-19 | 2012-01-18 | 杰群电子科技(东莞)有限公司 | 无引脚半导体引线框架焊铝箔方法 |
CN202948916U (zh) * | 2012-08-31 | 2013-05-22 | 杰群电子科技(东莞)有限公司 | 一种防止芯片压伤的半导体引线框架 |
CN206595249U (zh) * | 2017-02-23 | 2017-10-27 | 江苏盐芯微电子有限公司 | 承载大电流的sop器件封装结构 |
CN109904077A (zh) * | 2019-01-21 | 2019-06-18 | 深圳赛意法微电子有限公司 | 多管脚半导体产品的封装方法 |
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CN102324391A (zh) * | 2011-09-19 | 2012-01-18 | 杰群电子科技(东莞)有限公司 | 无引脚半导体引线框架焊铝箔方法 |
CN202948916U (zh) * | 2012-08-31 | 2013-05-22 | 杰群电子科技(东莞)有限公司 | 一种防止芯片压伤的半导体引线框架 |
CN206595249U (zh) * | 2017-02-23 | 2017-10-27 | 江苏盐芯微电子有限公司 | 承载大电流的sop器件封装结构 |
CN109904077A (zh) * | 2019-01-21 | 2019-06-18 | 深圳赛意法微电子有限公司 | 多管脚半导体产品的封装方法 |
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