CN110993561A - 一种防止金属连接线断连的方法 - Google Patents
一种防止金属连接线断连的方法 Download PDFInfo
- Publication number
- CN110993561A CN110993561A CN201911191046.5A CN201911191046A CN110993561A CN 110993561 A CN110993561 A CN 110993561A CN 201911191046 A CN201911191046 A CN 201911191046A CN 110993561 A CN110993561 A CN 110993561A
- Authority
- CN
- China
- Prior art keywords
- layer
- photoresist
- metal
- photoresist layer
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 54
- 239000002184 metal Substances 0.000 title claims abstract description 54
- 238000000034 method Methods 0.000 title claims abstract description 25
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 72
- 238000005530 etching Methods 0.000 claims abstract description 43
- 239000011248 coating agent Substances 0.000 claims abstract description 16
- 238000000576 coating method Methods 0.000 claims abstract description 16
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims abstract description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 4
- 238000000151 deposition Methods 0.000 claims abstract description 4
- 239000000758 substrate Substances 0.000 claims abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- 235000012239 silicon dioxide Nutrition 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 238000001704 evaporation Methods 0.000 claims description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 4
- 238000005406 washing Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 127
- 238000010586 diagram Methods 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 239000002356 single layer Substances 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 230000003247 decreasing effect Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000001883 metal evaporation Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/16—Coating processes; Apparatus therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
本发明公开一种防止金属连接线断连的方法,其中方法包括如下步骤:在带有第一金属层的砷化镓衬底上沉积介质层;涂布第一光阻层,经对准、显影去除待蚀刻处的第一光阻层,并涂布微缩光阻,进行烘烤;蚀刻介质层,形成凹槽,并去除第一光阻层;涂布第二光阻层,经对准、显影去除凹槽上待蚀刻处的第二光阻层,所述对准显影第二光阻层的宽度小于凹槽宽度;涂布微缩光阻,并进行烘烤;蚀刻剩余介质层,并去除第二光阻层。上述技术方案在实际作业中避免了后续沉积金属时,金属层出现断层或薄层的问题,同时也降低了制程成本。
Description
技术领域
本发明涉及半导体制作领域,尤其涉及一种防止金属连接线断连的方法。
背景技术
常用介质膜(如:二氧化硅、氮化硅)作为杂质选择扩散的掩蔽膜、电容器的介电材料、器件或导线的电绝缘和隔离、器件的表面保护和钝化作用等。在半导体行业,大多采用湿法蚀刻工艺或干法蚀刻工艺对二氧化硅或氮化硅膜进行蚀刻。湿法蚀刻是各向同性的,蚀刻液在做纵向蚀刻时,侧向的蚀刻也同时发生;蚀刻时间过短,易造成底部介质膜的残留;蚀刻时间过长,易造成图形的咬边现象;干法蚀刻方向性较强,在进行纵向蚀刻时,横向蚀刻较小,薄膜蚀刻的蚀刻角度较大,垂直性好。二氧化硅或氮化硅蚀刻后,常需在其上用PVD工艺沉积上层金属以实现上下金属层之间的导通。但采用湿法蚀刻工艺,由于咬边现象,将会出现金属层的断层或薄层;采用干法蚀刻工艺,由于蚀刻角度较大,将会出现金属层的断层或薄层。所以在现有技术中,操作员一般沉积较厚的金属膜来避免金属断层或层薄,如此便造成金属的用量和成本的增加。
发明内容
为此,需要提供一种防止金属连接线断连的方法,解决金属层的断层或薄层问题。
为实现上述目的,发明人提供了一种防止金属连接线断连的方法,包括如下步骤:
在带有第一金属层的砷化镓衬底上沉积介质层;
涂布第一光阻层,经对准、显影去除待蚀刻处的第一光阻层,并涂布微缩光阻,进行烘烤,形成弧形的断面结构;
蚀刻介质层,形成凹槽,并去除第一光阻层;
涂布第二光阻层,经对准、显影去除凹槽上待蚀刻处的第二光阻层,所述对准显影第二光阻层的宽度小于凹槽宽度;
涂布微缩光阻,并进行烘烤,形成弧形的断面结构;
蚀刻剩余介质层,并去除第二光阻层。
进一步地,在去除第二光阻层步骤后还包括:
蒸镀第二金属层,所述第二金属层与第一金属层相连接。
进一步地,在进行两个烘烤步骤前,还包括步骤:进行水清洗。
进一步地,所述第一光阻层、第二光阻层为正光阻。
进一步地,所述凹槽深度为所述介质层的一半。
进一步地,所述介质层为一氮化硅或二氧化硅。
区别于现有技术,上述技术方案经过二次蚀刻,减小每层断面高度,通过分层蚀刻克服现有技术中蒸镀金属时,出现的断层或薄层的问题。本发明先以第一光阻层、微缩光阻为掩膜,进行第一次的蚀刻,蚀刻介质层的深度为所沉积介质层的部分厚度,并去除第一光阻层;再次蚀刻则是以第二光阻层、微缩光阻为掩膜进行第二次的蚀刻,此次蚀刻将去除介质层剩余部分,使位于介质层下的第一金属层暴露出来。需要说明的是,第二次的蚀刻的宽度小于第一次蚀刻的宽度,具体的,逐次逐层减小的蚀刻宽度将使所述介质层出现上大下小的梯级通孔。同时在上述所涂布的第一光阻层、第二光阻层的厚度均为到之间,其在蚀刻时将保护其余未蚀刻区域介质层的完好性。在实际作业中,为了防止金属断层或薄层的情况发生,发明将原先的一层断面结构,通过阶梯状的过度改为二层断面结构,二层断面结构中每层断面高度之和等于原先单层断面高度;进一步地,通过对微缩光阻烘烤,将原先垂直的断面结构,修整为弧形的断面结构,以至于在蚀刻介质层时,所述介质层的断面也将呈现弧形的断面结构。需要说明的是,弧形的断面结构避免了原先沉积金属时,金属对所述介质层垂直断面处的附着力不够,致使竖直方向上的金属层较少或是没有。具体的,发明人将断面高度转换为宽度,意增加金属在介质层的附着力,提升沉积金属的厚度。上述技术方案在实际作业中避免了后续沉积金属时,金属层出现断层或薄层的问题,同时也降低了成本。
附图说明
图1为介质层、第一金属层结构示意图;
图2为第一光阻层、微缩光阻的结构示意图;
图3为蚀刻第一光阻层、介质层的结构示意图;
图4为凹槽的结构示意图;
图5为蚀刻第二光阻层、介质层的结构示意图;
图6为介质层的结构示意图;
图7为第二金属层的结构示意图;
附图标记说明:
1、第一金属层;
2、第一光阻层;
3、介质层;
301、凹槽;
4、第二光阻层;
5、第二金属层。
具体实施方式
为详细说明技术方案的技术内容、构造特征、所实现目的及效果,以下结合具体实施例并配合附图详予说明。
请参阅图1至6,在本实施例中,提供了一种防止金属连接线断连的方法,包括如下步骤:在带有第一金属层1的砷化镓衬底上沉积介质层3,所述介质层3可以为一氮化硅或者二氧化硅;涂布第一光阻层2,经对准、显影去除待蚀刻处的第一光阻层2,并涂布微缩光阻,进行烘烤;蚀刻介质层3,形成凹槽301,优选的,所述凹槽301深度为所述介质层3的一半,并去除第一光阻层2,需要说明的是,介质层3与第一光阻层2是同时蚀刻,蚀刻介质层3的同时所述第一光阻层2也将变薄;涂布第二光阻层4,经对准、显影去除凹槽301上待蚀刻处的第二光阻层4,所述对准显影第二光阻层4的宽度小于凹槽301底部宽度,使第二次的蚀刻的宽度小于第一次蚀刻的宽度;涂布微缩光阻,并进行烘烤;蚀刻剩余介质层3,并去除第二光阻层4,需要说明的是,剩余的介质层3与第二光阻层4也是同时蚀刻,蚀刻介质层3的同时所述第二光阻层4也将变薄。上述技术方案经过二次蚀刻,通过分层蚀刻克服现有技术中蒸镀金属时,因原先单层层断面过高,出现的断层或薄层的问题。本发明先以第一光阻层2、微缩光阻为掩膜,进行第一次的蚀刻,蚀刻介质层3的深度为所沉积介质层3的一半的厚度,并去除第一光阻层2;再次蚀刻则是以第二光阻层4、微缩光阻为掩膜进行第二次的蚀刻,此次蚀刻将去除介质层3剩余部分,使位于介质层3下的第一金属层1暴露出来。需要说明的是,因所述对准显影第二光阻层4的宽度小于凹槽301底部宽度,第二次的蚀刻的宽度将小于第一次蚀刻的宽度,具体的,逐次逐层减小的蚀刻宽度将使所述介质层3出现上大下小的梯级通孔,在断面高度较高的情况下还可以多次蚀刻,每次蚀刻所对准显影的光阻区域都将比上一次对准显影区域小。同时在上述所涂布的第一光阻层2、第二光阻层4的厚度均为到之间,其在蚀刻时将保护其余未蚀刻区域介质层3的完好性。在实际作业中,为了防止金属断层或薄层的情况发生,发明将原先的一层断面结构,通过阶梯状的过度改为二层断面结构,二层断面结构中每层断面高度之和等于原先单层断面高度;进一步地,通过对微缩光阻烘烤,将原先垂直的第一光阻层2、第二光阻层4的断面结构,改为弧形的断面结构,以至于在蚀刻介质层3时,所述介质层3的断面也将呈现弧形的断面结构。需要说明的是,弧形的断面结构避免了原先沉积金属时,金属对所述介质层3垂直断面处的附着力不够,致使竖直方向上的金属层较少或是没有。具体的,发明人将断面高度转换为宽度,意增加金属在介质层3的附着力,提升沉积金属的厚度。上述技术方案在实际作业中避免了后续沉积金属时,金属层出现断层或薄层的问题,同时也降低了制程成本。
请参阅图7,在本实施例中,在去除第二光阻层4步骤后还包括:蒸镀第二金属层5,所述第二金属层5与第一金属层1相连接。第二金属层5的蒸镀保证了上下层电路的相互连通。
在本实施例中,在进行两个烘烤步骤前,还包括步骤:进行水清洗。水清洗将去除微缩光阻上的多余杂质,提高半导体制程的精确性,同时也将避免晶圆的损毁。在本实施例中,所述第一光阻层2、第二光阻层4为正光阻。正光阻的曝光、显影可以使得所制作出来的开口宽度由上至下是逐渐减小的。
需要说明的是,尽管在本文中已经对上述各实施例进行了描述,但并非因此限制本发明的专利保护范围。因此,基于本发明的创新理念,对本文所述实施例进行的变更和修改,或利用本发明说明书及附图内容所作的等效结构或等效流程变换,直接或间接地将以上技术方案运用在其他相关的技术领域,均包括在本发明的专利保护范围之内。
Claims (6)
1.一种防止金属连接线断连的方法,其特征在于,包括如下步骤:
在带有第一金属层的砷化镓衬底上沉积介质层;
涂布第一光阻层,经对准、显影去除待蚀刻处的第一光阻层,并涂布微缩光阻,进行烘烤,形成弧形的断面结构;
蚀刻介质层,形成凹槽,并去除第一光阻层;
涂布第二光阻层,经对准、显影去除凹槽上待蚀刻处的第二光阻层,所述对准显影第二光阻层的宽度小于凹槽宽度;
涂布微缩光阻,并进行烘烤,形成弧形的断面结构;
蚀刻剩余介质层,并去除第二光阻层。
2.如权利要求1所述的一种防止金属连接线断连的方法,其特征在于,在去除第二光阻层步骤后还包括:
蒸镀第二金属层,所述第二金属层与第一金属层相连接。
3.如权利要求1所述的一种防止金属连接线断连的方法,其特征在于,在进行两个烘烤步骤前,还包括步骤:进行水清洗。
4.如权利要求1所述的一种防止金属连接线断连的方法,其特征在于,所述第一光阻层、第二光阻层为正光阻。
5.如权利要求1所述的一种防止金属连接线断连的方法,其特征在于,所述凹槽深度为所述介质层的一半。
6.如权利要求1所述的一种防止金属连接线断连的方法,其特征在于,所述介质层为一氮化硅或二氧化硅。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201911191046.5A CN110993561A (zh) | 2019-11-28 | 2019-11-28 | 一种防止金属连接线断连的方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201911191046.5A CN110993561A (zh) | 2019-11-28 | 2019-11-28 | 一种防止金属连接线断连的方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN110993561A true CN110993561A (zh) | 2020-04-10 |
Family
ID=70087970
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201911191046.5A Pending CN110993561A (zh) | 2019-11-28 | 2019-11-28 | 一种防止金属连接线断连的方法 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN110993561A (zh) |
Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02125614A (ja) * | 1988-11-04 | 1990-05-14 | Nec Corp | 半導体装置の製造方法 |
US20020047209A1 (en) * | 2000-10-20 | 2002-04-25 | Lee Suk Joo | Method for forming contact hole for dual damascene interconnection of semiconductor device and resultant structure |
US20030207180A1 (en) * | 2002-05-03 | 2003-11-06 | Nanya Technology Corporation | Dual damascene process using a single photo mask |
US20040121588A1 (en) * | 2002-12-23 | 2004-06-24 | Choi Jae Sung | Method of forming dual damascene pattern in semiconductor device |
CN1825189A (zh) * | 2005-02-23 | 2006-08-30 | 中华映管股份有限公司 | 平面显示器的阶梯式接触窗的制作方法 |
KR20070034294A (ko) * | 2005-09-23 | 2007-03-28 | 매그나칩 반도체 유한회사 | 듀얼 다마신 공정을 이용한 비아홀 형성방법 |
CN101097860A (zh) * | 2007-06-28 | 2008-01-02 | 西安电子科技大学 | 化合物半导体微波大功率器件中的空气桥制作方法 |
KR100800892B1 (ko) * | 2006-08-16 | 2008-02-04 | 동부일렉트로닉스 주식회사 | 반도체 소자의 금속 배선 형성방법 |
CN101266913A (zh) * | 2007-03-12 | 2008-09-17 | 旺宏电子股份有限公司 | 增进图案均匀度的方法 |
CN104882373A (zh) * | 2015-04-24 | 2015-09-02 | 石以瑄 | 晶体管t形栅的制造方法 |
CN108565213A (zh) * | 2018-01-26 | 2018-09-21 | 成都海威华芯科技有限公司 | 一种高电子迁移率晶体管t形栅的制造方法 |
-
2019
- 2019-11-28 CN CN201911191046.5A patent/CN110993561A/zh active Pending
Patent Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02125614A (ja) * | 1988-11-04 | 1990-05-14 | Nec Corp | 半導体装置の製造方法 |
US20020047209A1 (en) * | 2000-10-20 | 2002-04-25 | Lee Suk Joo | Method for forming contact hole for dual damascene interconnection of semiconductor device and resultant structure |
US20030207180A1 (en) * | 2002-05-03 | 2003-11-06 | Nanya Technology Corporation | Dual damascene process using a single photo mask |
US20040121588A1 (en) * | 2002-12-23 | 2004-06-24 | Choi Jae Sung | Method of forming dual damascene pattern in semiconductor device |
CN1825189A (zh) * | 2005-02-23 | 2006-08-30 | 中华映管股份有限公司 | 平面显示器的阶梯式接触窗的制作方法 |
KR20070034294A (ko) * | 2005-09-23 | 2007-03-28 | 매그나칩 반도체 유한회사 | 듀얼 다마신 공정을 이용한 비아홀 형성방법 |
KR100800892B1 (ko) * | 2006-08-16 | 2008-02-04 | 동부일렉트로닉스 주식회사 | 반도체 소자의 금속 배선 형성방법 |
CN101266913A (zh) * | 2007-03-12 | 2008-09-17 | 旺宏电子股份有限公司 | 增进图案均匀度的方法 |
CN101097860A (zh) * | 2007-06-28 | 2008-01-02 | 西安电子科技大学 | 化合物半导体微波大功率器件中的空气桥制作方法 |
CN104882373A (zh) * | 2015-04-24 | 2015-09-02 | 石以瑄 | 晶体管t形栅的制造方法 |
CN108565213A (zh) * | 2018-01-26 | 2018-09-21 | 成都海威华芯科技有限公司 | 一种高电子迁移率晶体管t形栅的制造方法 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10714341B2 (en) | Reactive ion etching assisted lift-off processes for fabricating thick metallization patterns with tight pitch | |
CN107481969B (zh) | 一种通孔的形成方法 | |
CN109243971B (zh) | 一种半导体器件介质膜低角度蚀刻方法 | |
CN103646883B (zh) | 一种铝衬垫制备方法 | |
US7196002B2 (en) | Method of making dual damascene with via etch through | |
CN110993561A (zh) | 一种防止金属连接线断连的方法 | |
KR100187666B1 (ko) | 반도체 소자의 텅스텐 플러그 형성방법 | |
KR20100078947A (ko) | 반도체 소자의 제조방법 | |
JPH09129730A (ja) | 半導体装置の製造方法 | |
KR100688700B1 (ko) | 반도체 소자 제조 방법 | |
KR100807026B1 (ko) | 반도체 장치 제조 방법 | |
CN102376567B (zh) | 金属刻蚀方法 | |
KR100854209B1 (ko) | 반도체 장치 제조 방법 | |
KR100650902B1 (ko) | 반도체 금속 배선 및 그 제조방법 | |
KR100313529B1 (ko) | 반도체소자의 컨택 형성방법 | |
KR0172467B1 (ko) | 금속배선 마스크의 얼라인먼트 키 형성을 위한 반도체소자 제조방법 | |
KR20020009426A (ko) | 반도체장치의 제조방법 | |
KR100763099B1 (ko) | 반도체 소자의 금속 배선 형성 방법 | |
KR100609222B1 (ko) | 반도체 제조 공정에서 미세 금속 배선 제작방법 | |
KR100526470B1 (ko) | 플래쉬 메모리의 게이트 형성방법 | |
KR100881082B1 (ko) | 듀얼 다마신 공정을 이용한 배선 형성 방법 | |
KR100607368B1 (ko) | 반도체소자의 콘택홀 제조 방법 | |
CN117976620A (zh) | 半导体器件及其形成方法 | |
KR100271402B1 (ko) | 반도체소자의접촉구형성방법 | |
CN111354643A (zh) | 存储器的制造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
RJ01 | Rejection of invention patent application after publication |
Application publication date: 20200410 |
|
RJ01 | Rejection of invention patent application after publication |