KR100881082B1 - 듀얼 다마신 공정을 이용한 배선 형성 방법 - Google Patents
듀얼 다마신 공정을 이용한 배선 형성 방법 Download PDFInfo
- Publication number
- KR100881082B1 KR100881082B1 KR1020020057073A KR20020057073A KR100881082B1 KR 100881082 B1 KR100881082 B1 KR 100881082B1 KR 1020020057073 A KR1020020057073 A KR 1020020057073A KR 20020057073 A KR20020057073 A KR 20020057073A KR 100881082 B1 KR100881082 B1 KR 100881082B1
- Authority
- KR
- South Korea
- Prior art keywords
- layer
- etch stop
- etch
- cell region
- forming
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 37
- 230000009977 dual effect Effects 0.000 title description 18
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 15
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 15
- 238000012544 monitoring process Methods 0.000 claims abstract description 14
- 229910052751 metal Inorganic materials 0.000 claims description 16
- 239000002184 metal Substances 0.000 claims description 16
- 238000005530 etching Methods 0.000 claims description 9
- 230000004888 barrier function Effects 0.000 claims description 8
- 239000010410 layer Substances 0.000 description 46
- 229920002120 photoresistant polymer Polymers 0.000 description 12
- 238000000151 deposition Methods 0.000 description 6
- 239000004020 conductor Substances 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 4
- 238000001465 metallisation Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000006117 anti-reflective coating Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 238000000149 argon plasma sintering Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000002310 reflectometry Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims (2)
- 셀 영역과 에치 모니터링 박스 영역에 장벽층, 제1 저유전체막 및 식각 정지막을 차례로 형성하는 단계;상기 에치 모니터링 박스 영역에만 남도록 상기 셀 영역의 식각 정지막을 제거하는 단계;셀 영역의 식각 정지막이 제거된 결과물 상에 제2 저유전체막 및 하드 마스크를 형성하는 단계;셀 영역의 상기 하드 마스크 및 제2 저유전체막을 식각하여 상기 셀 영역에 제1 비아홀을 형성하는 단계;상기 셀 영역 및 에치 모니터링 박스 영역의 제2 저유전체막을 식각하여, 상기 셀 영역 및 에치 모니터링 박스 영역에 제2 비아홀을 형성하는 단계; 및상기 제1 및 제2 비아홀을 금속으로 매립하여 배선층을 형성하는 단계를 포함하는 것을 특징으로 하는 듀얼 다마신 공정을 이용한 배선 형성 방법.
- 제 1항에 있어서,상기 장벽층과 식각 정지막 및 하드마스크는 실리콘 질화막으로 형성하는 것을 특징으로 하는 듀얼 다마신 공정을 이용한 배선 형성 방법.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020020057073A KR100881082B1 (ko) | 2002-09-18 | 2002-09-18 | 듀얼 다마신 공정을 이용한 배선 형성 방법 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020020057073A KR100881082B1 (ko) | 2002-09-18 | 2002-09-18 | 듀얼 다마신 공정을 이용한 배선 형성 방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20040025220A KR20040025220A (ko) | 2004-03-24 |
KR100881082B1 true KR100881082B1 (ko) | 2009-01-30 |
Family
ID=37328175
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020020057073A KR100881082B1 (ko) | 2002-09-18 | 2002-09-18 | 듀얼 다마신 공정을 이용한 배선 형성 방법 |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR100881082B1 (ko) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20020009211A (ko) * | 2000-07-25 | 2002-02-01 | 윤종용 | 듀얼 다마신 배선구조의 반도체 소자 및 그 제조방법 |
-
2002
- 2002-09-18 KR KR1020020057073A patent/KR100881082B1/ko active IP Right Grant
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20020009211A (ko) * | 2000-07-25 | 2002-02-01 | 윤종용 | 듀얼 다마신 배선구조의 반도체 소자 및 그 제조방법 |
Also Published As
Publication number | Publication date |
---|---|
KR20040025220A (ko) | 2004-03-24 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7119006B2 (en) | Via formation for damascene metal conductors in an integrated circuit | |
KR100349680B1 (ko) | 듀얼 다마신 배선의 형성 방법 | |
KR100460771B1 (ko) | 듀얼다마신 공정에 의한 다층 배선의 형성 방법 | |
KR100268459B1 (ko) | 반도체 장치의 콘택 플러그 형성 방법 | |
US7135783B2 (en) | Contact etching utilizing partially recessed hard mask | |
KR100881082B1 (ko) | 듀얼 다마신 공정을 이용한 배선 형성 방법 | |
KR100515058B1 (ko) | 금속 패턴을 갖는 반도체 소자의 형성방법 | |
KR100230733B1 (ko) | 반도체 소자의 다층 금속 배선 형성 방법 | |
US20020001877A1 (en) | Interconnect formation in a semiconductor device | |
KR100568794B1 (ko) | 반도체 소자의 금속 배선 형성 방법 | |
KR100403351B1 (ko) | 듀얼 다마신 공정에서의 식각 모니터링 박스 형성방법 | |
US7524760B2 (en) | Semiconductor device and method for manufacturing the same | |
KR100609036B1 (ko) | 반도체 소자의 콘택홀 형성방법 | |
KR100857989B1 (ko) | 반도체 소자의 금속 배선 형성 방법 | |
KR100379530B1 (ko) | 반도체 소자의 듀얼 다마신 형성방법 | |
KR100235960B1 (ko) | 반도체소자의 도전 라인 형성방법 | |
KR100269662B1 (ko) | 반도체 장치의 도전체 플러그 형성 방법 | |
KR100383084B1 (ko) | 반도체 소자의 플러그 형성 방법 | |
KR100523655B1 (ko) | 반도체 소자의 듀얼 다마신 패턴 형성 방법 | |
KR930011503B1 (ko) | 반도체장치의 금속배선 형성방법 | |
KR100799123B1 (ko) | 반도체 소자의 높은 종횡비를 갖는 콘택 플러그 형성 방법 | |
KR100741593B1 (ko) | 상감법에 의한 구리 금속배선의 형성방법 | |
KR20050116483A (ko) | 반도체소자의 콘택홀 형성 방법 | |
JPH1174355A (ja) | 半導体装置の製造方法 | |
KR20000045377A (ko) | 반도체소자의 도전배선 형성방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
N231 | Notification of change of applicant | ||
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20121210 Year of fee payment: 5 |
|
FPAY | Annual fee payment |
Payment date: 20131217 Year of fee payment: 6 |
|
FPAY | Annual fee payment |
Payment date: 20141222 Year of fee payment: 7 |
|
FPAY | Annual fee payment |
Payment date: 20151217 Year of fee payment: 8 |
|
FPAY | Annual fee payment |
Payment date: 20161220 Year of fee payment: 9 |
|
FPAY | Annual fee payment |
Payment date: 20171218 Year of fee payment: 10 |
|
FPAY | Annual fee payment |
Payment date: 20181218 Year of fee payment: 11 |
|
FPAY | Annual fee payment |
Payment date: 20191217 Year of fee payment: 12 |