CN110892530B - 集成光学系统 - Google Patents

集成光学系统 Download PDF

Info

Publication number
CN110892530B
CN110892530B CN201880047604.8A CN201880047604A CN110892530B CN 110892530 B CN110892530 B CN 110892530B CN 201880047604 A CN201880047604 A CN 201880047604A CN 110892530 B CN110892530 B CN 110892530B
Authority
CN
China
Prior art keywords
micro
substrate
layer
light emitting
emitting micro
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201880047604.8A
Other languages
English (en)
Other versions
CN110892530A (zh
Inventor
格拉姆雷扎·查济
埃桑诺拉·法蒂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Vuereal Inc
Original Assignee
Vuereal Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from CA2879465A external-priority patent/CA2879465A1/en
Priority claimed from CA2879627A external-priority patent/CA2879627A1/en
Priority claimed from CA2880718A external-priority patent/CA2880718A1/en
Priority claimed from CA2883914A external-priority patent/CA2883914A1/en
Priority claimed from CA2890398A external-priority patent/CA2890398A1/en
Priority claimed from CA2936473A external-priority patent/CA2936473A1/en
Priority to CN202311598175.2A priority Critical patent/CN117613166A/zh
Application filed by Vuereal Inc filed Critical Vuereal Inc
Publication of CN110892530A publication Critical patent/CN110892530A/zh
Publication of CN110892530B publication Critical patent/CN110892530B/zh
Application granted granted Critical
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40—Materials therefor
    • H01L33/42—Transparent materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40—Materials therefor
    • H01L33/405—Reflective materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/50—Wavelength conversion elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/58—Optical field-shaping elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68318—Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
    • H01L2221/68322—Auxiliary support including means facilitating the selective separation of some of a plurality of devices from the auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68354—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support diced chips prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68363—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08151—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/08221—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/08225—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/32235—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80003—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/80004—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding involving a temporary auxiliary member not forming part of the bonding apparatus being a removable or sacrificial coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80003—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/80006—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8038—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/80385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80905—Combinations of bonding methods provided for in at least two different groups from H01L2224/808 - H01L2224/80904
    • H01L2224/80907—Intermediate bonding, i.e. intermediate bonding step for temporarily bonding the semiconductor or solid-state body, followed by at least a further bonding step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/83002—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus being a removable or sacrificial coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/83005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83905—Combinations of bonding methods provided for in at least two different groups from H01L2224/838 - H01L2224/83904
    • H01L2224/83907—Intermediate bonding, i.e. intermediate bonding step for temporarily bonding the semiconductor or solid-state body, followed by at least a further bonding step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/9202—Forming additional connectors after the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0016—Processes relating to electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0058—Processes relating to semiconductor body packages relating to optical field-shaping elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/58—Optical field-shaping elements
    • H01L33/60—Reflective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Abstract

本发明涉及用于将微装置集成于系统(受体)衬底中或在转移之后改进所述微装置的性能的后处理步骤。可使用例如反射层、填料、黑色矩阵或其它层的额外结构的后处理步骤以改进所产生的LED光的输出耦合或限制。在另一实例中，可使用电介质层及金属层以将光电薄膜装置与经转移微装置集成于所述系统衬底中。在另一实例中，将色彩转换层集成于所述系统衬底中以产生来自所述微装置的不同输出。

Description

集成光学系统
相关申请案的交叉参考
此申请案主张2017年7月18日申请的序列号为15/653,120的美国专利申请案的优先权，所述申请案的全部内容以引用的方式并入本文中。
技术领域
本发明涉及将经转移微装置系统集成到受体衬底上。更具体来说，本发明涉及用于在转移到受体衬底中之后增强微装置的性能的后处理步骤，包含光学结构的显影、光电薄膜装置的集成、色彩转换层的添加及施体衬底上的装置的恰当图案化。
背景技术
本发明的目的是通过提供集成于相同受体衬底上的发光微装置及薄膜光电发光装置而克服现有技术的缺点。
发明内容
因此，本发明涉及一种集成光学系统，其包括多个像素，每一像素包括：
受体衬底；
发光微装置，其集成于所述受体衬底上；
平坦化或堤岸区，其包围所述微装置；及
薄膜发光光电装置，其至少一部分安装于所述平坦化或堤岸区上。
附图说明
参考表示本发明的优选实施例的附图更详细描述本发明，其中：
图1展示具有接触垫的受体衬底及附接到受体衬底的经转移微装置的阵列。
图2A展示具有接触垫的受体衬底、附接到受体衬底的经转移微装置的阵列及顶部上的保形电介质及反射层。
图2B展示具有接触垫的受体衬底、附接到受体衬底的经转移微装置的阵列及经图案化的保形电介质及反射层。
图2C展示具有接触垫的受体衬底、附接到受体衬底的经转移微装置的阵列、经图案化的保形电介质及反射层及形成于相邻微装置之间的黑色矩阵层。
图3A展示具有接触垫的受体衬底、附接到受体衬底的经转移微装置的阵列、经图案化的保形电介质及反射层、黑色矩阵层及沉积于衬底上的透明导电层。
图3B展示具有附接到其经转移微装置的集成阵列的受体衬底及用于光输出耦合增强的光学反射组件。
图3C展示具有附接到其经转移微装置的集成阵列的受体衬底及用于光输出耦合增强的凹形接触垫。
图3D展示具有以底部发射配置附接到其经转移微装置的集成阵列的受体衬底。
图3E展示具有附接到其经转移微装置的集成阵列的受体衬底。
图4A展示具有经转移微装置的受体衬底、保形电介质层及经连接反射层。
图4B展示具有经转移微装置、保形电介质层、经连接反射层的受体衬底及沉积于衬底上的透明导电层。
图5展示具有经转移微装置的受体衬底及界定像素(或子像素)的经图案化填料。
图6A展示覆盖至少一个像素中的所有子像素(例如，覆盖由两个子像素组成的像素的两个子像素)的像素化填料结构。
图6B展示由两个子像素组成的像素、经图案化以界定所述像素的填料层及所述像素周围的经图案化保形电介质及反射层。
图6C展示由两个子像素组成的像素、经图案化以界定所述像素的填料层、所述像素周围的经图案化保形电介质及反射层以及卷绕所述像素的黑色矩形层。
图6D展示由两个子像素组成的像素、经图案化以界定所述像素的填料层、所述像素周围的经图案化保形电介质及反射层、卷绕所述像素的黑色矩形层及沉积于衬底上的透明导电层。
图6E展示由两个子像素组成的像素，其具有受体衬底上的反射光学组件以用于更好光输出耦合。
图6F展示由两个子像素组成的像素，其具有受体衬底上的凹形接触垫。
图6G展示具有底部发射配置的由两个子像素组成的像素。
图6H展示具有底部发射配置的由两个子像素组成的像素、共同顶部电极及侧反射器。
图7展示具有两个接触垫的受体衬底。
图8展示具有接合到接触垫中的一者的经转移微装置的受体衬底。
图9展示在混合结构中将经转移微装置与光电薄膜装置集成。
图10展示在混合结构中将经转移微装置与光电薄膜装置集成的另一实例。
图11展示在具有共同顶部电极的混合结构中将经转移微装置与光电薄膜装置集成的实例。
图12展示在具有顶部及底部透明电极两者的双表面混合结构中将经转移微装置与光电薄膜装置集成的实施例。
图13A展示系统衬底及具有薄膜光电装置的集成微装置的另一实施例。
图13B展示系统衬底及与具有薄膜光电装置的集成微装置的另一实施例。
图14A展示系统衬底及具有两个薄膜光电装置的集成微装置的实施例。
图14B展示系统衬底及具有两个薄膜光电装置及受体衬底上的反射层的集成微装置的实施例。
图14C及图14D展示微LED及光电装置的实例，其中光通过光电装置。
图14E、图14F及图14G展示与系统衬底上的光电装置集成的微LED的另一实例。
图14H及图14I展示与系统衬底上的光电装置及彩色滤光器集成的微LED的另一实例。
图14J展示与系统衬底上的光电装置及彩色滤光器集成的微LED的另一实例。
图15说明系统衬底及微装置衬底的横截面。
图16展示转移工艺中的系统衬底及微装置衬底的对准步骤。
图17展示转移工艺中的系统衬底及微装置衬底的接合步骤。
图18展示转移工艺中的系统衬底及微装置衬底的微装置衬底移除步骤。
图19展示转移工艺中的系统衬底及微装置衬底的牺牲层移除步骤。
图20展示转移工艺中的系统衬底及微装置衬底的共同电极形成步骤。
图21是具有填料层的微装置衬底的横截面。
图22是使用支撑层覆盖的微装置衬底的横截面。
图23展示转移工艺中的微装置衬底的微装置衬底移除步骤。
图24A及图24B展示转移工艺中的微装置衬底的牺牲层移除步骤。还展示具有接触垫的系统衬底。
图25展示转移工艺中的系统衬底及微装置衬底的接合步骤。
图26A及图26B展示转移工艺中的微装置衬底的支撑层移除步骤。还展示具有接触垫及经转移微装置的系统衬底。
图27是使用填料层覆盖的微装置衬底的横截面。
图28A及图28B是具有衬底中的导通孔及牺牲层的微装置衬底的横截面。
图29是具有衬底中的导通孔及由绝缘层覆盖的牺牲层的微装置衬底的横截面。
图30是具有衬底中的经导电层填充的导通孔及牺牲层的微装置衬底的横截面。
图31是具有共同顶部电极的微装置衬底的横截面。
图32是具有共同顶部电极的集成系统衬底的横截面。
图33A展示施体衬底上的微装置的二维布置。
图33B是系统衬底及微装置衬底的横截面。
图34是经接合系统衬底及微装置衬底的横截面。
图35展示转移工艺中的微装置衬底的激光剥离步骤。
图36是选择性转移工艺之后的系统衬底及微装置衬底的横截面。
图37是具有共同顶部电极的集成系统衬底。
图38A及38B是具有拥有不同高度的微装置的微装置衬底的横截面。
图39是具有填料层的微装置衬底的横截面。
图40展示转移工艺中的具有夹持机构的系统衬底及微装置衬底的对准步骤。
图41A展示施体衬底上的微装置的二维布置。
图41B是具有不同节距的系统衬底及微装置衬底的横截面。
图42展示具有不同节距的系统衬底及微装置衬底的选择性微装置转移工艺。
图43是具有不同节距的系统衬底及微装置衬底的横截面。
图44展示具有不同节距的系统衬底及微装置衬底的选择性微装置转移工艺。
图45展示集成微装置衬底。
图46A及图46B展示微装置到具有平坦化层、共同顶部电极、堤岸结构及色彩转换元件的系统衬底的转移工艺。
图47展示具有用于界定像素的色彩的色彩转换的结构。
图48展示具有由堤岸层分离的保形共同电极及色彩转换的结构。
图49展示具有由堤岸层分离的保形色彩转换的结构。
图50展示具有无堤岸层的共同电极上的色彩转换元件的结构。
图51展示具有保形共同电极及色彩转换的结构。
图52展示具有直接形成于微装置上的保形色彩转换元件的结构。
图53A及图53B展示具有用于定义像素色彩的色彩转换、平坦化层及共同透明电极的结构。
图54A及图54B展示具有用于定义像素色彩的色彩转换的结构及用于囊封的单独衬底。
图55A、图55B、图55C及图55D展示具有用于定义像素色彩的色彩转换的结构，而使用当前限制方法完成像素化。
具体实施方式
虽然结合各种实施例及实例描述本教示，但不希望本教示限于此类实施例。相反，如所属领域的技术人员将了解到，本教示涵盖各种替代及等效物。
开发基于微装置的系统的工艺包括：在施体衬底(或临时衬底)上预处理装置；将微装置从施体衬底转移到受体衬底；及后处理以实现装置功能性。预处理步骤可包含图案化及添加接合元件。转移工艺可涉及将微装置的预选定阵列接合到受体衬底，接着移除施体衬底。已针对微装置开发若干不同选择性转移工艺。在将微装置集成到受体衬底中之后，可执行额外后处理以制成所需功能连接。
在本发明中，使用发射装置以描述不同集成及后处理方法。然而，所属领域的技术人员将了解，在这些实施例中可使用其它装置(例如传感器)。例如，在传感器微装置的情况中，光学路径将类似于发射微装置，但在相反方向上。
本发明的一些实施例涉及用于改进微装置的性能的后处理步骤。例如，在一些实施例中，微装置阵列可包括微发光二极管(LED)、有机LED、传感器、固态装置、集成电路、(微机电系统)MEMS及/或其它电子组件。受体衬底可为但不限于印刷电路板(PCB)、薄膜晶体管底板、集成电路衬底或(在光学微装置(例如LED)的一个情况中)显示器的组件(例如，驱动电路底板)。在这些实施例中，除了使微装置互连之外，可使用额外结构(例如，反射层、填料、黑色矩阵或其它层)的后处理步骤来改进所产生的LED光的输出耦合。在另一实例中，可使用电介质层及金属层以将光电薄膜装置与经转移微装置集成于系统衬底中。
在一个实施例中，通过使用填料(或电介质)将像素(或子像素)的作用区域延展为大于微装置。此处，图案化填料以界定像素的作用区域(作用区域是发射光或吸收输入光的区域)。在另一实施例中，使用反射层以将光限制在作用区域内。
在一个实施例中，反射层可为微装置电极中的一者。
在另一实施例中，作用区域可包括若干子像素或像素。
作用区域的大小可比像素(子像素)区域大、小或相同。
在另一实施例中，在将微装置集成于受体衬底中之后，将薄膜光电装置沉积于受体衬底中。
在一个实施例中，针对微装置产生光学路径以通过光电装置的所有或一些层发射(吸收)光。
在另一实施例中，微装置的光学路径未通过光电装置的所有或一些层。
在一个实施例中，光电装置是薄膜装置。
在另一实施例中，使用光电装置的电极以界定像素(或子像素)的作用区域。
在另一实施例中，至少一个光电装置电极与微装置电极共享。
在一个实施例中，色彩转换材料覆盖表面且部分(或完全)包围微装置的主体。
在一个实施例中，堤岸结构分离色彩转换材料。
在另一实施例中，色彩转换材料覆盖表面(及/或部分或完全)覆盖作用区域(的主体)。
在一个实施例中，施体衬底上的微装置经图案化以匹配受体(系统)衬底中的阵列结构。在此情况中，施体衬底的部分(或全部)中的所有装置经转移到受体衬底。
在另一实施例中，在施体衬底中产生通孔(VIA)以将施体衬底上的微装置与受体衬底耦合。
在另一实施例中，施体衬底具有一个以上微装置类型且至少在一个方向上，施体衬底上的微装置类型的图案部分或完全匹配系统衬底上的对应区域(或垫)的图案。
在另一实施例中，施体衬底具有一个以上微装置类型且至少在一个方向上，施体衬底中的不同微装置类型之间的节距是系统衬底上的对应区域(或垫)的节距的倍数。
在另一实施例中，施体衬底具有一个以上微装置类型。至少在一个方向上，两个不同微装置之间的节距匹配受体(或系统)衬底上的对应区域(或垫)的节距。
在一个实施例中，施体衬底上的不同微装置类型的图案产生每一类型的二维阵列，其中不同类型的每一阵列之间的节距匹配系统衬底上的对应区域的节距。
在另一实施例中，施体衬底上的不同微装置类型的图案产生一维阵列，其中阵列的节距匹配系统衬底上的对应区域(或垫)的节距。
图1展示受体衬底100、接触垫101a及101b及微装置102a及102b，其以阵列形式附接到受体衬底100。微装置102a及102b已经转移到其上的接触垫101a及101b定位在平行于受体衬底100且安装于受体衬底100上的阵列中。微装置102a及102b从施体衬底转移且接合到接触垫101a及101b。微装置102a及102b可为通常可按平面批次制造的任何微装置，包含但不限于LED、OLED、传感器、固态装置、集成电路、MEMS及/或其它电子组件。
如在图2A中描绘，在其中微装置102a及102b为微LED的一个实施例中，在经接合的微LED 102a及102b上方形成保形电介质层201及反射层202。在一些实施例中，保形电介质层201为约0.1μm到1μm厚，且可通过数个不同薄膜沉积技术中的任一者沉积。保形电介质层201将微LED 102a及102b的侧壁与反射层202隔离。另外，电介质层201钝化且保护微LED102a及102b的侧壁。保形电介质层201还可覆盖相邻微LED装置102a及102b之间的受体衬底100的顶部表面。保形反射层202可经沉积于电介质层201上方。反射层202可为单个层或由多个层组成。各种导电材料可用作反射层202。在一些实施例中，保形反射层202可为具有高达0.5μm的总厚度的金属双层。
参考图2B，可接着通过使用(例如)光刻图案化及蚀刻而图案化电介质层201及反射层202以部分暴露微LED 102a及102b的顶部表面。在其中微LED 102a及102b集成于显示器系统的背板中(还参考图2C)的一个实施例中，可在相邻微LED 102a及102b之间且在反射层202上形成黑色矩阵203以降低环境光的反射。在一个实例中，黑色矩阵203可为树脂层(例如聚酰亚胺或聚丙烯酸)，其中已分散有黑色颜料(例如碳黑)的颗粒。在一些实施例中，黑色矩阵层203的厚度可为0.01μm到2μm。黑色矩阵层203可经图案化及蚀刻以暴露微LED102a及102b的顶部表面，如在图2C中展示。任选地，黑色矩阵203的厚度可经设计以平坦化集成衬底100。在另一实施例中，可由有机绝缘材料制成的平坦化层经形成及图案化以平坦化背板衬底。
参考图3A，可在衬底100上方保形沉积透明导电层301，从而覆盖黑色矩阵203及微LED 102a及102b的顶部表面。在一些实施例中，透明电极301可为0.1到1um厚的氧化物层，包含(但不限于)铟锡氧化物(ITO)及掺杂铝的氧化锌。在其中集成组合件是显示结构的情况中，透明电极301可为微LED装置102a及102b的共同电极。
任选地，反射层202可用作透明电极301的导电率增强剂。在此情况中，反射层202的部分可不使用黑色矩阵203或其它平坦化层覆盖，使得透明电极层301可连接到反射层202。
在图3B中展示的另一实施例中，可在衬底100上形成反射或其它类型的光学组件302以增强由微装置102a及102b产生的光的输出耦合。共同接触件301是透明的以允许光通过此层输出。这些结构可称为顶部发射结构。
参考图3C，接触垫101a及101b可经形成以具有凹形或其它形状结构以增强由微装置102a及102b产生的光的输出耦合。接触垫101a及101b的形式不限于凹形形式且可取决于微装置光发射特性而具有其它形式。
在实施例中，参考图3D，结构经设计以从衬底100输出光。在这些底部发射结构中，衬底100可为透明的且共同电极303经设计为反射性以用于更好光提取。
在图3E中展示的另一实施例中，反射层202可经延展以覆盖微装置102a及102b且还充当共同顶部电极。
参考图4A，在另一实施例中，可在形成反射层202之前沉积且图案化电介质层201，此可允许微LED 102a及102b与反射层202之间的直接接触。因此，反射层202可用作微装置102a及102b的共同顶部接触件。可使用黑色矩阵203或替代地使用平坦化层。
参考图4B，在其它实施例中，可在衬底100的顶部上沉积共同透明电极301及/或其它光学层以增强导电率及/或光输出耦合。
微光电装置的主要挑战中的一者是相邻微装置102a与102b之间的空白空间。具有此结构特性的显示系统可产生称为“纱门效应”的图像假影。在一个实施例中，微装置大小可在光学上延展以与微装置大小相同或大于微装置大小。在图5中展示的一个实施例中，在将微装置102a及102b的阵列从施体转移到受体衬底100之后，可沉积且图案化透明填料501以界定像素(或子像素)。在一个实施例中，填料501的大小可为像素(或子像素)区域中可能的较小或最大的大小。在另一实例中，填料501大小可大于像素或子像素区域。填料501可具有与系统衬底100上的像素区域不同或类似的形状。可接着应用图3及图4中提及的工艺以改进从微装置102a及102b的光提取。
参考图6A，在其中像素601包括两个子像素601a及601b的实施例中，填料501经图案化以界定像素601的作用区域(作用区域是定义为显示器从其发射光的区域)。此处，作用区域的大小可小于、大于像素(子像素)区域或与像素(子像素)区域相同。如在图6B、图6C及图6D中展示，可应用图2及图3中提及的工艺。此配置管理归因于子像素601a与601b之间的分离的边缘处的变色。
参考图6B，可在像素601周围形成电介质层201及反射层202。
还参考图6C，可在相邻像素601之间且在每一子像素601a及601b周围形成黑色矩阵203以降低环境光的反射。
参考图6D，可在衬底100的顶部上沉积透明导电层301，从而覆盖黑色矩阵203及微LED 601a及601b的顶部表面。
在图6E中展示的另一实施例中，可在衬底100上形成反射或其它光学组件602以增强由微装置601a及601b产生的光的输出耦合。共同接触件301是透明的以使光通过此层输出。这些结构可称为顶部发射结构。
参考图6F，接触垫101a及101b可经形成以具有凹形结构以增强由微装置101a及101b产生的光的输出耦合。接触垫101a及101b的形式不限于凹形形式且可取决于微装置光发射特性而具有其它形式。
参考图6G，在另一实施例中，结构经设计以从衬底100输出光。在这些底部发射结构中，衬底100可为透明的且共同电极303可包括反射材料用于更好光提取。
在图6H中展示的另一实施例中，反射层202可经延展以覆盖微装置601a及601b且还充当共同顶部电极。
在其它实施例中，前述像素界定结构可覆盖一个以上像素(或子像素)601a及601b。
在另一情况中，可使用受体衬底100上的反射层或接触垫101a及101b以覆盖受体衬底100且在转移微装置601a及601b之前产生反射区域以用于更好光输出耦合。
在所有前述实施例中，反射层还可为不透明的。另外，反射层可用作微装置601a及601b的电极中的一者或用作系统衬底连接中的一者(电极、信号或电力线)。在另一实施例中，反射层可用作触摸电极。可图案化反射层以充当触摸屏电极。在一个情况中，其可在垂直及水平方向上图案化以形成触摸屏交叉电极。在此情况中，我们可使用垂直及水平迹线之间的电介质。
混合结构
在另一实施例中，在微装置801的阵列已经转移到受体衬底100之后，将薄膜光电装置904集成于受体衬底100中。
图7说明受体衬底100及下电极接触件或接合垫702a及702b(微装置801阵列经转移到其上且在数个混合结构实施例中，薄膜光电装置904集成于其中)。
参考图8，可将微装置801中的一者转移且接合到受体衬底100的接合垫702a。在一个情况中，如在图9中展示，可在受体衬底100上方形成电介质层901以覆盖暴露的电极702a及702b及任何其它导电层。可使用光刻及蚀刻来图案化电介质层901。接着沉积且图案化导电层902以形成薄膜光电装置904的底部电极。如果底部电极902与受体衬底100中的其它导电层之间不存在非所要耦合的风险，那么可消除电介质层901。然而，电介质层901还可充当平坦层以提供光电装置904的更好制造。
仍参考图9，可在受体衬底100上例如在电介质层901及微装置801上方沉积堤岸层903以覆盖底部电极902及微装置801的边缘。可接着在堤岸层903及底部电极902结构上方形成薄膜光电装置904。有机LED(OLED)装置是此薄膜光电装置904的实例，其可使用不同技术形成，例如但不限于阴影掩模、光刻及印刷图案化。最后，根据需要沉积且图案化光电薄膜装置904的顶部电极905。
在其中微装置801的厚度极高的实施例中，底部电极902内可出现裂缝或其它结构问题。在这些实施例中，平坦化层903可结合电介质层901或在无电介质层901的情况下使用来解决此问题。
在图10中展示的另一实施例中，微装置801可具有上装置电极1001。上装置电极1001在系统衬底100中或上的其它微装置801之间可为共同的。在此情况中，平坦化层901(如果存在)及/或堤岸结构903覆盖上装置电极1001以将上电极1001与光电薄膜装置904及顶部及底部电极902、905绝缘，以避免光电装置904与装置电极1001之间的任何短路。
参考图11，在一个实施例中，薄膜光电装置904的顶部电极905可通过堤岸(平坦化)层903及光电薄膜装置904中的开口1005连接到微装置801。在此情况中，光电薄膜装置904可选择性地形成使得其并不覆盖开口1005。
在另一情况中，微装置801的下电极702a可在薄膜光电装置904与经转移微装置801之间共享。
参考图12，在另一实例中，薄膜光电装置904的底部电极902可在微装置801上方延伸，使得薄膜光电装置904可叠置在微装置801上方或周围。如果微装置801需要具有通过其顶部电极1001到外部的透明路径，那么底部电极902(如果不透明)需要在微装置801上方具有开口(例如，如图13A中结合另一实施例展示)。在此情况中，可还由堤岸层903覆盖开口。开口不限于图12中说明的特定结构且可使用不同方法产生。
仍参考图12，如果下电极702a是透明的，那么微装置801可具有通过衬底100的透明路径。在其中需要通过上电极1001的透明路径的情况中，底部电极902及微装置上电极1001需要是透明的或需要上电极1001及底部电极902中的一者或两者中的开口与上电极1001及底部电极902中的一者或两者中的透明度的组合。
图13A展示布局结构，其中底部电极902具有开口1301以允许通到顶部电极905的透明路径。开口1301还可延伸通过共同顶部电极905的堤岸层903。如果不存在共同顶部电极905且如果堤岸层903是透明的，那么不需要堤岸层903中的开口1301。在一些实施例中，如果顶部电极905还是不透明的，那么还需要顶部电极905中的开口1301以用于顶部发射。
参考图13B，在另一实施例中，为提供微装置801的透明路径，底部电极902不覆盖微装置801。针对共同顶部电极905，堤岸层903中可存在开口1301。如果不存在共同顶部电极905且堤岸层903是透明的，那么不需要堤岸层903中的开口1301。
在另一情况中，薄膜光电装置904的接触垫结构702b可延伸以充当反射层。如在图14A中可见，具有接触件702b的两个并排像素可用来侧向限制由像素中的微装置801产生的光。在图14B中展示的另一实施例中，安装于衬底100的顶部表面上的反射层1401可朝向顶部电极905反射更多光。因此，增强由微装置801产生的光的输出耦合。在此情况中，最佳实践是使薄膜光电装置904的顶部及底部电极902及905透明，或在电极902及905是不透明的情况下制成开口。
在另一实施例中，薄膜光电装置904及微装置801可在系统衬底100的两个相对侧上。在此情况中，系统衬底电路可在系统衬底100的一侧上且通过接触孔连接到另一侧，或电路可在系统衬底100的两侧上。
在另一情况中，微装置801可在一个系统衬底100上且薄膜光电装置904在另一系统衬底上。这两个衬底可接着经接合在一起。在此情况中，电路可在系统衬底中的一者上或两个衬底上。
图14C及14D展示其中微装置(LED)801及薄膜光电装置904经集成以产生半导体装置的不同结构。此处，使用理想地安装于衬底100上沿着衬底100在微装置801及薄膜光电装置904两者下方延伸的反射或光限制结构5601以引导微装置801的光输出。反射结构5601可与微装置电极702a相同或可使用单独电极702a。如在图14D中展示，从接触垫702b延伸到平行于光电装置904的主要平坦区段902b的底部电极902的第一部分902a可包括能够用作光限制或反射结构的反射材料，其用于将光引导在所要方向上(例如，通过衬底100或顶部电极905)且防止光进入相邻像素。可首先沉积底部电极902的第一部分902a，接着可在主要平坦区段902b之后沉积底部电极的剩余部分902b或第一部分902a。此外，其它电极可经沉积以连接微装置801。理想地，薄膜光电装置904的底部及顶部电极902及905两者是透明的，使得来自微装置801及光电装置904的光经发射通过顶部电极905。未向外发射的任何离散光可通过反射结构5601及902a向外重导引通过顶部电极905。可在堤岸结构903之间形成光电装置904，堤岸结构903可替代地为黑色矩阵。在光电装置904之后，可集成(例如囊封)其它结构。
图14E、14F及14G描述其中光电装置904及微装置801并排在衬底100上的另一结构。此处，将微装置801转移到系统衬底100。沉积且图案化平坦化层903(或堤岸层)以敞开光电装置904的区域。使用不同可能方法(例如气相沉积、印刷等)沉积光电装置904。接着，在光电装置904及微装置801的顶部上方沉积顶部电极905。此处，可在顶部电极905之后沉积其它结构。光可通过顶部电极905或系统衬底100。在图14E中描述的一个结构中，微装置801及光电装置904具有相同顶部电极905。在图14F中描述的另一结构中，微装置801具有由钝化(电介质)层903覆盖的单独上电极5620。此处，在薄膜光电装置904及微装置801两者上方延伸的顶部电极905可用作光限制/反射结构以导引来自微装置801及薄膜光电装置904的光通过系统衬底100。在图14G中展示的另一实例中，共享顶部电极905；然而，钝化/平坦化层903在5622处图案化为一或多个凹形结构以产生用于将光引导在所要方向上(例如，返回通过衬底100)的一或多个光限制/反射结构。此处，可使用单独层来在沉积顶部电极905之前产生光限制结构。
在此处描述的所有结构中，微装置801的接触电极702a可在微装置801转移到系统衬底100之后沉积，或接触件702a可在转移工艺之前预先存在。在微装置801之前可存在平坦化层901或903，且可在系统衬底100上安装其它装置以改进表面轮廓。在此情况中，可存在将微装置801连接到系统衬底100中的其它元件的开口。
可组合前文描述的结构。例如，可混合光限制或提取结构及混合装置。
在此处图9到14中描述的混合装置中，薄膜发光装置结构904可包含彩色滤光器。在使用彩色滤光器的情况中，来自微装置801的光需要经过薄膜发光装置结构904且通过彩色滤光器。
图14H及14I展示将微装置801与彩色滤光器5810及光电装置904集成的两个实例。在此情况中，光通过系统衬底100。在沉积彩色滤光器5810、定位接合垫702a及702b且转移微装置801及上电极1001(可改变这些步骤的顺序)之后，可根据需要沉积平坦化(例如，电介质)层901。可在各先前步骤之后沉积两个或三个不同平坦化层。接着，分别沉积且形成光电装置904及底部及顶部电极902及905。此处，微装置801可在转移之前包含光限制结构(此还可用于此文献中的其它结构)。此外，如在图14I中展示，光限制结构可在转移微装置801之后形成。在所说明的实施例中，光限制具有钝化层5814(借此与微装置801及上电极1001绝缘)及形成为用于将光反射在所要方向上(例如，通过衬底100)的凹形结构的反射层5812。
图14J展示将微装置801与光电装置904及安装于光电装置904及顶部电极905上方的彩色滤光器5810集成的另一实例。所有上述结构(例如光限制结构)在此实例中可配合微装置801及光电装置904使用。此处，光通过透明顶部电极905。此结构中，顶部电极905与彩色滤光器5810之间可存在(或若干)透明保护层5910。
集成
此文献还揭示用于将单体微装置阵列集成于系统衬底中或将微装置阵列选择性转移到系统衬底的各种方法。此处，所提出的工艺分为两个类别。在第一类别中，系统衬底上的接合垫的节距与微装置的接合垫的节距相同。在第二类别中，系统衬底上的接合垫具有大于微装置的接合垫的节距。针对第一类别，呈现三个不同集成或转移方案
1.前侧接合
2.后侧接合
3.贯穿衬底通孔接合。
在此实施例中，微装置在功能性方面可具有相同类型或不同类型。在一个实施例中，微装置是具有相同色彩或具有数个不同色彩(例如，红色、绿色及蓝色)的微LED，且系统衬底是背板，从而控制个别微LED。这些多色LED阵列直接制造在衬底上或从生长衬底转移到临时衬底。在图15中展示的一个实例中，在牺牲/缓冲层1502及衬底1501上生长RGB微LED装置1503、1504及1505。在一个情况中，具有接触垫1507的系统衬底1506可对准(图16)且接合到微装置衬底1501，如在图17中展示。在移除微装置衬底1501(图18)及牺牲/缓冲层1502(图19)之后，可在集成样本上(图20)旋涂/沉积填料电介质涂层2001(例如，聚酰亚胺光致抗蚀剂)。此步骤之后可进行蚀刻工艺以揭露微LED装置的顶部。在微LED装置的情况中，可在样本上沉积共同透明电极2002。在另一实施例中，可沉积且图案化顶部电极以隔离微装置以用于后续工艺。
在另一实施例中，如在图21中展示，在缓冲/牺牲层1502上生长微装置1503、1504及1505。在衬底上沉积/旋涂电介质填料层2101以完全覆盖微装置。在图21中说明的一个实例中，此步骤之后可进行蚀刻工艺以揭露微装置1503、1504及1505的顶部以形成顶部共同接触件及晶种层以用于后续工艺(例如，电镀)。参考图22，接着在样本的顶部上沉积、生长或接合厚机械支撑层2102。此处，填料层2101可为黑色矩阵层或反射材料。此外，在沉积机械支撑件之前，我们可沉积电极(作为经图案化或共同层)。接着沉积机械支撑层。在光电装置(例如LED)的情况中，机械支撑层需要是透明的。如在图23及图24中展示，接着使用各种工艺(例如激光剥离或蚀刻)来移除微装置衬底1501。在一个情况中，衬底的厚度最初通过例如(但不限于)深反应性离子蚀刻(DRIE)的工艺减小到几微米。接着，通过例如(但不限于)湿式化学蚀刻工艺的工艺移除剩余衬底。在此情况中，缓冲/牺牲层1502可充当蚀刻停止层以确保均匀蚀刻子表面且避免对微装置的任何损害。在移除缓冲层1502之后，如在图24中展示，执行另一蚀刻(例如，RIE)以暴露微装置。我们可沉积且图案化金属层以在微装置的上接触件及接合垫在微装置制造期间尚未形成的情况下充当所述上接触件及接合垫。接着可将具有接触垫1507的系统衬底1506对准且接合微装置阵列，如在图25中展示。取决于微装置的类型及功能性，可接着移除机械支撑层2102及填料层2101，如在图26A及图26B中展示。
在另一实施例中，实施贯穿衬底通孔以制成到微装置的背面的接触件。
参考图27，在一个实施例中，微装置1503、1504及1505可为生长在绝缘缓冲层1502上的多色微LED。此缓冲层1502还可用作蚀刻停止层。在微装置1503、1504及1505上方及周围沉积电介质层2701作为填料层。
参考图28A及图28B，使用例如(但不限于)光刻的工艺在衬底1501的背侧上形成图案。在一个实施例中，使用例如DRIE的方法以在衬底1501中制成衬底穿孔(throughsubstrate hole)。可使用(例如)湿式蚀刻工艺来移除可充当蚀刻停止层的缓冲层1502。
参考图29，可在衬底1501的背面上沉积绝缘膜2901。可从微装置1503、1504及1505的背侧部分移除绝缘层2901以允许形成到这些微装置的电接触件。
参考图30，使用例如(但不限于)电镀的工艺用导电材料3001填充贯穿孔。此处，通孔可充当微装置接触件及接合垫。
如在图31中说明，通过以下步骤形成微装置1503、1504及1505的共同前接触件3101：执行蚀刻工艺(例如，使用RIE)以揭露微装置1503、1504及1505的顶部；接着沉积透明导电层以形成前接触件3101。
参考图32，接着，将微装置衬底1501对准且接合到具有接触垫1507的系统衬底1506，系统衬底1506在此实例中可为控制个别装置的背板。
在另一实施例中，已以任意节距长度在衬底上制造微装置以最大化生产良率。例如，微装置可为多色微LED(例如，RGB)。此实例的系统衬底可为具有拥有不同于微LED的节距长度的节距长度的接触垫的显示器背板。
参考图33A，在一个实施例中，施体衬底1501具有微装置类型3301、3302及3303且其以一维阵列3304的形式图案化，其中针对来自一个类型的每一微装置3301、3302及3303，至少存在其节距3305与受体(或系统)衬底1506上的对应区域(或垫)的节距匹配的来自另一类型的微装置。
作为实例，在图33B中展示的一个实施例中，接触垫1507的节距3404比如在图33B中展示的微装置3401的节距3402大倍。
参考图34，使系统衬底1506及微装置衬底1501接合在一起，对准且接触。
如在图35及图36中展示，可使用例如激光剥离(LLO)的方法以将微装置3401选择性地转移到系统衬底1506上的接触垫3403。如在图37中展示，转移之后可接着在系统衬底的顶部上沉积填料层3701及保形导电层3702作为共同电极。
在图38A及38B中展示的另一实施例中，缓冲层3801作为用于制造微装置1503、1504及1505的材料模板是必需的。
仍参考图38A及图38B，缓冲层3801经沉积于牺牲层1502上且经图案化以隔离微装置1503、1504及1505。在一些情况中，还可图案化牺牲层1502。
在一个实施例中，代替隔离个别微装置，可使微装置群组彼此隔离(如在图38A及图38B中展示)以促进转移工艺。
参考图39，可在衬底1501上旋涂填充材料3901(例如但不限于聚酰亚胺)以填充个别微装置1503、1504及1505之间之间隙。此填充步骤确保转移工艺期间的机械强度。此在使用如激光剥离的工艺以将微装置脱离载体衬底时是尤其重要的。
参考图40，微装置可不具有相同高度，这使得难以将其接合到系统衬底1506。在这些情况中，我们可实施静电夹持机构4001或系统衬底1506中的其它夹持机构以将微装置暂时保持在系统衬底1506上以用于最终接合步骤。夹持机构4001可对微装置是局部的或对微装置群组是全局夹持，如在针对整个晶片的相同节距转移的情况中。夹持机构4001可在接触电极1507上方的层上。在此情况中，可使用平坦化层。
在一个实施例中，参考图41A，施体衬底上的不同微装置类型3301、3302及3303的图案产生每一类型的二维阵列(例如，阵列4100)，其中经定义为相邻阵列之间的中心到中心距离的阵列之间的节距4101与系统衬底上的对应区域的节距匹配。
在图41B及图42中展示的一个实施例中，当子装置节距4103大于其衬底上的经制造个别微装置1503的正常距离(例如，在大显示器中)时，微装置衬底1501以二维单色阵列的形式布局。此处，接触垫1507的节距4102及微装置阵列1503的节距4103是相同的。使用此技术，我们可放松微装置制造要求且相较于上文所描述的技术减少选择性转移工艺。
图43及图44展示替代性图案，其中微装置1503未形成为二维群组，且其中不同微装置1503跨衬底1501均匀放置，如在图43中针对三个不同微装置1503展示那样。
参考图45，在另一实施例中，首先将微装置4503转移到导电半透明共同衬底4501，接着将其接合到系统衬底4502。
色彩转换结构
在其中微装置是光学装置(例如LED)的一些实施例中，我们可使用色彩转换或彩色滤光器来定义不同功能性(在像素的情况中为不同色彩)。在此实施例中，系统衬底上的两个或两个以上接触垫装有相同类型的光学装置。一旦处在适当位置中，系统衬底上的装置便通过不同色彩转换层区分。
参考图46A及图46B，在一个实施例中，在将微装置1503转移到系统衬底1506之后，由平坦化层4601覆盖整个结构。接着在平坦化层4601上形成共同电极4602。平坦化层的高度可与经堆叠装置相同、高于或低于经堆叠装置。如果平坦化层4601较低(或不存在平坦化层)，那么装置的壁可通过钝化材料保形覆盖。
参考图47，产生堤岸结构4701(尤其在使用印刷工艺来沉积色彩转换层的情况下)。堤岸4701可分离每一像素或仅分离不同色彩转换材料4702。
图48展示集成结构，其中色彩转换材料4702完全覆盖经转移微装置的顶部且部分覆盖其侧。堤岸4701分离色彩转换层4702且电极4602是所有经转移微装置的共同接触件。
图49展示集成结构，其中色彩转换层4702完全覆盖经转移微装置的顶部且部分覆盖其侧。堤岸4701分离色彩转换层4702且到微装置的接触件经制成仅通过系统衬底1506。
图50展示集成结构，其中色彩转换层4702直接形成在共同电极4602上。在此情况中，不使用堤岸层。
图51展示集成结构，其中色彩转换层4702完全覆盖经转移微装置的顶部且部分覆盖其侧。电极4602是所有经转移微装置的共同接触件。在此情况中，不使用堤岸层。
图52展示集成结构，其中色彩转换层4702完全覆盖经转移微装置的顶部且部分覆盖其侧。到微装置的接触件经制成仅通过系统衬底1506。在此情况中，不使用堤岸层。
在图53A及图53B中展示的一个实施例中，在集成系统衬底1506上形成色彩转换材料4702之后，在结构上沉积平坦化层5301。在其中需要保护集成衬底的色彩转换材料及/或其它组件以免受环境条件影响的一些情况中，在整个结构上方形成囊封层5302。应注意，囊封层5302可由不同层堆叠形成以有效保护集成结构以免受环境条件影响。
参考图54A及图54B，在另一实施例中，可将使用囊封层5302涂布的单独衬底5401接合到集成系统衬底。
可组合图53及图54中描绘的实施例，其中在结构1506及单独结构5401两者上形成囊封层5302以用于更有效囊封。
共同电极是以毯覆层的形式沉积于衬底上的透明导电层。在一个实施例中，此层可充当平坦化层。在一些实施例中，此层的厚度经选择以满足光学及电子要求两者。
光学装置之间的距离可经选择为足够大以便降低光学装置之间的串扰，或在光学装置之间沉积阻挡层以实现此效果。在一个情况中，平坦化层还充当阻挡层。
在沉积色彩转换层之后，可沉积不同层(例如偏光器)。
在另一方面中，在色彩转换层上沉积彩色滤光器。在此情况中，可实现更宽的色域及更高的效率。我们可在沉积彩色滤光器层之前在色彩转换层之后使用平坦化层及/或堤岸层。
彩色滤光器可大于色彩转换层以阻挡任何光泄露。此外，可在色彩转换岛状物或彩色滤光器之间形成黑色矩阵。
图55A、55B及55C说明其中在数个像素(或子像素)之间共享装置的结构。此处，微装置1503并不完全图案化，但水平条件经设计使得接触件1507界定经分配到每一像素的区域。图55A展示具有接触垫1507的系统衬底1506及具有微装置1503的施体衬底1501。在微装置1503经转移到系统衬底(在图55B中展示)之后，我们可进行后处理(图55C)，例如沉积共同电极4602、色彩转换层4702、彩色滤光器等。图55C展示在微装置1503的顶部上沉积色彩转换层4702的一个实例。此处，色彩转换层之后可进行彩色滤光器沉积。本发明中描述的方法及/或其它可能方法可用于不同部分或将不同层集成于显示器中。此外，我们可在电极4602之前或之后使用平坦化层4601。此外，可在LED 1503之间使用反射层1509。可在垫1507之间使用填料且填料可为黑色矩阵。可在LED 1503之间使用某一间隔件或光限制结构。在系统衬底1506上，可使用反射层来引导光。
图55D展示在微装置1503的顶部上沉积色彩转换层4702的另一实例。然而，还可使用本发明中描述的其它方法及其它可能方法。此外，我们可在透明上电极4602之前或之后使用平坦化层4601。此外，可在LED 1503之间使用反射层。可在垫1507之间使用填料且填料5502可为黑色矩阵。可在微LED 1503之间使用某一间隔件或光限制结构5504。在系统衬底1506上，可使用反射层1509来引导光。此处，微LED 1503的光扩散到较大区域上方，使得色彩转换层4702上存在较少应力。还可使用不同结构来将光扩散到较大区域上。
在形成作用区域之后，可将如描述的色彩转换层添加到像素(或子像素)作用区域中。此可提供更高填充因子及更高的性能且还在像素(或子像素)的作用区域由反射层覆盖的情况下避免色彩从侧像素(或子像素)泄露。
已处于说明及描述的目的呈现本发明的一或多个实施例的先前描述。其并非希望详尽性或使本发明限于所揭示的精确形式。鉴于上述教示，许多修改及变化是可能的。本发明的范围不希望受限于此详细描述，而是受限于所附权利要求书。

Claims (10)

1.一种集成光学系统，其包括：
系统衬底；
第一及第二多个电极接触垫，其在所述系统衬底上；
第一发光微装置，其安装于所述第一多个电极接触垫上；
第二发光微装置，其安装于所述第二多个电极接触垫上；
平坦化层，其包围所述第一发光微装置及所述第二发光微装置且介于所述第一发光微装置及所述第二发光微装置之间；
第一色彩转换层，其在所述第一发光微装置上，及第二色彩转换层，其在所述第二发光微装置上；
堤岸结构，其沉积在所述第一色彩转换层和所述第二色彩转换层之间，以分离第一发光微装置和所述第二发光微装置；及
底部反射器，其在所述系统衬底上，用于引导来自所述第一发光微装置及所述第二发光微装置的光通过所述第一色彩转换层和所述第二色彩转换层。
2.根据权利要求1所述的集成光学系统，其中所述第一发光微装置或所述第二发光微装置通过跨所述第一发光微装置和所述第二发光微装置两者的顶部上方的顶部共同电极提供连接，其中所述顶部共同电极是沉积在所述系统衬底上的透明导电层。
3.根据权利要求1所述的集成光学系统，其中所述平坦化层在所述第一多个电极接触垫和所述第二多个电极接触垫之前或之后使用。
4.根据权利要求1所述的集成光学系统，其进一步包括安装在所述第一色彩转换层和所述第二色彩转换层上的彩色滤光器。
5.根据权利要求4所述的集成光学系统，其进一步包括安装在所述第一多个电极接触垫和所述第二多个电极接触垫之间的作为填充物的黑色矩阵。
6.根据权利要求1所述的集成光学系统，其中所述第一发光微装置和所述第二发光微装置之间设置有间隔件。
7.根据权利要求6所述的集成光学系统，其中所述间隔件是光限制结构。
8.根据权利要求1所述的集成光学系统，其进一步包括沉积在所述第一发光微装置和所述第二发光微装置之间的反射层，以引导所述光。
9.根据权利要求1所述的集成光学系统，其中所述第一发光微装置和所述第二发光微装置并不完全图案化而是水平条件经设计使得所述第一多个电极接触垫和所述第二多个电极接触垫界定经分配到每一像素的区域。
10.根据权利要求1所述的集成光学系统，其中通过所述系统衬底与所述第一发光微装置和所述第二发光微装置连接。
CN201880047604.8A 2015-01-23 2018-07-18 集成光学系统 Active CN110892530B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202311598175.2A CN117613166A (zh) 2015-01-23 2018-07-18 集成光学系统

Applications Claiming Priority (9)

Application Number Priority Date Filing Date Title
CA2879465A CA2879465A1 (en) 2015-01-23 2015-01-23 Integration of semiconductor devices into system substrate
CA2879627A CA2879627A1 (en) 2015-01-23 2015-01-23 Selective semiconductor device integration into system substrate
CA2880718A CA2880718A1 (en) 2015-01-28 2015-01-28 Selective transfer of semiconductor device to a system substrate
CA2883914A CA2883914A1 (en) 2015-03-04 2015-03-04 Selective transferring of micro-devices
CA2890398A CA2890398A1 (en) 2015-05-04 2015-05-04 Selective and non-selective micro-device transferring
CA2936473A CA2936473A1 (en) 2016-07-19 2016-07-19 Integrated micro-devices and method of assembly
US15/653,120 2017-07-18
US15/653,120 US10700120B2 (en) 2015-01-23 2017-07-18 Micro device integration into system substrate
PCT/IB2018/055347 WO2019016730A1 (en) 2015-01-23 2018-07-18 MICRO-DEVICE INTEGRATION IN A SYSTEM SUBSTRATE

Related Child Applications (1)

Application Number Title Priority Date Filing Date
CN202311598175.2A Division CN117613166A (zh) 2015-01-23 2018-07-18 集成光学系统

Publications (2)

Publication Number Publication Date
CN110892530A CN110892530A (zh) 2020-03-17
CN110892530B true CN110892530B (zh) 2023-12-19

Family

ID=60418928

Family Applications (2)

Application Number Title Priority Date Filing Date
CN201880047604.8A Active CN110892530B (zh) 2015-01-23 2018-07-18 集成光学系统
CN202311598175.2A Pending CN117613166A (zh) 2015-01-23 2018-07-18 集成光学系统

Family Applications After (1)

Application Number Title Priority Date Filing Date
CN202311598175.2A Pending CN117613166A (zh) 2015-01-23 2018-07-18 集成光学系统

Country Status (5)

Country Link
US (2) US10700120B2 (zh)
KR (2) KR102618938B1 (zh)
CN (2) CN110892530B (zh)
DE (1) DE112018003713T5 (zh)
WO (1) WO2019016730A1 (zh)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107851586B (zh) * 2015-01-23 2021-07-06 维耶尔公司 到受体衬底的选择性微型器件转移
US10224358B2 (en) 2017-05-09 2019-03-05 Lumileds Llc Light emitting device with reflective sidewall
TWI611573B (zh) * 2017-06-09 2018-01-11 晶典有限公司 微發光二極體顯示模組的製造方法
TWI633681B (zh) * 2017-06-09 2018-08-21 美商晶典有限公司 微發光二極體顯示模組的製造方法
CN107818931B (zh) * 2017-09-30 2021-10-19 厦门市三安光电科技有限公司 半导体微元件的转移方法及转移装置
KR102590433B1 (ko) * 2018-09-07 2023-10-18 삼성전자주식회사 디스플레이 모듈, 이를 포함하는 디스플레이 장치 및 디스플레이 모듈 제조 방법
FR3087580B1 (fr) * 2018-10-23 2020-12-18 Aledia Procede de realisation d’un dispositif optoelectronique comprenant des diodes electroluminescentes homogenes en dimensions
CN109979981B (zh) * 2019-03-29 2021-05-14 上海天马微电子有限公司 一种显示面板及其制作方法、显示装置
US11777059B2 (en) 2019-11-20 2023-10-03 Lumileds Llc Pixelated light-emitting diode for self-aligned photoresist patterning
WO2021097736A1 (zh) * 2019-11-21 2021-05-27 重庆康佳光电技术研究院有限公司 一种微器件及其制备方法
CN111834513B (zh) * 2020-06-30 2021-12-28 湖北长江新型显示产业创新中心有限公司 基板、显示面板及其组装检测方法
US20240124297A1 (en) * 2021-02-22 2024-04-18 Vuereal Inc. Cartridge interference
WO2022221950A1 (en) * 2021-04-21 2022-10-27 Vuereal Inc. Integrating color conversion material in a microdevice
WO2022232929A1 (en) * 2021-05-04 2022-11-10 Vuereal Inc. Integrated color conversion cartridge
WO2024073861A1 (en) * 2022-10-07 2024-04-11 Vuereal Inc. Chiplet cartridge

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105324858A (zh) * 2013-06-17 2016-02-10 勒克斯维科技公司 用于集成光发射设备的反射堤结构和方法
WO2016043497A2 (ko) * 2014-09-16 2016-03-24 엘지디스플레이 주식회사 광 제어 장치, 광 제어 장치의 제조 방법 및 광 제어 장치를 포함하는 표시 장치
CA2879465A1 (en) * 2015-01-23 2016-07-23 Ignis Innovation Inc. Integration of semiconductor devices into system substrate
CA2880718A1 (en) * 2015-01-28 2016-07-28 Ignis Innovation Inc. Selective transfer of semiconductor device to a system substrate
CA2883914A1 (en) * 2015-03-04 2016-09-04 Ignis Innovation Inc. Selective transferring of micro-devices

Family Cites Families (72)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5184398A (en) 1991-08-30 1993-02-09 Texas Instruments Incorporated In-situ real-time sheet resistance measurement method
US5782399A (en) 1995-12-22 1998-07-21 Tti Testron, Inc. Method and apparatus for attaching spherical and/or non-spherical contacts to a substrate
US20020048137A1 (en) 1998-04-01 2002-04-25 Williams Thomas J. Two-layered embedded capacitor
US6159822A (en) 1999-06-02 2000-12-12 Vanguard International Semiconductor Corporation Self-planarized shallow trench isolation
JP2004537158A (ja) 2001-02-08 2004-12-09 インターナショナル・ビジネス・マシーンズ・コーポレーション チップ転写方法および該装置
WO2002084631A1 (fr) 2001-04-11 2002-10-24 Sony Corporation Procede de transfert d'element, procede de disposition d'element mettant en oeuvre ce procede et procede de production d'un appareil d'affichage d'image
JP2003109773A (ja) 2001-07-27 2003-04-11 Semiconductor Energy Lab Co Ltd 発光装置、半導体装置およびそれらの作製方法
FR2838561B1 (fr) 2002-04-12 2004-09-17 Commissariat Energie Atomique Matrice de photodectecteurs, a pixels isoles par des murs, hybridee sur un circuit de lecture
SG120879A1 (en) 2002-08-08 2006-04-26 Micron Technology Inc Packaged microelectronic components
US6987355B2 (en) 2003-06-11 2006-01-17 Eastman Kodak Company Stacked OLED display having improved efficiency
CN1813362A (zh) 2003-06-26 2006-08-02 纳幕尔杜邦公司 在基底上形成填充介电材料的图案的方法
US7053412B2 (en) 2003-06-27 2006-05-30 The Trustees Of Princeton University And Universal Display Corporation Grey scale bistable display
US20050104225A1 (en) 2003-11-19 2005-05-19 Yuan-Chang Huang Conductive bumps with insulating sidewalls and method for fabricating
US7088431B2 (en) 2003-12-17 2006-08-08 Asml Netherlands B.V. Lithographic apparatus and device manufacturing method
KR100906475B1 (ko) * 2004-01-13 2009-07-08 삼성전자주식회사 마이크로 광학벤치 구조물 및 그 제조방법
JP4349952B2 (ja) 2004-03-24 2009-10-21 京セラ株式会社 ウェハ支持部材とその製造方法
US7018859B2 (en) * 2004-06-28 2006-03-28 Epistar Corporation Method of fabricating AlGaInP light-emitting diode and structure thereof
KR100635575B1 (ko) 2004-11-17 2006-10-17 삼성에스디아이 주식회사 풀 칼라 유기 전계 발광 표시 소자 및 그 제조방법
US7307327B2 (en) 2005-08-04 2007-12-11 Micron Technology, Inc. Reduced crosstalk CMOS image sensors
KR100685844B1 (ko) 2005-08-26 2007-02-22 삼성에스디아이 주식회사 양면발광 유기 전계발광 표시장치 및 그의 구동방법
JP5091150B2 (ja) 2005-11-11 2012-12-05 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 複数の半導体デバイス及びキャリア基板の製造方法
CN100576492C (zh) 2006-09-30 2009-12-30 中芯国际集成电路制造(上海)有限公司 形成器件隔离区的方法
US7629184B2 (en) 2007-03-20 2009-12-08 Tokyo Electron Limited RFID temperature sensing wafer, system and method
JP6097471B2 (ja) 2007-04-27 2017-03-15 アプライド マテリアルズ インコーポレイテッドＡｐｐｌｉｅｄ Ｍａｔｅｒｉａｌｓ，Ｉｎｃｏｒｐｏｒａｔｅｄ 環状のバッフル
TWI471971B (zh) 2007-10-30 2015-02-01 尼康股份有限公司 Substrate holding member, substrate bonding apparatus, laminated substrate manufacturing apparatus, substrate bonding method, laminated substrate manufacturing method, and laminated semiconductor device manufacturing method
WO2010004944A1 (en) 2008-07-10 2010-01-14 Semiconductor Energy Laboratory Co., Ltd. Light-emitting device and electronic device using the same
US8139340B2 (en) 2009-01-20 2012-03-20 Plasma-Therm Llc Conductive seal ring electrostatic chuck
US9991147B2 (en) 2009-09-01 2018-06-05 Hermes Microvision, Inc. Wafer grounding and biasing method, apparatus, and application
CN102097357A (zh) 2009-12-15 2011-06-15 中芯国际集成电路制造(上海)有限公司 隔离结构的制作方法
US8436255B2 (en) 2009-12-31 2013-05-07 Stmicroelectronics Pte Ltd. Fan-out wafer level package with polymeric layer for high reliability
JP5458307B2 (ja) 2010-03-05 2014-04-02 株式会社ジャパンディスプレイ 電気光学表示装置
US9496155B2 (en) 2010-03-29 2016-11-15 Semprius, Inc. Methods of selectively transferring active components
DE112011101135B4 (de) 2010-03-29 2021-02-11 X-Celeprint Limited Elektrisch verbundene Felder von aktiven Bauteilen in Überführungsdrucktechnik
EP2736089B1 (en) 2011-07-19 2018-09-12 Hitachi, Ltd. Organic light-emitting element, light source device and organic light-emitting element manufacturing method
US8573469B2 (en) 2011-11-18 2013-11-05 LuxVue Technology Corporation Method of forming a micro LED structure and array of micro LED structures with an electrically insulating layer
US8518204B2 (en) 2011-11-18 2013-08-27 LuxVue Technology Corporation Method of fabricating and transferring a micro device and an array of micro devices utilizing an intermediate electrically conductive bonding layer
US9965106B2 (en) 2011-11-22 2018-05-08 Atmel Corporation Touch screen with electrodes positioned between pixels
TWI631697B (zh) 2012-02-17 2018-08-01 財團法人工業技術研究院 發光元件及其製造方法
TWI546979B (zh) 2012-03-05 2016-08-21 晶元光電股份有限公司 對位接合之發光二極體裝置與其製造方法
US9134368B2 (en) 2012-05-07 2015-09-15 Taiwan Semiconductor Manufacturing Co., Ltd. Contactless wafer probing with improved power supply
CN103390647A (zh) 2012-05-10 2013-11-13 无锡华润上华半导体有限公司 一种功率mos器件结构
CN102683534B (zh) 2012-05-21 2015-02-25 厦门市三安光电科技有限公司 垂直式交流发光二极管器件及其制作方法
US8933433B2 (en) 2012-07-30 2015-01-13 LuxVue Technology Corporation Method and structure for receiving a micro device
DE102012215513A1 (de) 2012-08-31 2014-03-06 J. Schmalz Gmbh Greifvorrichtung
US8765582B2 (en) 2012-09-04 2014-07-01 Taiwan Semiconductor Manufacturing Company, Ltd. Method for extreme ultraviolet electrostatic chuck with reduced clamp effect
US9159700B2 (en) * 2012-12-10 2015-10-13 LuxVue Technology Corporation Active matrix emissive micro LED display
CN103904073A (zh) 2012-12-29 2014-07-02 欧普照明股份有限公司 Led和oled集成照明模块
EP2939265B1 (en) 2012-12-31 2018-10-31 Flir Systems, Inc. Wafer level packaging of microbolometer vacuum package assemblies
US9443833B2 (en) * 2013-01-31 2016-09-13 Nthdegree Technologies Worldwide Inc. Transparent overlapping LED die layers
KR101729603B1 (ko) 2013-02-25 2017-04-24 쿄세라 코포레이션 시료 유지구
WO2014165151A1 (en) 2013-03-13 2014-10-09 Cabot Corporation Coatings having filler-polymer compositions with combined low dielectric constant, high resistivity, and optical density properties and controlled electrical resistivity, devices made therewith, and methods for making same
WO2014149182A1 (en) 2013-03-15 2014-09-25 Applied Materials, Inc. Methods and apparatus for electrostatic chuck repair and refurbishment
US9728124B2 (en) 2013-05-08 2017-08-08 Apple Inc. Adaptive RGB-to-RGBW conversion for RGBW display systems
CN104241535B (zh) 2013-06-06 2017-07-25 上海和辉光电有限公司 一种有机发光结构
US9111464B2 (en) 2013-06-18 2015-08-18 LuxVue Technology Corporation LED display with wavelength conversion layer
US8928021B1 (en) * 2013-06-18 2015-01-06 LuxVue Technology Corporation LED light pipe
JP2015050011A (ja) 2013-08-30 2015-03-16 株式会社ジャパンディスプレイ エレクトロルミネセンス装置およびその製造方法
US9431283B2 (en) 2013-09-19 2016-08-30 Palo Alto Research Center Incorporated Direct electrostatic assembly with capacitively coupled electrodes
US10062738B2 (en) 2013-11-27 2018-08-28 The Regents Of The University Of Michigan Devices combining thin film inorganic LEDs with organic LEDs and fabrication thereof
US10153190B2 (en) 2014-02-05 2018-12-11 Micron Technology, Inc. Devices, systems and methods for electrostatic force enhanced semiconductor bonding
US11158526B2 (en) 2014-02-07 2021-10-26 Applied Materials, Inc. Temperature controlled substrate support assembly
US9871350B2 (en) 2014-02-10 2018-01-16 Soraa Laser Diode, Inc. Manufacturable RGB laser diode source
US9257414B2 (en) 2014-04-10 2016-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked semiconductor structure and method
US9196498B1 (en) 2014-08-12 2015-11-24 Applied Materials, Inc. Stationary actively-cooled shadow ring for heat dissipation in plasma chamber
KR20170047324A (ko) * 2014-08-26 2017-05-04 엑스-셀레프린트 리미티드 마이크로 어셈블링된 하이브리드 디스플레이들 및 조명 엘리먼트들
US10381335B2 (en) 2014-10-31 2019-08-13 ehux, Inc. Hybrid display using inorganic micro light emitting diodes (uLEDs) and organic LEDs (OLEDs)
US9607907B2 (en) 2014-12-01 2017-03-28 Industrial Technology Research Institute Electric-programmable magnetic module and picking-up and placement process for electronic devices
US9478583B2 (en) 2014-12-08 2016-10-25 Apple Inc. Wearable display having an array of LEDs on a conformable silicon substrate
CA2887186A1 (en) 2015-05-12 2016-11-12 Ignis Innovation Inc. Selective transferring and bonding of pre-fabricated micro-devices
CA2890398A1 (en) 2015-05-04 2016-11-04 Ignis Innovation Inc. Selective and non-selective micro-device transferring
US10134803B2 (en) * 2015-01-23 2018-11-20 Vuereal Inc. Micro device integration into system substrate
WO2017099905A1 (en) 2015-12-07 2017-06-15 Glo Ab Laser lift-off on isolated iii-nitride light islands for inter-substrate led transfer

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105324858A (zh) * 2013-06-17 2016-02-10 勒克斯维科技公司 用于集成光发射设备的反射堤结构和方法
WO2016043497A2 (ko) * 2014-09-16 2016-03-24 엘지디스플레이 주식회사 광 제어 장치, 광 제어 장치의 제조 방법 및 광 제어 장치를 포함하는 표시 장치
CA2879465A1 (en) * 2015-01-23 2016-07-23 Ignis Innovation Inc. Integration of semiconductor devices into system substrate
CA2880718A1 (en) * 2015-01-28 2016-07-28 Ignis Innovation Inc. Selective transfer of semiconductor device to a system substrate
CA2883914A1 (en) * 2015-03-04 2016-09-04 Ignis Innovation Inc. Selective transferring of micro-devices

Also Published As

Publication number Publication date
US20170345867A1 (en) 2017-11-30
US20200328249A1 (en) 2020-10-15
WO2019016730A1 (en) 2019-01-24
KR20240001289A (ko) 2024-01-03
US10700120B2 (en) 2020-06-30
KR102618938B1 (ko) 2023-12-27
CN110892530A (zh) 2020-03-17
KR20200035048A (ko) 2020-04-01
DE112018003713T5 (de) 2020-04-09
CN117613166A (zh) 2024-02-27
US11735623B2 (en) 2023-08-22

Similar Documents

Publication Publication Date Title
CN110892530B (zh) 集成光学系统
US20210202572A1 (en) Micro device integration into system substrate
US10847571B2 (en) Micro device integration into system substrate
JP6622923B2 (ja) マイクロドライバ及びマイクロｌｅｄのためのバックプレーン構造及びプロセス
WO2017149521A1 (en) Micro device integration into system substrate
US20230170338A1 (en) Circuit and system integration onto a microdevice substrate
US11322556B2 (en) Method of integrating functional tuning materials with micro devices and structures thereof
CN110462565B (zh) 内置触摸传感器的显示装置
US10658423B2 (en) Method of manufacturing light emitting device
US10381400B2 (en) Method of manufacturing light emitting device
WO2017123658A1 (en) Light emitting diode display
CA2880718A1 (en) Selective transfer of semiconductor device to a system substrate
TWI820033B (zh) 整合於系統基板中之微裝置
CA2936473A1 (en) Integrated micro-devices and method of assembly
WO2020100127A1 (en) Microdevice cartridge structure
US20220246593A1 (en) Display device using micro-led, and manufacturing method therefor
EP4170736A1 (en) Light-emitting device and display apparatus including the same
US20230207611A1 (en) Micro device integration into system substrate
CN116525532A (zh) 集成器件制造方法
CN113826227A (zh) 集成功能调谐材料与微型装置的方法及其结构

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant