CA2879627A1 - Selective semiconductor device integration into system substrate - Google Patents

Selective semiconductor device integration into system substrate Download PDF

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Publication number
CA2879627A1
CA2879627A1 CA2879627A CA2879627A CA2879627A1 CA 2879627 A1 CA2879627 A1 CA 2879627A1 CA 2879627 A CA2879627 A CA 2879627A CA 2879627 A CA2879627 A CA 2879627A CA 2879627 A1 CA2879627 A1 CA 2879627A1
Authority
CA
Canada
Prior art keywords
pixel
sub
substrate
micro device
integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
CA2879627A
Other languages
French (fr)
Inventor
Unknown
Gholamreza Chaji
Ehsanallah Fathi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ignis Innovation Inc
Original Assignee
Ignis Innovation Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ignis Innovation Inc filed Critical Ignis Innovation Inc
Priority to CA2879627A priority Critical patent/CA2879627A1/en
Priority to CN201680006964.4A priority patent/CN107851586B/en
Priority to DE112016000447.8T priority patent/DE112016000447T5/en
Priority to PCT/IB2016/050307 priority patent/WO2016116889A1/en
Priority to CN202110684431.4A priority patent/CN113410146A/en
Priority to US15/002,662 priority patent/US20160219702A1/en
Priority to US15/060,942 priority patent/US10134803B2/en
Publication of CA2879627A1 publication Critical patent/CA2879627A1/en
Priority to CN201780013977.9A priority patent/CN109075119B/en
Priority to CN202310495809.5A priority patent/CN116525532A/en
Priority to US15/653,120 priority patent/US10700120B2/en
Priority to DE112018003713.4T priority patent/DE112018003713T5/en
Priority to PCT/IB2018/055347 priority patent/WO2019016730A1/en
Priority to TW107124809A priority patent/TWI820033B/en
Priority to KR1020207004053A priority patent/KR20200035048A/en
Priority to CN201880047604.8A priority patent/CN110892530A/en
Priority to US16/107,692 priority patent/US10847571B2/en
Priority to US16/107,680 priority patent/US20180358404A1/en
Priority to US16/912,049 priority patent/US11735623B2/en
Priority to US16/931,132 priority patent/US11728302B2/en
Priority to US17/200,467 priority patent/US20210202572A1/en
Priority to US17/365,634 priority patent/US11735545B2/en
Priority to US17/365,708 priority patent/US11476216B2/en
Priority to US17/569,900 priority patent/US11735546B2/en
Priority to US17/569,893 priority patent/US11728306B2/en
Priority to US17/569,918 priority patent/US11735547B2/en
Priority to US17/730,719 priority patent/US20220254745A1/en
Priority to US18/177,613 priority patent/US20230207611A1/en
Abandoned legal-status Critical Current

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Classifications

    • H—ELECTRICITY
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    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00

Abstract

Post-processing steps for integrating of micro devices into system (receiver) substrate or improving the performance of the micro devices after transfer. Post processing steps for additional structures such as reflective layers, fillers, black matrix or other layers may be used to improve the out coupling or confining of the generated LED light. Dielectric and metallic layers may be used to integrate an electro-optical thin film device into the system substrate with transferred micro devices. Color conversion layers may be integrated into the system substrate to create different outputs from the micro devices.

Description

Inventors Reza Chaji and Ehsan Fathi Introduction Integrating prefabricated semiconductor devices to driving substrate allows development of high efficient and low power displays and other systems.
In one case, it is using thermal transfer of the devices. The donor substrate with semiconductor device puts in contact with system substrate and then the setup is heats up. The devices connected to pads in the system substrate will be connected to the system substrate. After that, laser or other mechanism can be used to disconnect the semiconductor device from the donor substrate.
The main challenge is selective transfer of the semiconductor devices to the system substrate as demonstrate in Figure 1.
Here, the "G" devices should be transferred to "G" pad on the system substrate.
-System Substrate Donor Substrate Figure 1: An example of system and donor substrate.
Selective transfer of semiconductor device using localized heater In one aspect of the invention, localized heater is used that can be selectively turned ON to increase the temperature locally. Before the transfer process, one may do some processing steps on either of the substrate. For example, doing substrate thinning, transferring the devices on another substrate with specific layer deposited on the substrate and detaching (or removing) the original substrate, depositing pads on the substrate, and/or dicing the devices.
After aforementioned processing steps on the donor substrate and system substrate and preparing them for transfer operation, the two substrates are brought together and aligned. Then the temperature is raised to a threshold temperature using global heaters. The global heaters can be either physical heaters that are raising the temperature of each substrate or an environmental chamber with a high temperature. The threshold temperature is selected so that addition of localized heater and global heater can provide enough temperature to create junction between the selected semiconductor device and the pads on the system substrate.
After that the semiconductor devices are released from the donor substrate by other means such as laser.
Global Heater Localized Heater Donor Substrate System Substrate =-= Localized Heater Global Heater Figure 2: Using Localized heaters for selective transfer of the devices from donor substrate to the system substrate.
In one aspect of the invention, the localized heater is made of some resistive layers in the system substrate or in the pads. In one method, the localized heaters can be transferred into a passive matrix that resembles the placement of the semiconductor devices. For example, the devices that are put on the system substrate at once are connected to the same address or drive line or can be addressed without affecting other devices. Figure 3 demonstrate an example of these connections. However, the connection can be any variation that suited the placement easier. Here, if the first and fourth columns are being populated at once, all the horizontal lines are connected to one side of the power supply and the first and fourth vertical lines are connected to the other side of the power supply. However, one can easily apply other combinations such as applying first vertical column and then the fourth column.

Lõõ_ Figure 3: an example of addressable localized heater.
In another aspect of the invention, the localized heater is the pad itself (or part of the pads). In one example, a current is transferred through the pads and the semiconductor device to create the localized heat. Here, the circuit in the system substrate can be used to selectively address each pad and apply a voltage or current to the pads. The donor substrate can have a common electrode either on the top or on between the device and substrate to be connected to the power supply. One also can pattern the electrode to increase the selectivity and reduce the load on the current level. In another example, the pad can be modified to have a heater integrated in it.
In another example, the current can transfer from one pad to the other pads or a dummy pad.
In another aspect of the invention, the localized heater is a laser beam focused on the selected pads or the interface between pads and the semiconductor device or the semiconductor device itself. Here, the donor or system substrate should be transparent to the laser beam to provide access to the pads and/or semiconductor device.
In another aspect of the invention the global heater is also patterned to create a non-uniform heating profile on the substrate enhancing the temperature gap between the selected pads and non-selected pads.
Selective transfer of semiconductor device using adhesive treated pads In another aspect of the invention, the selected pads are treated by adhesive materials. If the adhesive materials are not conductive, only a small area of the pad is covered with the adhesive materials (this area can be outside the conductive area of the pads). The substrates are put together and adhesive layer is cured. After detaching the devices connected to the pads from the donor substrate, the process is repeated till all the pads are covered by the devices (these devices can be different and from different donor substrate). After testing and verifications and other possible processing steps (e.g. isolation, connection, black matrix, planarization, etc.), the populated system substrate is put under annealing temperature and/or pressure to create proper contacts. Then other processing steps may be followed (e.g. contacts, metallization, sealing, and etc.). The order of extra process steps before and after annealing can be different and modified depending on the design and application. Also, one can eliminate the annealing step all together.
Figure 4 displays an example of adhesive treated pads. The pads can be either on the donor substrate or system substrate. In one case, trench can be created in the pads to make sure the adhesive does not block the conducting function of pads if needed. The trench can be in different shape or different places in the pads (e.g. at the edge, center, or cross).
Adhesive =
System Substrate (a) Adhesive Trench =
tt ___________________________________ =
111 Al (b) Figure 4: an example of the adhesive area on the pads on the system substrate.

In another aspect of the invention, the adhesive layer can be curable by electrical current (or voltage or charge). Here a current can be passed through the pads on system substrate to the donor substrate to cure the adhesive layer.
The adhesive layer can be stamped, printed, or patterned by normal lithography on the pads.
General terms The pads profile in all the structure in the document can be either higher than the surface or lower than the surface.
The pads profile in all the structure in the document can be made of few different layers.
The pads can be conductive or nonconductive. Only in case of current annealing the pads are conductive partially or fully.
A device can have multiple functional pads that some of them or none of them are bonded to the system substrate as part of transfer mechanism.
The transfer pads can be functional pads electrically (or optically) or just mechanical support for the transfer.
For optical devices, one can integrate different layers before transferring the device (e.g reflectors) or after transferring (e.g. deflectors) to enhance the light output.
One can combine different methods in this document to enhance the selectivity or speed of transfer mechanism.

Claims (14)

WHAT IS CLAIMED IS:
1. A method of integrated device fabrication, the integrated device comprising a plurality pixels each comprising at least one sub-pixel comprising a micro device integrated on a substrate, the method comprising:
extending an active area of a first sub-pixel to an area larger than an area of a first micro device of the first sub-pixel by patterning of a filler layer about the first micro device and between the first micro device and at least one second micro device.
2. A method according to claim 1 further comprising:
fabricating at least one reflective layer covering at least a portion of one side of the patterned filler layer, the reflective layer for confining at least a portion of incoming or outgoing light within the active area of the sub-pixel.
3. A method according to claim 2 wherein the reflective layer is fabricated as an electrode of the micro device.
4. A method according to claim 1 wherein the patterning of the filler layer further patterns the filler layer about a further sub-pixel.
5. A method according to claim 1 wherein the patterning of the filler layer further is performed with a dielectric filler material.
6. An integrated device comprising:
a plurality pixels each comprising at least one sub-pixel comprising a micro device integrated on a substrate; and a patterned filler layer formed about a first micro device of a first sub-pixel and between the first micro device and at least one second micro device, the patterned filler layer extending an active area of the first sub-pixel to an area larger than an area of the first micro device.
7. An integrated device according to claim 6 further comprising:
at least one reflective layer covering at least a portion of one side of the patterned filler layer, the reflective layer for confining at least a portion of incoming or outgoing light to the active area of the first sub-pixel.
8. An integrated device according to claim 7 wherein the reflective layer is an electrode of the micro device.
9. An integrated device according to claim 7 wherein the patterned filler layer is formed about a further sub-pixel.
10. A method of integrated device fabrication, the device comprising a plurality pixels each comprising at least one sub-pixel comprising a micro device integrated on a substrate, the method comprising:
integrating at least one micro device into a receiver substrate; and subsequently to the integration of the at least one micro device, integrating at least one thin-film electro-optical device into the receiver substrate.
11. A method according to claim 10, wherein integrating the at least one thin-film electro-optical device comprises forming an optical path for the micro device through all or some layers of the at least one electro-optical device.
12. A method according to claim 10 wherein integrating the at least one thin-film electro-optical device is such that an optical path for the micro device is through a surface or area of the integrated device other than a surface or area of the electro-optical device.
13. A method according to claim 10, further comprising fabricating an electrode of the thin-film electro-optical device, the electrode of the thin-film electro-optical device defining an active area of at least one of a pixel and a sub-pixel.
14.
A method of according to claim 10, further comprising fabricating an electrode which serves as a shared electrode of both the thin-film electro-optical device and the light emitting micro device.
CA2879627A 2015-01-23 2015-01-23 Selective semiconductor device integration into system substrate Abandoned CA2879627A1 (en)

Priority Applications (27)

Application Number Priority Date Filing Date Title
CA2879627A CA2879627A1 (en) 2015-01-23 2015-01-23 Selective semiconductor device integration into system substrate
CN201680006964.4A CN107851586B (en) 2015-01-23 2016-01-21 Selective micro device transfer to a receptor substrate
DE112016000447.8T DE112016000447T5 (en) 2015-01-23 2016-01-21 Selective micro-device transfer to a receptor substrate
PCT/IB2016/050307 WO2016116889A1 (en) 2015-01-23 2016-01-21 Selective micro device transfer to receiver substrate
CN202110684431.4A CN113410146A (en) 2015-01-23 2016-01-21 Selective micro device transfer to a receptor substrate
US15/002,662 US20160219702A1 (en) 2015-01-23 2016-01-21 Selective micro device transfer to receiver substrate
US15/060,942 US10134803B2 (en) 2015-01-23 2016-03-04 Micro device integration into system substrate
CN201780013977.9A CN109075119B (en) 2015-01-23 2017-03-06 Integrated device manufacturing method
CN202310495809.5A CN116525532A (en) 2015-01-23 2017-03-06 Integrated device manufacturing method
US15/653,120 US10700120B2 (en) 2015-01-23 2017-07-18 Micro device integration into system substrate
PCT/IB2018/055347 WO2019016730A1 (en) 2015-01-23 2018-07-18 Micro device integration into system substrate
TW107124809A TWI820033B (en) 2017-07-18 2018-07-18 Micro device integration into system substrate
CN201880047604.8A CN110892530A (en) 2015-01-23 2018-07-18 Micro device integration into system substrate
DE112018003713.4T DE112018003713T5 (en) 2015-01-23 2018-07-18 MICRO DEVICE INTEGRATION IN SYSTEM SUBSTRATE
KR1020207004053A KR20200035048A (en) 2015-01-23 2018-07-18 Micro device integration into the system board
US16/107,692 US10847571B2 (en) 2015-01-23 2018-08-21 Micro device integration into system substrate
US16/107,680 US20180358404A1 (en) 2015-01-23 2018-08-21 Micro device integration into system substrate
US16/912,049 US11735623B2 (en) 2015-01-23 2020-06-25 Micro device integration into system substrate
US16/931,132 US11728302B2 (en) 2015-01-23 2020-07-16 Selective micro device transfer to receiver substrate
US17/200,467 US20210202572A1 (en) 2015-01-23 2021-03-12 Micro device integration into system substrate
US17/365,634 US11735545B2 (en) 2015-01-23 2021-07-01 Selective micro device transfer to receiver substrate
US17/365,708 US11476216B2 (en) 2015-01-23 2021-07-01 Selective micro device transfer to receiver substrate
US17/569,900 US11735546B2 (en) 2015-01-23 2022-01-06 Selective micro device transfer to receiver substrate
US17/569,893 US11728306B2 (en) 2015-01-23 2022-01-06 Selective micro device transfer to receiver substrate
US17/569,918 US11735547B2 (en) 2015-01-23 2022-01-06 Selective micro device transfer to receiver substrate
US17/730,719 US20220254745A1 (en) 2015-01-23 2022-04-27 Selective micro device transfer to receiver substrate
US18/177,613 US20230207611A1 (en) 2015-01-23 2023-03-02 Micro device integration into system substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CA2879627A CA2879627A1 (en) 2015-01-23 2015-01-23 Selective semiconductor device integration into system substrate

Publications (1)

Publication Number Publication Date
CA2879627A1 true CA2879627A1 (en) 2016-07-23

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CA2879627A Abandoned CA2879627A1 (en) 2015-01-23 2015-01-23 Selective semiconductor device integration into system substrate

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CA (1) CA2879627A1 (en)

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