CN110783268B - 用于形成半导体的方法以及半导体器件 - Google Patents
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Abstract
本公开涉及用于形成半导体的方法以及半导体器件。一种方法包括在多个半导体鳍上形成栅极堆叠。该多个半导体鳍包括多个内部鳍,以及位于该多个内部鳍的相对侧上的第一外部鳍和第二外部鳍。基于该多个半导体鳍生长外延区域,并且沿着第一外部鳍的外部侧壁测量的外延区域的第一高度小于沿着第一外部鳍的内部侧壁测量的外延区域的第二高度。
Description
技术领域
本公开一般地涉及用于形成半导体的方法以及半导体器件。
背景技术
集成电路(IC)材料和设计的技术进步已经产生了几代IC,其中每一代都具有比上一代更小和更复杂的电路。在IC演进的过程中,功能密度(例如,每芯片面积的互连器件的数目)通常增加,而几何尺寸减小。这种缩小过程通常通过提高生产效率和降低相关成本来提供益处。
这种缩小也增加了处理和制造IC的复杂性,并且为了实现这些进步,需要IC处理和制造中的类似发展。例如,已经引入鳍式场效应晶体管(FinFET)来代替平面晶体管。正在开发FinFET的结构和制造FinFET的方法。
FinFET基于半导体鳍而形成。可以通过在栅极的相对侧上刻蚀半导体鳍的一些部分,并然后在由半导体鳍的刻蚀部分留下的空间中生长适当的材料来形成FinFET的源极和漏极区域。
发明内容
根据本公开的一个实施例,提供了一种用于形成半导体的方法,包括:在块半导体衬底上方形成隔离区域;凹陷所述隔离区域,其中,所述隔离区域之间的半导体条带的顶部部分突出高于所述隔离区域的顶表面以形成鳍组,并且所述鳍组包括:多个内部鳍;以及第一外部鳍和第二外部鳍,位于所述多个内部鳍的相对侧上;以及在所述多个内部鳍、所述第一外部鳍和所述第二外部鳍的侧壁上形成鳍间隔件,其中,所述鳍间隔件包括:外部鳍间隔件,位于所述第一外部鳍的外部侧壁上,其中,所述外部侧壁背离所述鳍组,并且所述外部鳍间隔件具有第一高度;以及内部鳍间隔件,位于所述第一外部鳍的内部侧壁上,其中,所述内部侧壁面向所述多个内部鳍,并且所述内部鳍间隔件具有小于所述第一高度的第二高度。
根据本公开的另一实施例,提供了一种用于形成半导体的方法,包括:在多个半导体鳍上形成栅极堆叠,其中,所述多个半导体鳍包括:多个内部鳍;以及第一外部鳍和第二外部鳍,位于所述多个内部鳍的相对侧上;以及基于所述多个半导体鳍外延生长外延区域,其中,沿着所述第一外部鳍的外部侧壁测量的所述外延区域的第一高度小于沿着所述第一外部鳍的内部侧壁测量的所述外延区域的第二高度。
根据本公开的又一实施例,提供了一种半导体器件,包括:多个半导体鳍,其中,所述多个半导体鳍包括:多个内部鳍;以及第一外部鳍和第二外部鳍,位于所述多个内部鳍的相对侧上;栅极堆叠,位于所述多个半导体鳍的侧壁和顶表面上;鳍间隔件,位于所述栅极堆叠的一侧上,其中,所述鳍间隔件包括:第一外部鳍间隔件和第二外部鳍间隔件,其中,所述第一外部鳍间隔件和所述第二外部鳍间隔件具有第一高度;以及内部鳍间隔件,位于所述第一外部鳍间隔件和所述第二外部鳍间隔件之间,其中,所述内部鳍间隔件具有小于所述第一高度的第二高度;以及半导体区域,位于延伸到每对所述鳍间隔件之间的空间中。
附图说明
在结合附图阅读下面的具体实施方式时,可以从下面的具体实施方式中最佳地理解本公开的各个方面。应当注意,根据行业的标准做法,各种特征不是按比例绘制的。事实上,为了讨论的清楚起见,各种特征的尺寸可能被任意增大或减小。
图1至图3、4A、4B-1至4B-5、5A、5B、6至9和10A示出了根据一些实施例的鳍式场效应晶体管(FinFET)的形成中的中间阶段的横截面图和透视图。
图10B示出了根据一些实施例的具有合并外延区域的FinFET的横截面图。
图11示出了根据一些实施例的具有非合并外延区域的FinFET的横截面图。
图12示出了根据一些实施例的具有非凹陷鳍的FinFET的横截面图。
图13示出了根据一些实施例的用于形成FinFET的工艺流程。
具体实施方式
下面的公开内容提供了用于实现本发明的不同特征的许多不同的实施例或示例。下文描述了组件和布置的具体示例以简化本公开。当然,这些仅仅是示例而不意图是限制性的。例如,在下面的说明中,在第二特征上方或之上形成第一特征可以包括以直接接触的方式形成第一特征和第二特征的实施例,并且还可以包括可以在第一特征和第二特征之间形成附加特征以使得第一特征和第二特征可以不直接接触的实施例。此外,本公开在各个示例中可能重复参考标号和/或字母。这种重复是为了简单性和清楚性的目的,并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
此外,本文中可能使用了空间相关术语(例如“下方”、“之下”、“低于”、“以上”、“上部”等),以易于描述图中所示的一个要素或特征相对于另一个(一些)要素或特征的关系。这些空间相关术语意在涵盖器件在使用或工作中除了图中所示朝向之外的不同朝向。装置可能以其他方式定向(旋转了90度或处于其他朝向),并且本文中所用的空间相关描述符同样可能被相应地解释。
根据一些实施例提供了鳍式场效应晶体管(FinFET)及其形成方法。根据一些实施例示出了形成FinFET的中间阶段。讨论了一些实施例的一些变体。在各种视图和说明性实施例中,相同的附图标记用于表示相同的元件。根据一些实施例,FinFET的鳍间隔件被形成为具有不同的高度,外部鳍间隔件的高度大于内部鳍间隔件的高度。结果,增加了鳍之间的外延区域的体积,并且增加了外延区域施加的应变。还降低了桥接相邻FinFET的外延区域的风险。
图1至图3、4A、4B-1至4B-5、5A、5B、6至9和10A示出了根据本公开的一些实施例的FinFET的形成中的中间阶段的透视图和横截面图。相应附图中所示的步骤还被示意性地反映在图13中所示的工艺流程中。
图1示出了初始结构的透视图。初始结构包括晶片10,晶片10还包括衬底20。衬底20可以是半导体衬底,其可以是硅衬底、硅锗衬底、或者由其他半导体材料形成的衬底。衬底20可以掺杂有p型或n型杂质。诸如浅沟槽隔离(STI)区域之类的隔离区域22可以被形成为从衬底20的顶表面延伸到衬底20中。相邻STI区域22之间的衬底20的部分被称为半导体条带24。根据一些实施例,半导体条带24的顶表面和STI区域22的顶表面可以基本上彼此齐平。
STI区域22可以包括电介质衬垫(未示出),其可以由氧化硅、氮化硅等形成。可以使用例如原子层沉积(ALD)、高密度等离子体化学气相沉积(HDPCVD)或化学气相沉积(CVD)来沉积电介质衬垫。STI区域22还可以包括电介质衬垫上方的电介质材料(例如,氧化硅),其中,电介质材料可以使用可流动化学气相沉积(FCVD)、旋涂等来形成。
参考图2,STI区域22被凹陷以使得半导体条带24的顶部突出高于STI区域22的顶表面22A,以形成突出的鳍24’。相应的工艺在图13所示的工艺流程中被示出为工艺202。STI区域22中的半导体条带24的部分仍被称为半导体条带。可以使用干法刻蚀工艺来执行刻蚀,其中,HF和NH3的混合物可以用作刻蚀气体。也可以使用NF3和NH3的混合物作为刻蚀气体进行刻蚀。在刻蚀工艺期间,可以产生等离子体。还可以包括氩。根据本公开的替代实施例,使用湿法刻蚀工艺来执行STI区域22的凹陷。例如,刻蚀化学品可以包括HF溶液。
根据一些实施例,可以通过任何适当的方法来形成/图案化用于形成FinFET的鳍。例如,可以使用一个或多个光刻工艺来对鳍进行图案化,包括双图案化或多图案化工艺。通常,双图案化或多图案化工艺组合光刻和自对准工艺,允许创建具有例如比使用单个直接光刻工艺以其他方式可以获得的间距更小的间距的图案。例如,在一个实施例中,在衬底上方形成牺牲层并使用光刻工艺进行图案化。使用自对准工艺在经图案化的牺牲层旁边形成间隔件。然后移除牺牲层,并且然后可以使用剩余的间隔件或心轴来对鳍进行图案化。
参考图3,在突出的鳍24’的顶表面和侧壁上形成虚设栅极堆叠30。相应的工艺在图13所示的工艺流程中被示出为工艺204。应理解,尽管为了清楚起见示出了两个虚设栅极堆叠30,但可以形成单个或多于两个(彼此平行的)虚设栅极堆叠,并且该多个虚设栅极堆叠跨相同的(一个或多个)半导体鳍24’。虚设栅极堆叠30可以包括虚设栅极电介质32和虚设栅极电介质32上方的虚设栅极电极34。可以使用例如非晶硅或多晶硅并且还可以使用其他材料来形成虚设栅极电极34。每个虚设栅极堆叠30还可以包括虚设栅极电极34上方的一个(或多个)硬掩模层36。硬掩模层36可以由氮化硅、碳氮化硅等形成。虚设栅极堆叠30还具有垂直于突出的鳍24’的长度方向的长度方向。
接下来,在虚设栅极堆叠30的侧壁上形成密封间隔件38A。相应的工艺在图13所示的工艺流程中被示出为工艺206。根据本公开的一些实施例,密封间隔件38A由诸如氧化硅、碳-氮氧化硅(SiCN)、氮化硅等之类的电介质材料形成。密封间隔件38A的形成可以包括使用诸如ALD、CVD等之类的共形沉积方法来沉积共形电介质层,然后执行各向异性刻蚀以移除鳍24’的顶部和侧壁上的部分。
在形成密封间隔件38A之后,可以执行注入以注入n型杂质或p型杂质,以在暴露的突出的鳍24’中形成轻微掺杂漏极/源极(LDD)区域37。例如,当将形成的相应FinFET是n型FinFET时,可以注入诸如磷、砷等之类的n型杂质。当将形成的相应FinFET是p型FinFET时,可以注入诸如硼、铟、镓等之类的p型杂质。在后续附图中,未示出LDD区域37,而它们可仍然存在。
图4A示出了形成栅极间隔件物38B和鳍间隔件39。相应的工艺在图13所示的工艺流程中被示出为工艺208。根据本公开的一些实施例,栅极间隔件38B是多层栅极间隔件,并且形成工艺可以包括在第一电介质层上方覆盖沉积第一电介质层和第二电介质层,并然后执行各向异性刻蚀以移除鳍24’的顶部和侧壁上的第一和第二电介质层的部分。电介质层的其余部分是栅极间隔件38B。密封间隔件38A和栅极间隔件38B在下文中被组合称为栅极间隔件38。
图4A还示出了在突出的鳍24’的侧壁上形成的鳍间隔件39。根据本公开的一些实施例,在共同的形成工艺中同时形成鳍间隔件39和栅极间隔件38B。例如,在用于形成栅极间隔件38B的工艺中,被沉积用于形成栅极间隔件38B的(一个或多个)覆盖电介质层在被刻蚀时可以在突出的鳍24’的侧壁上留下一些部分,因此形成鳍间隔件39。
图4B-1至4B-5示出了根据一些实施例的鳍间隔件39的形成中的中间阶段的横截面图。图4B-1至4B-5中的横截面图是从包含图4A中的线A-A的垂直平面获得的。栅极间隔件38B被同时形成并且未被示出,因为栅极间隔件38B处于与图4B-1至4B-5中所示平面不同的平面中。参考图4B-1,形成间隔层140,其可以被形成为共形层。间隔层140由诸如氮化硅、氧化硅、氮氧化硅、碳氮化硅、氮碳氧化硅等之类的电介质材料形成。间隔层140包括在突出的鳍24’的顶表面和侧壁上的一些部分,并且还包括在密封间隔件38A上以及栅极堆叠30的顶表面上的一些部分。间隔层140可以具有在约2nm和约10nm之间的范围内的厚度。如图所示的突出的鳍24’被紧密地定位以形成鳍组。用于形成同一FinFET的突出的鳍可以在同一鳍组中,该鳍组与相邻FinFET的鳍组间隔开。鳍组中的突出的鳍24’之间的距离S1小于紧邻的鳍组之间(或鳍组与相邻的分立鳍之间)的距离S2。例如,比率S2/S1可以大于约2.0或大于约5.0。突出的鳍24’可以具有均匀的间距P1。在整个说明书中,鳍组中的两个最外面的鳍24’(标记为24’A)被称为鳍组的外部鳍,并且外部鳍24’A之间的鳍24’B被称为鳍组的内部鳍。
然后执行各向异性刻蚀以刻蚀间隔层140。根据本公开的一些实施例,控制刻蚀工艺以使得鳍间隔件39(包括39A和39B)具有如图4B-5所示的轮廓。位于鳍组的外侧的鳍间隔件39A在下文中被称为(鳍组的)外部鳍间隔件,并且在鳍组的内部并且在鳍组中的突出的鳍24’之间的间隔件39B在下文中被称为(鳍组的)内部间隔件。根据一些实施例,外部间隔件39A的高度H1大于内部间隔件39B的高度H2。高度差(H1-H2)可以大于约10nm,并且可以在约30nm和约80nm之间的范围内。高度差(H1-H2)还可以大于突出的鳍24’的高度H3的约2.5%。
为了实现期望的高度差(H1-H2),控制刻蚀工艺条件,该工艺条件包括刻蚀气体的组成、用于刻蚀的功率等。结果,间隔层140(图4B-1)被刻蚀。参照图4B-2,在刻蚀工艺中,还形成诸如含碳层之类的层142。层142可以是聚合物层,因此在下文中称为聚合物层142。聚合物层142可以包括CxFy,其中x和y为整数。根据本公开的一些实施例,聚合物142的外部部分(该外部部分位于鳍组的外侧)具有厚度T1,并且聚合物142的内部部分(在鳍组中)具有厚度T2,该厚度T2小于厚度T1。比率T1/T2可以大于约1.1,并且可以在约1.1和约5之间的范围内。结果,由于聚合物层142的保护,外部部分的刻蚀速率低于内部部分的刻蚀速率。
根据本公开的一些实施例,刻蚀气体可以包括主要用于刻蚀的元素和主要用于形成聚合物的元素。根据一些实施例,刻蚀气体包括CH3F、CH2F2、CHF3或其组合。刻蚀气体中的氟用于刻蚀,并且刻蚀气体中的碳和氟用于形成聚合物。在后续讨论中,碳被称为聚合物形成气体,尽管氟也部分地用作聚合物形成气体。因此,根据一些实施例,CF4、CH3F、CH2F2、CHF3中的每一个可以用作刻蚀气体和聚合物形成气体二者。根据其他实施例,刻蚀气体和聚合物形成气体可以是不同的气体。刻蚀气体(例如,含氟)与聚合物形成气体(例如,含碳)的相对量影响刻蚀行为。例如,由于同一鳍组中的突出的鳍24’之间的内部间隔小于鳍组之间的距离,因此存在(鳍图案)隔离(iso)区域(鳍组之间的间隔)和(鳍图案)密集区域(同一鳍组中的鳍24’之间的间隔)。在间隔层140的刻蚀期间,间隔层140倾向于在隔离区域中具有比在密集区域中更高的刻蚀速率,因为与密集区域相比刻蚀气体更容易进入隔离区域。类似地,聚合物倾向于在隔离区域中具有比在密集区域中更高的累积速率,因为与密集区域相比聚合物形成气体更容易进入隔离区域。聚合物可以保护间隔层140不被刻蚀,并且可以减小间隔层140的刻蚀速率。因此,调节刻蚀气体与聚合物形成气体的比率(当使用上述气体时,比率F/C)以在鳍组的外部生成比在鳍组的内部更多的聚合物,使得间隔层140的外部的刻蚀速率被减小到使得高度H1(图4B-5)大于高度H2的量。
例如,CH3F具有1的F/C比,CH2F2具有2的F/C比,并且CHF3具有3的F/C比。因此,CHF3可以具有比CH2F2更高的刻蚀速率和更低的聚合物累积速率,并且CH2F2可以具有比CH3F更高的刻蚀速率和更低的聚合物累积速率。混合CF4、CH3F、CH2F2和CHF3并选择这些气体的适当比率可以进一步调节F/C比。此外,在刻蚀气体中,可以添加少量其他气体,例如H2和O2。H2可以与刻蚀气体中的氟反应,使得氟的量减少,降低F/C比。O2可以与刻蚀气体中的碳反应,使得碳的量减少,提高F/C比。可以理解,刻蚀的机制和因素是复杂的,并且实际刻蚀速率和聚合物累积速率受各种因素的影响。例如,由于氟也用作聚合物形成气体,这使得氟增加而影响刻蚀速率和聚合物形成速率二者。因此,增加F/C比可能不总是使得(聚合物142的)厚度比T1/T2增加。可以进行实验来微调工艺条件以在隔离和密集区域中实现期望的刻蚀速率和聚合物累积速率,并且实现期望的厚度比T1/T2(图4B-2)。
此外,为了增加厚度比T1/T2,调节在其中执行刻蚀的刻蚀腔室的主功率和偏置功率。例如,在其中放置晶片10以用于刻蚀间隔层140的刻蚀腔室可以具有主(RF)功率,其可以通过线圈和主电源(未示出)提供。主功率从刻蚀气体生成等离子体。偏置电压源可以连接到其上放置晶片10的卡盘(chunck)以提供偏置功率。主电源和偏置电压源由控制单元控制。当主电源开启并且偏置功率也开启时,间隔层140被刻蚀,并生成较少的聚合物层142(图4B-2)。当主电源开启并且偏置功率关闭时,刻蚀效果显著降低并且可以基本上消除,同时生成并累积聚合物142。可以开启和关闭(脉冲)偏置功率以具有多个周期,并且可以调整相应的占空比(开启时间/(开启时间+关闭时间)的比率)。例如,减小占空比可以使得比率H1/H2(图4B-5)增加,并且增加占空比可以使得致比率H1/H2减小。因此,通过开启和关闭偏置功率并调整占空比,可以控制刻蚀速率和聚合物累积速率,以产生期望的聚合物厚度差异(T1-T2)(图4B-2),这会影响刻蚀过程以产生期望的高度差(H1-H2)(图4B-5)。
除了偏置电压/功率的脉冲之外,用于生成等离子体的主功率也可以被脉冲(以多个周期开启和关闭)。偏置功率和主功率的脉冲的组合效果可以进一步调整所得到的鳍间隔件39的轮廓。主功率和偏置功率的占空比可以被同步,其包括主功率和偏置同时开启并同时关闭,或者在偏置功率关闭时开启主功率,反之亦然。替代地,可以以非同步模式施加主功率的脉冲和偏置功率的脉冲。
根据一些实施例,在刻蚀工艺中,CF4、CH3F、CH2F2、CHF3、H2、CO、O2及其组合可以用作刻蚀气体,并且还可以添加Ar和/或He。例如,刻蚀气体可以包括CHF3(其流速在约150sccm和约500sccm之间的范围内)和CH3F(其流速在约10sccm和约50sccm之间的范围内)。腔室压力可以在约3毫托和约900毫托之间的范围内。O2可以具有约5sccm和约50sccm之间的流速。晶片温度可以在约-50℃和约200℃之间的范围内。主(RF)功率可以在约50瓦特和约2000瓦特之间的范围内,并且通过主功率的脉冲提供连续等离子体或等离子体脉冲。当提供脉冲时,脉冲的频率可以在约0.01KHz和约10KHz之间的范围内。主功率的占空比可以在约10%和约90%之间的范围内,并且可以在约20%和约60%之间的范围内。偏置功率可以在约50瓦特和约2000瓦特之间的范围内,并且可以连续地或以脉冲施加。当提供脉冲时,脉冲的频率可以在约0.01KHz和约10KHz之间的范围内。偏置功率的占空比可以在约10%和约90%之间的范围内,并且可以在约20%和约60%之间的范围内。
再次参考图4B-2,可以存在用于主功率和偏置功率的多个占空比,因此可以存在用于累积聚合物然后刻蚀间隔层140的多个循环。根据本公开的一些实施例,在刻蚀一段时间之后,例如使用O2气体来移除累积的聚合物层142。所得到的结构如图4B-3所示,其中间隔层140的顶部已经变薄。
参考图4B-2和4B-3描述的工艺可以作为循环来重复,其可以在1个循环至约100个循环的范围内。图4B-4示出了聚合物层142的累积和间隔层140的连续刻蚀。作为刻蚀的结果,形成鳍间隔件39,如图4B-5所示。图4A还示出了相应晶片10的透视图,其还示出了栅极间隔件38B。
在形成如图4A和4B-5所示的鳍间隔件39之后,执行刻蚀工艺(下文中也称为鳍凹陷工艺)以凹陷未被虚设栅极堆叠30和栅极间隔件38覆盖的突出的鳍24’的部分,产生图5A所示的结构。相应的工艺在图13所示的工艺流程中被示出为工艺210。凹陷可以是各向异性的,因此保护直接位于虚设栅极堆叠30和栅极间隔件38下面的鳍24’的部分免受刻蚀。根据一些实施例,凹陷的半导体条带24的顶表面可以低于STI区域22的顶表面22A。因此,在STI区域22之间形成凹陷40。凹陷40还位于虚设栅极堆叠30的相对侧。凹陷40的底表面可以高于STI区域22的底表面22B,并且低于STI区域22的顶表面22A。在形成凹陷40之后留下鳍间隔件39。
根据一些实施例,在与图4A和4B-5中所示的晶片/管芯相同的晶片和相同的器件管芯上,一些突出的鳍24’未被刻蚀,并且基于未刻蚀的突出的鳍24’形成源极/漏极区域。例如,图12示出了未刻蚀的鳍24'和相应的源极/漏极区域。根据本公开的一些实施例,针对p型FinFET在突出的鳍上执行鳍凹陷,并且针对n型FinFET在突出的鳍上不执行鳍凹陷。
根据本公开的一些实施例,通过干法刻蚀步骤执行凹陷。可以使用诸如C2F6;CF4;SO2;HBr、Cl2和O2的混合物;HBr、Cl2和O2的混合物;或HBr、Cl2、O2和CF2的混合物等之类的工艺气体来执行干法刻蚀。根据本公开的替代实施例,通过湿法刻蚀步骤执行凹陷。可以使用KOH、氢氧化四甲基铵(TMAH)、CH3COOH、NH4OH、H2O2、异丙醇(IPA)或HF、HNO3和H2O的溶液来执行湿法刻蚀,
图5B示出了图5A中所示结构的横截面视图,并且横截面视图是从包含图5A中的箭头5B-5B的垂直平面获得的。根据本公开的一些实施例,如图5B所示,凹陷40具有基本上垂直的边缘,其基本上与鳍间隔件39的内边缘齐平。
图6示出了用于形成外延区域42的外延工艺。相应的工艺在图13所示的工艺流程中被示出为工艺212。在整个说明书中,外延区域42也被称为源极/漏极区域42。使用虚线标记突出的鳍24’,其在栅极堆叠30下面并且因此不在图示的平面中。外延区域42的形成方法可以包括CVD、等离子体增强化学气相沉积(PECVD)等。根据一些实施例,外延区域42包括硅锗、硅或硅碳。根据所得的FinFET是p型FinFET还是n型FinFET,可以利用进行外延来原位掺杂p型或n型杂质。例如,当所得的FinFET是p型FinFET时,可以生长硅锗硼(SiGeB)、GeB等,并且外延区域42是p型。相反,当所得的FinFET是n型FinFET时,可以生长硅磷(SiP)、硅碳磷(SiCP)等。根据本公开的替代实施例,外延区域42由III-V化合物半导体形成,例如,GaAs、InP、GaN、InGaAs、InAlAs、GaSb、AlSb、AlAs、AlP,GaP、其组合、或其多个层。在外延区域42完全填充凹陷40之后,外延区域42开始水平扩展,并且可以形成小平面。
当在形成外延区域42之前突出的鳍24’未被凹陷时,由于外部间隔件39A高于内部间隔件39B,因此突出的鳍24’的面向组间空间的外部侧壁表面具有比突出的鳍24’的面向内组空间的内部侧壁表面更小的面积和高度。因此,从内部侧壁表面生长的外延区域42的部分的高度H5大于从外部侧壁表面生长的外延区域42的部分的高度H4。当突出的鳍24’被凹陷时,将发生类似的结果。高度H4和H5是从相应的鳍间隔件39A和39B的垂直于外延区域42的相应顶表面的的顶端测量的高度。换句话说,高度H4是从最外面的突出的鳍24’的外部侧壁垂直向上测量的,并且高度H5是从最外面的突出的鳍24’的内部侧壁垂直向上测量的。尽管突出的鳍24’可能不在图示的平面中(除非该平面是栅极间隔件38B的外部侧壁),但可以确定突出的鳍24’的位置。例如,如果制作透射电子显微镜(TEM)图像以捕获图6中所示的横截面图的图像,则鳍24’在TEM图像中可见。
根据一些实施例,高度H5大于高度H4。高度差(H5-H4)可以大于约2nm,并且可以在约2nm和约10nm之间的范围内。此外,从突出的鳍24’的外部侧壁表面生长的外延区域42的部分的厚度T4小于从突出的鳍24’的内部侧壁表面生长的外延区域42的部分的厚度T5。厚度差(T5-T4)可以大于约2nm,并且可以在约2nm和约10nm之间的范围内。在厚度T4较小的情况下,外延区域42桥接到最近的相邻FinFET的外延区域42的可能性降低。
根据一些实施例,在从不同的鳍24’生长的外延区域42彼此间隔开时完成外延区域42的形成,并在最终FinFET中形成未合并的源极/漏极外延区域42。因此,如图6所示的外延区域42反映了相应的最终FinFET中的结构。根据替代实施例,进一步生长外延区域42以产生图7中所示的结构。外延区域42的相应外部高度和内部高度被称为H4’和H5’。根据一些实施例,高度H5’大于高度H4’。高度差(H5’-H4’)可以大于约2nm,并且可以在约2nm和约8nm之间的范围内。在相邻的鳍间隔件39之间形成气隙43。
图8示出了图7中所示结构的透视图。图9示出了在形成接触刻蚀停止层(CESL)46和层间电介质(ILD)48之后的结构的透视图。相应的工艺在图13所示的工艺流程中被示出为工艺214。CESL 46可以由氮化硅、碳氮化硅等形成。根据本公开的一些实施例,使用诸如ALD或CVD之类的共形沉积方法形成CESL 46。ILD 48可以包括使用例如可流动化学气相沉积(FCVD)、旋涂、CVD或其他沉积方法形成的电介质材料。ILD 48还可以由含氧电介质材料形成,其可以是基于氧化硅的材料,例如,正硅酸乙酯(TEOS)氧化物、PECVD氧化物(SiO2)、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂的磷硅酸盐玻璃(BPSG)等。可以执行诸如化学机械抛光(CMP)工艺或机械研磨工艺之类的平坦化工艺以使得ILD 48和栅极间隔件38的顶表面彼此齐平。
图9还示出了替换栅极50的形成。相应的工艺在图13所示的工艺流程中被示出为工艺216。形成工艺包括移除虚设栅极堆叠30(图8)的剩余部分以形成沟槽,并在所得到的沟槽中形成替换栅极50。替换栅极50包括栅极电介质52和金属栅极电极54。根据本公开的一些实施例,每个栅极电介质52包括界面层(IL,未单独示出)作为其较下部分。在突出的鳍24’的暴露表面上形成IL。IL可以包括氧化物层,例如,氧化硅层,其通过突出的鳍24’(图8中未示出)的热氧化、化学氧化工艺或沉积工艺形成。栅极电介质层52还可以包括在IL上方形成的高k电介质层(未单独示出)。高k电介质层可以包括高k电介质材料,例如,氧化铪、氧化镧、氧化铝、氧化锆等。高k电介质材料的电介质常数(k值)高于3.9,并且可高于约7.0。高k电介质层覆盖并且可以接触IL。高k电介质层52可以被形成为共形层,并且在突出的鳍24’的侧壁和栅极间隔件38的侧壁上延伸。根据本公开的一些实施例,使用ALD或CVD来形成高k电介质层。
栅极电极54可以包括扩散阻挡层和在扩散阻挡层上方的一个(或多个)功函数层。扩散阻挡层可以由氮化钛(TiN)形成,其可以(或可以不)掺杂硅。功函数层确定栅极的功函数,并且包括至少一个层或由不同材料形成的多个层。例如,功函数层的材料可以包括TaN层和TaN层上方的钛铝(TiAl)层。在沉积(一个或多个)功函数层之后,形成另一阻挡层,其可以是另一TiN层。诸如钨或钴之类的填充金属可以填充由被移除的虚设栅极留下的剩余沟槽。然后可以执行平坦化工艺以移除扩散阻挡层、功函数层、填充金属等的多余部分以形成栅极电极54。
还如图9所示,在栅极堆叠50上方并且在栅极间隔件38之间形成硬掩模56。硬掩模56可以由氮化硅、碳化硅、碳氮化硅、碳氮氧化硅等形成。硬掩模56的形成可以包括凹陷替换栅极堆叠50、用电介质材料填充所得到的凹陷、以及执行平坦化工艺以移除电介质材料的多余部分。
参考图10A,移除ILD 48和CESL 46的一些部分以形成接触开口(由接触插塞60占据),然后硅化源极/漏极区域42的暴露部分以形成源极/漏极硅化物区域58。相应的工艺在图13所示的工艺流程中被示出为工艺218。将诸如钨之类的导电材料填充到接触开口中以形成源极/漏极接触插塞60。相应的工艺在图13所示的工艺流程中被示出为工艺220。因此形成了FinFET 62和相应的源极/漏极接触插塞。根据本公开的一些实施例,如图10所示,基于不同的鳍形成的源极/漏极区域42被合并。根据本公开的其他实施例,基于不同的鳍形成的源极/漏极区域保持彼此分离。
图10B示出了图10A中所示结构的横截面视图,其中,图10B中所示的结构是从包含图10A中的线10B-10B的垂直平面获得的。外延区域42的相应的外部高度和内部高度被称为H4”和H5”。根据一些实施例,高度H5”大于高度H4”。高度差(H5”-H4”)可以大于约2nm,并且可以在约2nm和约8nm之间的范围内。
图11示出了具有未合并的外延区域42的FinFET 62’的截面图。外延区域42的相应的外部高度和内部高度分别被称为H4”’和H5”’。根据一些实施例,高度H5”’大于高度H4”’。高度差(H5”’-H4”’)可以大于约2nm,并且可以在约2nm和约10nm之间的范围内。此外,从突出的鳍24’的外部侧壁表面生长的外延区域42的部分的厚度T4’小于从突出的鳍24’的内部侧壁表面生长的外延区域42的部分的厚度T5’。厚度差(T5’-T4’)可以大于约2nm,并且可以在约2nm和约10nm之间的范围内。应当理解,图10A和图10B中所示的FinFET 62可以与图11中所示的FinFET 62’在同一管芯和同一晶片上共存。
图12示出了FinFET 62”,其中,突出的鳍24’未被刻蚀,并且基于未刻蚀的突出的鳍24’形成外延(源极/漏极区域)42’。根据本公开的一些实施例,FinFET 62”是n型FinFET,并且相应的外延区域42是n型,并且可以由SiP、SiCP、Si等形成。此外,外延区域42’可以具有圆形外表面,而不是具有基本上直的小平面。外延区域42’的相应的外部高度(从外部鳍间隔件39A的顶表面测量)和内部高度(从内部鳍间隔件39B的顶表面测量)分别被称为H6和H7。根据一些实施例,高度H7大于高度H6。高度差(H7-H6)可以大于约2nm,并且可以在约2nm和约10nm之间的范围内。
本公开的实施例具有一些有利特征。通过控制用于形成鳍间隔件的刻蚀工艺,外延区域的组内部分具有比外延区域的外部部分更高的高度。这使得外延区域的体积增加,并使得外延区域生成的应变增加。此外,降低了外延区域桥接的可能性。
根据本公开的一些实施例,一种方法包括在块半导体衬底上方形成隔离区域;凹陷隔离区域,其中,隔离区域之间的半导体条带的顶部部分突出高于隔离区域的顶表面以形成鳍组,并且鳍组具有多个内部鳍,以及位于该多个内部鳍的相对侧上的第一外部鳍和第二外部鳍;以及在该多个内部鳍、第一外部鳍和第二外部鳍的侧壁上形成鳍间隔件,其中,鳍间隔件包括在第一外部鳍的外部侧壁上的外部鳍间隔件,其中,外部侧壁背离鳍组,并且外部鳍间隔件具有第一高度;以及第一外部鳍的内部侧壁上的内部鳍间隔件,其中,内部侧壁面向该多个内部鳍,并且内部鳍间隔件具有小于第一高度的第二高度。在实施例中,第一高度比第二高度大的高度差大于约2nm。在实施例中,外部鳍间隔件和内部鳍间隔件以共同的工艺形成。在实施例中,该方法还包括形成栅极堆叠,其中,栅极堆叠在多个内部鳍、第一外部鳍和第二外部鳍中的每一项的侧壁和顶部表面上延伸。在实施例中,该方法还包括在栅极堆叠的侧壁上形成栅极间隔件,其中,栅极间隔件和鳍间隔件以共同的形成工艺形成。在实施例中,该方法还包括基于该多个内部鳍、第一外部鳍和第二外部鳍来外延生长外延区域,其中,直接在外部鳍间隔件上方测量的外延区域的第三高度小于直接在内部鳍间隔件上方测量的外延区域的第四高度。在实施例中,第四高度比第三高度大的高度差大于约2nm。在实施例中,外延生长外延区域包括以多个周期脉冲偏置电压。在实施例中,脉冲的占空比在约10%和约90%之间的范围内。
根据本公开的一些实施例,一种方法包括在多个半导体鳍上形成栅极堆叠,其中,该多个半导体鳍包括:多个内部鳍;以及位于该多个内部鳍的相对侧上的第一外部鳍和第二外部鳍;以及基于该多个半导体鳍外延生长外延区域,其中,沿着第一外部鳍的外部侧壁测量的外延区域的第一高度小于沿着第一外部鳍的内部侧壁测量的外延区域的第二高度。在实施例中,第一高度和第二高度之间的差大于约2nm。在实施例中,基于多个半导体鳍形成的外延区域被合并。在实施例中,基于多个半导体鳍形成的外延区域未被合并。在实施例中,该方法还包括在栅极堆叠的侧壁上形成栅极间隔件;并且在用于形成栅极间隔件的同一工艺中,在多个半导体鳍的侧壁上形成鳍间隔件,其中,鳍间隔件包括:第一外部鳍间隔件和第二外部鳍间隔件,其中,第一外部鳍间隔件和第二外部鳍间隔件具有第三高度;以及第一外部鳍间隔件和第二外部鳍间隔件之间的内部鳍间隔件,其中,内部鳍间隔件具有小于第三高度的第四高度。在实施例中,第三高度和第四高度之间的差大于约2nm。
根据本公开的一些实施例,一种器件包括多个半导体鳍,其中,该多个半导体鳍包括:多个内部鳍;以及该多个内部鳍的相对侧上的第一外部鳍和第二外部鳍;该多个半导体鳍的侧壁和顶表面上的栅极堆叠;栅极堆叠的一侧上的鳍间隔件,其中,鳍间隔件包括:第一外部鳍间隔件和第二外部鳍间隔件,其中,第一外部鳍间隔件和第二外部鳍间隔件具有第一高度;以及第一外部鳍间隔件和第二外部鳍间隔件之间的内部鳍间隔件,其中,内部鳍间隔件具有小于第一高度的第二高度;以及延伸到每对鳍间隔件之间的空间中的半导体区域。在实施例中,第一高度和第二高度之间的差大于约2nm。在实施例中,器件还包括在栅极堆叠的侧壁上的栅极间隔件,其中,鳍间隔件连续地连接到栅极间隔件。在实施例中,直接在第一外部鳍间隔件上方测量的半导体区域的第一高度小于直接在内部鳍间隔件上方测量的半导体区域的第二高度。在实施例中,半导体区域被合并为连续半导体区域。
上文概述了一些实施例的特征,以使本领域技术人员可以更好地理解本公开的各个方面。本领域技术人员应理解,他们可以容易地使用本公开作为基础来设计或修改其他工艺和结构,以实施与本文所介绍的实施例相同的目的和/或实现相同的优点。本领域技术人员还应当意识到,这些等同构造并不脱离本公开的精神和范围,并且它们可以在不脱离本公开的精神和范围的情况下进行各种改变、替代和变更。
示例1是一种用于形成半导体的方法,包括:在块半导体衬底上方形成隔离区域;凹陷所述隔离区域,其中,所述隔离区域之间的半导体条带的顶部部分突出高于所述隔离区域的顶表面以形成鳍组,并且所述鳍组包括:多个内部鳍;以及第一外部鳍和第二外部鳍,位于所述多个内部鳍的相对侧上;以及在所述多个内部鳍、所述第一外部鳍和所述第二外部鳍的侧壁上形成鳍间隔件,其中,所述鳍间隔件包括:外部鳍间隔件,位于所述第一外部鳍的外部侧壁上,其中,所述外部侧壁背离所述鳍组,并且所述外部鳍间隔件具有第一高度;以及内部鳍间隔件,位于所述第一外部鳍的内部侧壁上,其中,所述内部侧壁面向所述多个内部鳍,并且所述内部鳍间隔件具有小于所述第一高度的第二高度。
示例2是示例1所述的方法,其中,所述第一高度比所述第二高度大,高度差大于约2nm。
示例3是示例1所述的方法,其中,所述外部鳍间隔件和所述内部鳍间隔件以共同的工艺形成。
示例4是示例1所述的方法,还包括形成栅极堆叠,其中,所述栅极堆叠在所述多个内部鳍、所述第一外部鳍和所述第二外部鳍中的每一项的侧壁和顶部表面上延伸。
示例5是示例4所述的方法,还包括在所述栅极堆叠的侧壁上形成栅极间隔件,其中,所述栅极间隔件和所述鳍间隔件以共同的形成工艺形成。
示例6是示例1所述的方法,还包括基于所述多个内部鳍、所述第一外部鳍和所述第二外部鳍来外延生长外延区域,其中,直接在所述外部鳍间隔件上方测量的所述外延区域的第三高度小于直接在所述内部鳍间隔件上方测量的所述外延区域的第四高度。
示例7是示例6所述的方法,其中,所述第四高度比所述第三高度大,高度差大于约2nm。
示例8是示例6所述的方法,其中,所述外延生长外延区域包括用多个周期来脉冲偏置电压。
示例9是示例8所述的方法,其中,所述脉冲的占空比在约10%和约90%之间的范围内。
示例10是一种用于形成半导体的方法,包括:在多个半导体鳍上形成栅极堆叠,其中,所述多个半导体鳍包括:多个内部鳍;以及第一外部鳍和第二外部鳍,位于所述多个内部鳍的相对侧上;以及基于所述多个半导体鳍外延生长外延区域,其中,沿着所述第一外部鳍的外部侧壁测量的所述外延区域的第一高度小于沿着所述第一外部鳍的内部侧壁测量的所述外延区域的第二高度。
示例11是示例10所述的方法,其中,所述第一高度和所述第二高度之间的差大于约2nm。
示例12是示例10所述的方法,其中,基于所述多个半导体鳍形成的所述外延区域被合并。
示例13是示例10所述的方法,其中,基于所述多个半导体鳍形成的所述外延区域未被合并。
示例14是示例10所述的方法,还包括:在所述栅极堆叠的侧壁上形成栅极间隔件;并且在用于形成所述栅极间隔件的同一工艺中,在所述多个半导体鳍的侧壁上形成鳍间隔件,其中,所述鳍间隔件包括:第一外部鳍间隔件和第二外部鳍间隔件,其中,所述第一外部鳍间隔件和所述第二外部鳍间隔件具有第三高度;以及内部鳍间隔件,位于所述第一外部鳍间隔件和所述第二外部鳍间隔件之间,其中,所述内部鳍间隔件具有小于所述第三高度的第四高度。
示例15是示例14所述的方法,其中,所述第三高度和所述第四高度之间的差大于约2nm。
示例16是一种半导体器件,包括:多个半导体鳍,其中,所述多个半导体鳍包括:多个内部鳍;以及第一外部鳍和第二外部鳍,位于所述多个内部鳍的相对侧上;栅极堆叠,位于所述多个半导体鳍的侧壁和顶表面上;鳍间隔件,位于所述栅极堆叠的一侧上,其中,所述鳍间隔件包括:第一外部鳍间隔件和第二外部鳍间隔件,其中,所述第一外部鳍间隔件和所述第二外部鳍间隔件具有第一高度;以及内部鳍间隔件,位于所述第一外部鳍间隔件和所述第二外部鳍间隔件之间,其中,所述内部鳍间隔件具有小于所述第一高度的第二高度;以及半导体区域,延伸到每对所述鳍间隔件之间的空间中。
示例17是示例16所述的器件,其中,所述第一高度和所述第二高度之间的差大于约2nm。
示例18是示例16所述的器件,还包括栅极间隔件,位于所述栅极堆叠的侧壁上,其中,所述鳍间隔件连续地连接到所述栅极间隔件。
示例19是示例16所述的器件,其中,直接在所述第一外部鳍间隔件上方测量的所述半导体区域的第一高度小于直接在所述内部鳍间隔件上方测量的所述半导体区域的第二高度。
示例20是示例16所述的器件,其中,所述半导体区域被合并为连续半导体区域。
Claims (13)
1.一种用于形成半导体器件的方法,包括:
在块半导体衬底上方形成隔离区域;
凹陷所述隔离区域,其中,所述隔离区域之间的半导体条带的顶部部分突出高于所述隔离区域的顶表面以形成鳍组,并且所述鳍组包括:
多个内部鳍;以及
第一外部鳍和第二外部鳍,位于所述多个内部鳍的相对侧上;以及
在所述多个内部鳍、所述第一外部鳍和所述第二外部鳍的侧壁上形成鳍间隔件,其中形成所述鳍间隔件包括:
在所述多个内部鳍、所述第一外部鳍和所述第二外部鳍的顶部表面和侧壁上沉积间隔件层;
执行第一刻蚀工艺以减薄所述间隔件层;
移除在所述第一刻蚀工艺中所产生的第一聚合物;
在移除了所述第一聚合物之后,执行第二刻蚀工艺以刻蚀所述间隔件层;
移除在所述第二刻蚀工艺中所产生的第二聚合物,并且
其中,所述鳍间隔件包括:
外部鳍间隔件,位于所述第一外部鳍的外部侧壁上,其中,所述外部侧壁背离所述鳍组,并且所述外部鳍间隔件具有第一高度;以及
内部鳍间隔件,位于所述第一外部鳍的内部侧壁上,其中,所述内部侧壁面向所述多个内部鳍,并且所述内部鳍间隔件具有小于所述第一高度的第二高度,
基于所述多个内部鳍、所述第一外部鳍和所述第二外部鳍来外延生长外延区域,其中所述外延生长外延区域包括用多个周期来脉冲偏置电压。
2.根据权利要求1所述的方法,其中,所述第一高度比所述第二高度大,高度差大于2nm。
3.根据权利要求1所述的方法,其中,所述外部鳍间隔件和所述内部鳍间隔件以共同的工艺形成。
4.根据权利要求1所述的方法,还包括形成栅极堆叠,其中,所述栅极堆叠在所述多个内部鳍、所述第一外部鳍和所述第二外部鳍中的每一项的侧壁和顶部表面上延伸。
5.根据权利要求4所述的方法,还包括在所述栅极堆叠的侧壁上形成栅极间隔件,其中,所述栅极间隔件和所述鳍间隔件以共同的形成工艺形成。
6.根据权利要求1所述的方法,其中,直接在所述外部鳍间隔件上方测量的所述外延区域的第三高度小于直接在所述内部鳍间隔件上方测量的所述外延区域的第四高度。
7.根据权利要求6所述的方法,其中,所述第四高度比所述第三高度大,高度差大于2nm。
8.根据权利要求1所述的方法,其中,所述脉冲的占空比在10%和90%之间的范围内。
9.一种用于形成半导体器件的方法,包括:
形成延伸到半导体衬底的隔离区域;
形成突出高于所述隔离区域的多个半导体鳍,其中,所述多个半导体鳍包括:
多个内部鳍;以及
第一外部鳍和第二外部鳍,位于所述多个内部鳍的相对侧上;
在所述多个半导体鳍的侧壁上形成鳍间隔件,其中形成所述鳍间隔件包括:
在所述多个半导体鳍的顶部表面和侧壁上沉积间隔件层;
执行第一蚀刻工艺以减薄所述间隔件层;
移除在所述第一蚀刻工艺中所产生的第一聚合物;
在移除了所述第一聚合物之后,执行第二蚀刻工艺以蚀刻所述间隔件层;
移除在所述第二蚀刻工艺中所产生的第二聚合物;并且
其中,所述鳍间隔件包括:
第一外部鳍间隔件和第二外部鳍间隔件,其中所述第一外部鳍间隔件和所述第二外部鳍间隔件具有第三高度;以及
内部鳍间隔件,位于所述第一外部鳍间隔件和所述第二外部鳍间隔件之间,其中,所述内部鳍间隔件具有小于所述第三高度的第四高度;并且
基于所述多个半导体鳍外延生长外延区域,其中,沿着所述第一外部鳍的外部侧壁测量的所述外延区域的第一高度小于沿着所述第一外部鳍的所述内部侧壁测量的所述外延区域的第二高度。
10.根据权利要求9所述的方法,其中,所述第一高度和所述第二高度之间的差大于2nm。
11.根据权利要求9所述的方法,其中,基于所述多个半导体鳍形成的所述外延区域被合并。
12.根据权利要求9所述的方法,其中,基于所述多个半导体鳍形成的所述外延区域未被合并。
13.根据权利要求9所述的方法,其中,所述第三高度和所述第四高度之间的差大于2nm。
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US11600728B2 (en) * | 2020-06-15 | 2023-03-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of manufacturing a facet-free source/drain epitaxial structure having an amorphous or polycrystalline layer |
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