CN1106690C - 半导体封装及其插座 - Google Patents

半导体封装及其插座 Download PDF

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CN1106690C
CN1106690C CN97104274A CN97104274A CN1106690C CN 1106690 C CN1106690 C CN 1106690C CN 97104274 A CN97104274 A CN 97104274A CN 97104274 A CN97104274 A CN 97104274A CN 1106690 C CN1106690 C CN 1106690C
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CN1179009A (zh
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安永峻
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MagnaChip Semiconductor Ltd
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LG Semicon Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K7/00—Constructional details common to different types of electric apparatus
    • H05K7/02—Arrangements of circuit components or wiring on supporting structure
    • H05K7/10—Plug-in assemblages of components, e.g. IC sockets
    • H05K7/1053—Plug-in assemblages of components, e.g. IC sockets having interior leads
    • H05K7/1061—Plug-in assemblages of components, e.g. IC sockets having interior leads co-operating by abutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body

Abstract

一种可很好地适应多管脚结构的半导体封装和它的插座，封装包括一个非导电水平基层，多个导电的金属引线垂直穿过基层，一个布线层，其中细金属线图形与导电的金属引线电连接，布线层的中央有一个凹室，半导体芯片安装在凹室的底部，半导体芯片和布线层的细金属线间有导线进行电连接，和一个覆盖凹室上部分的盖。

Description

半导体封装及其插座
本发明涉及半导体封装及其与之匹配很好具有多管脚结构的插座。
近来，半导体封装趋于更轻尺寸更小。在预定尺寸的封装中，将电信号从半导体芯片传输到外部的管脚(或引线)数减少。除此以外，为了增强封装的可靠性，热传输特性，和频率特性，进行了大量的细致的研究。在常规的半导体封装中，有一种为陶瓷无引线芯片托架(CLCC)。
图1A和1B为常规的CLCC半导体封装的剖示图和底视图。
图1A中，有一个陶瓷管座1。半导体芯片2借助粘合剂(未显示)安装在管座1的上部中央部分。第一导电层3的图形位于陶瓷体1的上部半导体芯片2外的部分到管座1下部侧面部分。第一绝缘层4形成在第一导电层3的上表面除图形以外的部分。第二导电层5的图形形成在第一绝缘层4上表面。第二绝缘层6形成在第二导电层5的上表面除图形预定区域以外的部分。半导体芯片2和第一和第二导电图形3和5通过引线7进行电连接。密封盖8位于第二绝缘层6的上表面以便保护半导体芯片2和引线7。
如图1B所示，接触槽9位于封装的周边，其中管座1，第一导电层3，第一绝缘层4，第二导电层5，和第二绝缘层6依次形成。
图2为将图1的CLCC半导体封装安装在常规插座中的剖面图。如图中所示，插座20中的许多插座引线管脚21插入到半导体封装10周边的接触槽9中的一个中。插座引线管脚21可将电信号从半导体芯片2传输到外部。
图3为将图1的CLCC半导体封装直接安装在印制电路板(PCB)上的剖面图。如图中所示，半导体封装10较低周边的导电层3电焊到PCB30的电路图形31上。在图中，参考数字32表示焊料。
然而，当常规CLCC半导体封装安装到PCB上时，金属层3和5仅在管座1的周边形成电触点。也就是，因为半导体封装的电路形成部分受到限制，所以很难增加半导体封装的管脚数目。
因此，本发明的目的在于提供一种可克服常规工艺遇到的问题的半导体封装和它的插座。
本发明的另一目的在于提供一种可很好地适应多管脚结构的改进的半导体封装和它的插座。
要达到以上目的，可提供这样一种半导体封装，它包括一个非导电水平基层；多个导电的金属引线垂直穿过基层；一个布线层，其中细金属线图形与导电的金属引线电连接；布线层的中央有一个凹室，半导体芯片安装在凹室的底部；半导体芯片和布线层的细金属线间有导线进行电连接；和一个覆盖凹室上部分的盖，其特征在于：所述多个导电金属引线的末端排列于所述基层的整个下表面上。
要达到以上目的，还提供了一种半导体封装的插座，它包括一个插座体，一个位于插座体中央上部的凹室，可用来在其中容纳半导体封装；多个第一插座管脚垂直地穿过水平的插座体底部，它的上下两端分别伸展超出了插座体的上下表面，多个第二插座管脚垂直地穿过插座体的侧壁，它的上端伸入凹室的内部，它的下端伸展超出了插座体的下表面，和一个覆盖凹室上部的插座盖，其特征在于：所述多个第一插座管脚的末端排列于所述插座体的整个底表面上。
通过以下介绍发明的其它优点，目的和特性将更明显。
下面将结合具体的实施例和附图说明本发明，但本发明并不局限于此，其中：
图1A和1B为常规的CLCC半导体封装的剖示图和底视图；
图2为将图1的CLCC半导体封装安装在常规插座中的剖面图；
图3为将图1的CLCC半导体封装直接安装在印制电路板(PCB)上的剖面图；
图4A和4B为依据本发明的半导体封装的剖面图和底视图；
图5为用于本发明半导体封装的插座的剖面图；
图6为依据本发明将图4的半导体封装安装在图5的插座上的剖面图；
图7为依据本发明将图4的半导体封装安装在PCB上的侧视图。
图4A和4B为依据本发明的半导体封装的剖面图和底视图。
如图所示，有一个由陶瓷材料制成的非导电基层41。多个导电的金属引线42垂直穿过基层41。如图4B所示，每个金属引线42的末端穿过基层的下表面，从而形成矩形栅。
此外，布线层43在基层41的上表面形成。布线层43包括绝缘层43a和由导电金属层形成的细金属线层43b，其中导电金属层是通过交替地叠层形成的。细金属线层43b是通过在每个绝缘层43a上腐蚀导电金属层形成的。每个细金属线43b都分别与对应的金属引线42电连接。
凹室45位于布线层43的上部中央处，用来在其中容纳半导体芯片44。在这里，当形成布线层43图形的细金属线43b时，细金属线43b的图形不是形成在布线层43的中心位置处，即凹室45形成的区域，这样，当细金属线43b的图形生成后，凹室45可以很容易并且自然地形成在布线层43的上部中央处。
此外，半导体芯片44安装在凹室45的底部，半导体芯片44和布线层43中的细金属线43b通过多个引线46进行电连接。非导电盖47固定在布线层43的上部并密封凹室45，这样凹室45中的半导体芯片44和引线46都可得到保护。
图5为用于图4A和4B中半导体封装的插座的剖面图。
在图中，有一个插座体50。凹室51位于插座体50的上部中央处，用来容纳半导体封装40。第一插座管脚52插入插座体50的底部并向上和向下延伸。第二插座管脚53垂直地插入插座体50的侧壁，它的一端伸入凹室51的内部，另一端向下穿过插座体50的下表面。伸入凹室51内部的第一和第二插座管脚52和53的末端都呈椭圆形弯曲用来增加它的接触面积，从而在凹室51内安装半导体封装40时，第一和第二插座管脚52和53与导电金属引线42形成电连接。
此外，插座盖54位于插座体50的上部分用于封闭凹室51。盖54的一侧通过绞链部分55与插座体50绞接，以便盖54开/关凹室51。盖54的底面有一个中央突起54a，可用来接触和按压半导体封装。挂钩56在盖54的另一侧形成，钩槽57为插座体50的一部分，以便当插座盖54覆盖凹室51时，挂钩56可挂住钩槽57。在盖54的上表面有许多平行的散热片和沟槽以便盖54更有效地散热。
图6为依据本发明将图4的半导体封装安装在图5的插座上的剖面图。
如图所示，半导体封装40安装在插座的凹室51内，插座的盖54闭合。盖54的挂钩56挂住体50的钩槽57，以便盖54紧紧地固定住体50。此外，盖54下表面的突起54a向下按压半导体封装40的上表面，以便凹室51底部凸出的第一插座管脚52与半导体封装40的金属引线42相互形成电连接。
此外，由于显示在图5中的插座有第二插座管脚53，而该第二插座管脚53与显示在图2中的插座管脚21有相同的图形，因此常规的半导体封装可安装在本发明的插座中。
图7为依据本发明将图4的半导体封装安装在PCB上的侧视图。
如图所示，半导体封装40下表面的多个金属引线42与PCB60的电路图形61相接触并被焊接，从而形成电接触点。在图中，参考数字62表示焊料。
如前所述，依照本发明的半导体封装和插座可在有限的空间内直接安排一个多管脚结构，这样就可得到带有多管脚结构的小型产品。此外，常规的CLCC半导体封装也可以使用本发明的半导体封装。而且，可在插座和半导体封装间得到更精确的电连接以及优良的散热特性。
本发明的最佳实施例仅为说明，本领域的技术人员可进行不同的修改，增补和替换，但都不脱离本发明的权利要求的范围和精神。

Claims (9)

1.一种半导体封装，包括：
一个非导电水平基层；
多个导电的金属引线垂直穿过基层；
一个布线层，其中细金属线图形与导电的金属引线电连接；
布线层的中央有一个凹室；
半导体芯片安装在凹室的底部；
半导体芯片和布线层的细金属线间有导线进行电连接；和
一个覆盖凹室上部分的盖，
其特征在于：
所述多个导电金属引线的末端排列于所述基层的整个下表面上。
2.如权利要求1所述的半导体封装，其中所述的基层由陶瓷材料制成。
3.如权利要求1所述的半导体封装，其中所述的布线层由多个细金属线图形层通过涂层和腐蚀导电层和绝缘层形成。
4.一种用于半导体封装的插座，包括：
一个插座体；
一个位于插座体中央上部的凹室，可用来容纳半导体封装；
多个第一插座的管脚垂直地穿过水平的管座底部，所说的第一插座的管脚上下两端分别穿过插座体的上下表面；
多个第二插座的管脚垂直地穿过插座体的侧壁，所说的第二插座的管脚上端穿入凹室的内部，所说的第二插座的管脚的下端穿过插座体的下表面；和
一个覆盖凹室上部的插座盖，
其特征在于：
所述多个第一插座管脚的末端排列于所述插座体的整个底表面上。
5.如权利要求4所述的插座，其中伸入凹室内部的所述第一和第二插座管脚的末端都呈椭圆形弯曲。
6.如权利要求4所述的插座，其中插座盖的上表面有多个散热片和沟槽。
7.如权利要求4所述的插座，其中插座盖的一侧与插座体的绞链部分相绞接。
8.如权利要求4所述的插座，其中所述的插座盖包括一个在一侧形成的挂钩。
9.如权利要求4所述的插座，其中所述的插座体包括一个在一侧形成的钩槽。
CN97104274A 1996-10-04 1997-05-16 半导体封装及其插座 Expired - Lifetime CN1106690C (zh)

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US5977623A (en) 1999-11-02
KR100218319B1 (ko) 1999-09-01
JPH10125822A (ja) 1998-05-15
KR19980025603A (ko) 1998-07-15
CN1179009A (zh) 1998-04-15

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