CN1613148A - 带有共封装管芯的半导体器件 - Google Patents

带有共封装管芯的半导体器件 Download PDF

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CN1613148A
CN1613148A CNA028269438A CN02826943A CN1613148A CN 1613148 A CN1613148 A CN 1613148A CN A028269438 A CNA028269438 A CN A028269438A CN 02826943 A CN02826943 A CN 02826943A CN 1613148 A CN1613148 A CN 1613148A
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semiconductor device
clamping device
semiconductor element
encapsulated semiconductor
connecting plate
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CN100466235C (zh
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马丁·斯坦丁
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Infineon science and technology Americas
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International Rectifier Corp USA
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Abstract

一种包含金属容器形式的外夹持装置(12)的共封装半导体管芯(10)还包括两个半导体管芯(30)，其中至少一个半导体管芯将所述外夹持装置作为电连接器使用。内夹持装置(28)用来将管芯之一安放在外夹持装置之内。内夹持装置可通过绝缘层与外夹持装置绝缘。

Description

带有共封装管芯的半导体器件
发明背景
本发明涉及半导体器件，特别涉及一种包含至少两个共封装(co-packaged)半导体管芯(die)的半导体器件。
一般称为copak的共封装器件是公知的。通常，这类器件包含封装在一公用外壳内的两个或更多个相同或不同的半导体器件。这种结构所实现的好处在于其具有更加紧凑的电子封装，这种紧凑的电子封装在电路板上占用的空间比在电路内实现相同功能的单独封装的半导体管芯所占用的空间小。空间的节省自然地使得建构更紧凑的和/或在相同空间中包含更多电子部件的更加复杂仪器成为可能。
许多共封装器件包含模制的外壳(housing)和引线框(lead frame)。外壳为半导体管芯提供了对诸如湿气等环境因素的保护，而引线框则被用来连接半导体管芯与电路内的外部元件。因此，由于这种结构需要多个部件，所以它不仅增加了copak的成本而且其制造也变得复杂。所以，需要有这样一种copak器件，其含有两个或更多的器件，同时减少了其组装所需的部件的数目。
发明内容
根据本发明的半导体器件包含至少两个相同或不同的半导体管芯(die)。这两个半导体管芯被共同封装在公用的外金属夹具(clip)中，所述金属夹具可作为至少一个所述半导体管芯的外连接器使用。
根据本发明的第一个方面所述，两个相同或不同的半导体管芯被包容在一个外夹具中，所述外夹具既用作所述管芯的外壳，又用作电连接器以连接所述管芯之一与电子电路中的外部元件。
明确地讲，根据本发明所述的共封装半导体器件包括金属容器(metalcan)，其具有基本平直的连接板(web)部分以及多个壁，所述壁限定出一个空间。可以是金属氧化物半导体场效应晶体管(MOSFET)的第一半导体管芯的漏极通过导电层与所述连接板部分电连接，所述导电层可以是焊料层或导电环氧树脂层。从所述外夹具的两个相对壁的边缘伸展的两个凸起部分与诸如电路板的衬底上的相应电焊盘(pad)连接，从而将MOSFET的漏极连接至其在电子电路中的合适位置。
第二半导体管芯被设置于一内夹具中，该内夹具通过绝缘层与所述外夹具的连接板部分连接，但是与其绝缘。第二半导体管芯可以是和第一半导体管芯相同的MOSFET，或者可以是在半导体芯片上形成的用于控制第一半导体管芯操作的集成电路。
根据本发明的第一个方面所述，第一半导体管芯的厚度与内夹具和第二半导体管芯的总高度相同，从而他们各自的上表面相互共面，并且优选地与凸起部分的接触面互相共面。为了实现这一结果，可对第二半导体管芯进行打磨以减小其厚度。
根据本发明的内夹具包括底板和多个从所述底板的边缘充分垂直伸展的壁。所述内夹具的至少一个壁包括一个伸展部分，该伸展部分被弯曲以限定出一个接触面，所述接触面优选地与所述外夹具的凸起部分共面。所述内夹具的所述接触面和衬底上的合适的焊盘(pad)接触，以将所述第二半导体管芯连接至其在电子电路内的相应位置。优选地，所述内夹具的外表面经过化学处理以形成绝缘表面，或通过电绝缘聚合物(如聚酰亚胺)层被隔离。所述内夹具的内表面上优选地涂有诸如银的良导电金属。通过使铜箔的边缘凸起以形成至少部分容纳了所述第二半导体管芯的基本垂直的壁，就可形成所述内夹具。
根据本发明第二个实施方案所述的共封装半导体器件包含一个外夹具，该外夹具可以是与第一实施方案中所使用的金属容器基本类似的金属容器。根据第二实施方案所述的半导体器件包括至少两个相同或不同的半导体管芯，每一个管芯至少有一个主要电极通过焊料或导电环氧树脂形成的导电层与外夹具的连接板部分电导通。在这个实施方案中，外夹具既用作半导体管芯的外壳，又用作电连接器以连接器件与电子电路中的外部元件。
通过以下结合附图对本发明的描述，本发明的其它特征和优点将变得更加清楚。
附图的简要说明
图1是根据本发明第一实施方案所述的半导体器件的俯视平面图。
图2是从图1中的线1-1的方向看去所得到的本发明第一实施方案的剖视图。
图3是根据本发明一个方面所述的内夹具的侧视平面图。
图4是图3中所示内夹具的俯视平面图。
图5是根据本发明第二实施方案所述的半导体器件的俯视平面图。
图6是从图5中的线2-2的方向看去所得到的本发明第二实施方案的剖视图。
图7示出了与衬底连接的根据本发明第一实施方案所述的半导体器件。
图8示出了与衬底连接的根据本发明第二实施方案所述的半导体器件。
附图的详细说明
图1示出了根据本发明第一实施方案所述的半导体器件10。该半导体器件10包括外导电夹具12。外导电夹具12为金属容器(metal can)，其包含连接板部分(web portion)14和多个壁16，壁16从连接板部分14的边缘伸展以限定出一个空间。外夹具12可以是铜制的，优选地涂有银。第一半导体管芯18被放置在由外导电夹具12的壁16所限定出的空间之内。第一半导体管芯18可以是垂直导电的金属氧化物半导体场效应晶体管(MOSFET)，功率二极管(power diode)，绝缘栅双极型晶体管(IGBT)或类似器件。在本发明的第一实施方案中，第一半导体器件18是垂直导电的MOSFET，其具有源极20、栅极22以及漏极24(图2)。
参照图2，第一半导体管芯18的漏极24通过导电材料层26与外导电夹具12的连接板部分14电连接。导电材料可以是焊料或导电环氧树脂。根据第一实施方案所述的半导体器件10还包括放置在由外夹具12的壁16所限定出的空间之内的内夹具28。
参照图3和4，内夹具28优选地由导电金属薄片(如薄铜片)制成，并且优选地包括垂直伸展的壁30，壁30围绕其底板部分32限定出了一个空间。内夹具28还包括伸展部分34，它从夹具28的壁30之一的边缘伸展，并且被弯曲从而提供一个接触面33。内夹具28的内表面可以涂上良导电材料(如银)，并且其外表面可以经过化学处理以具有绝缘性或者被覆盖以绝缘胶膜(如聚酰亚胺)。内夹具28优选地是通过使薄铜箔的外边缘凸起以形成壁30而做成的。如此形成的壁中的一个应该具有伸展部分34，该伸展部分34随后被向外弯曲以暴露出伸展部分34的内表面，该内表面就作为接触面33。用于形成内夹具28的铜箔，其厚度应该薄于外夹具12的深度。例如，在一个优选实施方案中，所使用的铜箔的厚度约为0.100mm，而外夹具12的深度则约为0.396mm。
现在参照图1和2，第二半导体管芯36位于内夹具28的壁30之内的空间中。在第一实施方案中，第二半导体管芯可以是MOSFET，其漏极(未示出)通过导电层38与内夹具28电连接，导电层38可以由焊料或导电环氧树脂(如含银环氧树脂)形成。内夹具28的壁30起到阻碍物(dam)的作用，用以防止焊料或导电环氧树脂溅到外夹具12的连接板部分14上并与其接触。第二半导体管芯36通过设置在内夹具28的底部和外夹具12的连接板部分14之间的绝缘层40而与外夹具12绝缘。在一个优选实施方案中，第一半导体管芯18的厚度约为0.350，该厚度通过导电材料26被升高到外夹具12的深度的顶部。在内夹具28的内部，第二半导体管芯36也被升高，从而使其上表面与第一半导体管芯18的上表面共面。为了获得这一结果，有可能需要使用比第一半导体管芯18薄的管芯。在一个优选实施方案中，第二半导体管芯36的厚度为0.200mm。为了获得这一厚度，在将管芯放入内容器28之前，可将管芯的背面打磨至所需的厚度。
参照图7，根据本发明的一个方面所述，外夹具12包括至少两个凸起部分42，其从外夹具12的两个相对的壁的边缘处升起。每个凸起部分42都具有平的接触面，用以与衬底45(如电路板或绝缘金属衬底)上的相应电焊盘(pad)43进行电接触。第一半导体管芯18的漏极24通过凸起部分42与其在电路中的合适的位置电连接。所以，外夹具12同时起到了第一半导体管芯12的外壳和电连接器的作用。
在根据第一实施方案所述的半导体器件10中，伸展部分34的接触面33、第一半导体管芯18的源极20以及第二半导体管芯36的源极35与外夹具12的凸起部分42的接触面相共面。接触面33将第二半导体管芯36的漏极连接至衬底45上的合适的导电焊盘(pad)47，从而使第二半导体管芯36的漏极与其在电路中的合适位置连接。
图5和6示出了根据本发明第二实施方案所述的半导体器件44，在图中相同的标号代表了相同的零件(feature)。根据第二实施方案所述的半导体器件44包括第一和第二半导体器件18，18’，它们可以都是MOSFET。但是功率二极管、IGBTS等也可以用来代替MOSFET。第一和第二半导体18和18’的漏极24和24’通过导电层27，27’与外夹具12的连接板部分14电连接。也可以利用公共的导电层来代替单独的导电层27，27’。导电层27和27’可以是由焊料或导电环氧树脂(如含银导电环氧树脂)形成的层。第一和第二半导体器件18，18’的源极20和20’相互共面，并且优选地与外夹具12的凸起部分42共面。在第二实施方案中，外夹具12既用作半导体管芯的漏极24和24’的外壳，也用作它们的公共连接器。如图8所示，凸起部分42与衬底45上的焊盘(pad)43产生电接触，从而使管芯的漏极24，24’与它们在电路中的适当位置相连接。管芯的源极20和20’也和衬底45上的焊盘49电接触，从而使源极20和20’与它们在电路中的适当位置相连接，如图和图8所示。
本领域的普通技术人员应该预计到，通过采用在本文中描述并且以实施方案为例进行说明的创造性概念，就可以利用各种半导体管芯的组合来实现本发明。例如，在第一实施方案中，第二半导体36可以用肖特基(Schottky)二极管或控制集成电路(IC)取代以用于控制第一半导体管芯18。
尽管对本发明的描述是结合其特定实施方案来进行的，但是对于本领域的普通技术人员来说，许多其他的变化、修改和应用是显而易见的。因此，本发明优选地并不受限于本文的具体说明，而只受限于所附的权利要求。

Claims (13)

1.一种共封装半导体器件，包括：
外导电夹持装置，其具有连接板部分和多个壁，所述壁从所述连接板部分的边缘伸展以限定出一个空间；
第一半导体管芯，其至少含有两个主要电极，所述各主要电极被安放于所述第一半导体管芯的各主要表面上；
导电层，其将所述主要电极之一电连接至所述连接板部分；
内夹持装置，其具有多个壁，并且被安放于所述空间之内和所述连接板部分上；
第二半导体管芯，其至少部分地被安放在所述内导电夹持装置之内。
2.根据权利要求1所述的共封装半导体器件，其特征在于，所述外导电夹持装置包含从其两个相对的壁的边缘伸展的两个凸起部分，每个所述凸起部分都包含一个接触面，用以与衬底上的相应电接触焊盘电连接。
3.根据权利要求2所述的共封装半导体器件，其特征在于，所述内夹持装置包括从其多个壁中的至少一个伸展的部分，所述部分与所述外导电夹持装置的所述两个凸起部分的所述接触面相共面。
4.根据权利要求1所述的共封装半导体器件，其特征在于，所述内夹持装置与所述连接板部分连接但与其绝缘。
5.根据权利要求1所述的共封装半导体器件，其特征在于，所述第一和第二半导体管芯是金属氧化物半导体场效应晶体管。
6.根据权利要求1所述的共封装半导体器件，其特征在于，所述第一半导体芯管芯是金属氧化物半导体场效应晶体管，其漏极和所述连接板部分相连，所述第二半导体管芯是用于控制所述金属氧化物半导体场效应晶体管的集成电路。
7.根据权利要求1所述的共封装半导体器件，其特征在于，所述内夹持装置由铜制成。
8.根据权利要求1所述的共封装半导体器件，其特征在于，所述内导电夹持装置的外表面是绝缘的。
9.根据权利要求1所述的共封装半导体器件，其特征在于，所述内夹持装置的内表面涂有银。
10.根据权利要求1所述的共封装半导体器件，进一步包括连接所述内夹持装置和所述连接板部分的绝缘层。
11.根据权利要求1所述的共封装半导体器件，其特征在于，所述第二半导体管芯比所述第一半导体管芯薄。
12.根据权利要求1所述的共封装半导体器件，其特征在于，所述第二半导体管芯通过导电环氧树脂与所述内夹持装置电连接。
13.根据权利要求1至12所述的共封装半导体器件，其特征在于，所述外导电夹持装置为金属容器。
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104916615A (zh) * 2014-03-13 2015-09-16 株式会社东芝 半导体装置及模块
CN105321921A (zh) * 2006-07-14 2016-02-10 阿莱戈微系统有限责任公司 为用于集成电路的部件实现无源附着的方法和设备
CN108242436A (zh) * 2016-12-23 2018-07-03 英飞凌科技美洲公司 共接触部半导体器件封装

Families Citing this family (59)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6946740B2 (en) * 2002-07-15 2005-09-20 International Rectifier Corporation High power MCM package
WO2005024937A1 (de) * 2003-09-05 2005-03-17 Rohde & Schwarz Gmbh & Co. Kg Elektronisches bauelement mit kühlfläche
JP4244318B2 (ja) * 2003-12-03 2009-03-25 株式会社ルネサステクノロジ 半導体装置
JP4312616B2 (ja) * 2004-01-26 2009-08-12 Ｎｅｃエレクトロニクス株式会社 半導体装置
US7235877B2 (en) * 2004-09-23 2007-06-26 International Rectifier Corporation Redistributed solder pads using etched lead frame
CN100435324C (zh) * 2004-12-20 2008-11-19 半导体元件工业有限责任公司 具有增强散热性的半导体封装结构
US7884454B2 (en) 2005-01-05 2011-02-08 Alpha & Omega Semiconductor, Ltd Use of discrete conductive layer in semiconductor device to re-route bonding wires for semiconductor device package
US7898092B2 (en) * 2007-11-21 2011-03-01 Alpha & Omega Semiconductor, Stacked-die package for battery power management
US7524701B2 (en) * 2005-04-20 2009-04-28 International Rectifier Corporation Chip-scale package
US7230333B2 (en) 2005-04-21 2007-06-12 International Rectifier Corporation Semiconductor package
US7504733B2 (en) * 2005-08-17 2009-03-17 Ciclon Semiconductor Device Corp. Semiconductor die package
US7560808B2 (en) * 2005-10-19 2009-07-14 Texas Instruments Incorporated Chip scale power LDMOS device
US8089147B2 (en) * 2005-11-02 2012-01-03 International Rectifier Corporation IMS formed as can for semiconductor housing
US7446375B2 (en) * 2006-03-14 2008-11-04 Ciclon Semiconductor Device Corp. Quasi-vertical LDMOS device having closed cell layout
US20070215997A1 (en) * 2006-03-17 2007-09-20 Martin Standing Chip-scale package
US7541681B2 (en) * 2006-05-04 2009-06-02 Infineon Technologies Ag Interconnection structure, electronic component and method of manufacturing the same
US7476978B2 (en) * 2006-05-17 2009-01-13 Infineon Technologies, Ag Electronic component having a semiconductor power device
US7757392B2 (en) 2006-05-17 2010-07-20 Infineon Technologies Ag Method of producing an electronic component
US7271470B1 (en) 2006-05-31 2007-09-18 Infineon Technologies Ag Electronic component having at least two semiconductor power devices
US7626262B2 (en) * 2006-06-14 2009-12-01 Infineon Technologies Ag Electrically conductive connection, electronic component and method for their production
US20080036078A1 (en) * 2006-08-14 2008-02-14 Ciclon Semiconductor Device Corp. Wirebond-less semiconductor package
DE102006044690B4 (de) * 2006-09-22 2010-07-29 Infineon Technologies Ag Elektronisches Bauteil und Verfahren zum Herstellen
DE102006047761A1 (de) * 2006-10-06 2008-04-10 Infineon Technologies Ag Halbleiterbauteil und Verfahren zu dessen Herstellung
DE102007007142B4 (de) * 2007-02-09 2008-11-13 Infineon Technologies Ag Nutzen, Halbleiterbauteil sowie Verfahren zu deren Herstellung
DE102007012154B4 (de) * 2007-03-12 2014-05-08 Infineon Technologies Ag Halbleitermodul mit Halbleiterchips und Verfahren zur Herstellung desselben
DE102007013186B4 (de) * 2007-03-15 2020-07-02 Infineon Technologies Ag Halbleitermodul mit Halbleiterchips und Verfahren zur Herstellung desselben
US7759777B2 (en) * 2007-04-16 2010-07-20 Infineon Technologies Ag Semiconductor module
US7879652B2 (en) * 2007-07-26 2011-02-01 Infineon Technologies Ag Semiconductor module
US20090057855A1 (en) * 2007-08-30 2009-03-05 Maria Clemens Quinones Semiconductor die package including stand off structures
US7701065B2 (en) * 2007-10-26 2010-04-20 Infineon Technologies Ag Device including a semiconductor chip having a plurality of electrodes
US7799614B2 (en) * 2007-12-21 2010-09-21 Infineon Technologies Ag Method of fabricating a power electronic device
US8642394B2 (en) * 2008-01-28 2014-02-04 Infineon Technologies Ag Method of manufacturing electronic device on leadframe
US8294208B2 (en) * 2008-03-04 2012-10-23 International Rectifier Corporation Semiconductor device having a gate contact on one surface electrically connected to a gate bus on an opposing surface
US8637341B2 (en) * 2008-03-12 2014-01-28 Infineon Technologies Ag Semiconductor module
US7759163B2 (en) * 2008-04-18 2010-07-20 Infineon Technologies Ag Semiconductor module
US8441804B2 (en) * 2008-07-25 2013-05-14 Infineon Technologies Ag Semiconductor device and method of manufacturing a semiconductor device
US8410590B2 (en) * 2008-09-30 2013-04-02 Infineon Technologies Ag Device including a power semiconductor chip electrically coupled to a leadframe via a metallic layer
US8710665B2 (en) 2008-10-06 2014-04-29 Infineon Technologies Ag Electronic component, a semiconductor wafer and a method for producing an electronic component
US8049312B2 (en) * 2009-01-12 2011-11-01 Texas Instruments Incorporated Semiconductor device package and method of assembly thereof
US9257375B2 (en) 2009-07-31 2016-02-09 Alpha and Omega Semiconductor Inc. Multi-die semiconductor package
US8164199B2 (en) * 2009-07-31 2012-04-24 Alpha and Omega Semiconductor Incorporation Multi-die package
US20120175688A1 (en) * 2011-01-10 2012-07-12 International Rectifier Corporation Semiconductor Package with Reduced On-Resistance and Top Metal Spreading Resistance with Application to Power Transistor Packaging
US8637981B2 (en) 2011-03-30 2014-01-28 International Rectifier Corporation Dual compartment semiconductor package with temperature sensor
US8531016B2 (en) * 2011-05-19 2013-09-10 International Rectifier Corporation Thermally enhanced semiconductor package with exposed parallel conductive clip
US9048338B2 (en) * 2011-11-04 2015-06-02 Infineon Technologies Ag Device including two power semiconductor chips and manufacturing thereof
DE102011086687A1 (de) * 2011-11-21 2013-05-23 Robert Bosch Gmbh Verfahren zum Kontaktieren eines Halbleiters und Kontaktanordnung für einen Halbleiter
DE102012215656B4 (de) * 2012-09-04 2015-05-21 Semikron Elektronik Gmbh & Co. Kg Verfahren zur Herstellung eines Leistungshalbleitermoduls
US9202811B2 (en) * 2012-12-18 2015-12-01 Infineon Technologies Americas Corp. Cascode circuit integration of group III-N and group IV devices
US9054040B2 (en) 2013-02-27 2015-06-09 Infineon Technologies Austria Ag Multi-die package with separate inter-die interconnects
US9041170B2 (en) 2013-04-02 2015-05-26 Infineon Technologies Austria Ag Multi-level semiconductor package
US9214415B2 (en) * 2013-04-11 2015-12-15 Texas Instruments Incorporated Integrating multi-output power converters having vertically stacked semiconductor chips
US9536800B2 (en) 2013-12-07 2017-01-03 Fairchild Semiconductor Corporation Packaged semiconductor devices and methods of manufacturing
DE102014118080B4 (de) * 2014-12-08 2020-10-15 Infineon Technologies Ag Elektronisches Modul mit einem Wärmespreizer und Verfahren zur Herstellung davon
DE102015200868A1 (de) * 2015-01-20 2016-07-21 Zf Friedrichshafen Ag Steuerelektronik
CN104617058B (zh) 2015-01-23 2020-05-05 矽力杰半导体技术(杭州)有限公司 用于功率变换器的封装结构及其制造方法
EP3065172A1 (en) * 2015-03-06 2016-09-07 Nxp B.V. Semiconductor device
DE102015104995B4 (de) 2015-03-31 2020-06-04 Infineon Technologies Austria Ag Verbindungshalbleitervorrichtung mit einem mehrstufigen Träger
US10559510B2 (en) 2017-08-24 2020-02-11 Semiconductor Components Industries, Llc Molded wafer level packaging
US10438877B1 (en) * 2018-03-13 2019-10-08 Semiconductor Components Industries, Llc Multi-chip packages with stabilized die pads

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3784726A (en) * 1971-05-20 1974-01-08 Hewlett Packard Co Microcircuit package assembly
US3972062A (en) 1973-10-04 1976-07-27 Motorola, Inc. Mounting assemblies for a plurality of transistor integrated circuit chips
US4314270A (en) 1977-12-02 1982-02-02 Mitsubishi Denki Kabushiki Kaisha Hybrid thick film integrated circuit heat dissipating and grounding assembly
US4766479A (en) * 1986-10-14 1988-08-23 Hughes Aircraft Company Low resistance electrical interconnection for synchronous rectifiers
JPS6481346A (en) * 1987-09-24 1989-03-27 Fujitsu Ltd Sealing structure of chip component of microwave integrated circuit
US5731970A (en) * 1989-12-22 1998-03-24 Hitachi, Ltd. Power conversion device and semiconductor module suitable for use in the device
JP2936855B2 (ja) * 1991-12-26 1999-08-23 富士電機株式会社 電力用半導体装置
DE69329542T2 (de) * 1992-06-05 2001-02-08 Mitsui Chemicals Inc Dreidimensionale leiterplatte, elektronische bauelementanordnung unter verwendung dieser leiterplatte und herstellungsverfahren zu dieser leiterplatte
JP3198796B2 (ja) * 1993-06-25 2001-08-13 富士電機株式会社 モールドモジュール
JP3180863B2 (ja) * 1993-07-27 2001-06-25 富士電機株式会社 加圧接触形半導体装置およびその組立方法
JP2991010B2 (ja) * 1993-09-29 1999-12-20 富士電機株式会社 半導体装置およびその製造方法
JPH07161925A (ja) * 1993-12-09 1995-06-23 Mitsubishi Electric Corp パワーモジュール
JPH07297575A (ja) * 1994-04-21 1995-11-10 Mitsubishi Electric Corp パワーモジュール装置
KR100230894B1 (ko) * 1995-06-22 1999-11-15 구라우치 노리타카 전력증폭모듈
TW315491B (en) * 1995-07-31 1997-09-11 Micron Technology Inc Apparatus for applying adhesive tape for semiconductor packages
JP3448159B2 (ja) * 1996-06-20 2003-09-16 株式会社東芝 電力用半導体装置
US6075289A (en) * 1996-10-24 2000-06-13 Tessera, Inc. Thermally enhanced packaged semiconductor assemblies
US5814884C1 (en) * 1996-10-24 2002-01-29 Int Rectifier Corp Commonly housed diverse semiconductor die
JP3535328B2 (ja) * 1996-11-13 2004-06-07 株式会社ルネサステクノロジ リードフレームとこれを用いた半導体装置
US5926695A (en) * 1997-06-10 1999-07-20 National Semiconductor Corporation Lead frame incorporating material flow diverters
US6184585B1 (en) * 1997-11-13 2001-02-06 International Rectifier Corp. Co-packaged MOS-gated device and control integrated circuit
TW451535B (en) * 1998-09-04 2001-08-21 Sony Corp Semiconductor device and package, and fabrication method thereof
US6624522B2 (en) * 2000-04-04 2003-09-23 International Rectifier Corporation Chip scale surface mounted device and process of manufacture
JP3923258B2 (ja) * 2001-01-17 2007-05-30 松下電器産業株式会社 電力制御系電子回路装置及びその製造方法
JP4286465B2 (ja) * 2001-02-09 2009-07-01 三菱電機株式会社 半導体装置とその製造方法

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105321921A (zh) * 2006-07-14 2016-02-10 阿莱戈微系统有限责任公司 为用于集成电路的部件实现无源附着的方法和设备
CN105321921B (zh) * 2006-07-14 2020-11-27 阿莱戈微系统有限责任公司 为用于集成电路的部件实现无源附着的方法和设备
CN104916615A (zh) * 2014-03-13 2015-09-16 株式会社东芝 半导体装置及模块
CN108242436A (zh) * 2016-12-23 2018-07-03 英飞凌科技美洲公司 共接触部半导体器件封装
CN108242436B (zh) * 2016-12-23 2021-07-27 英飞凌科技美洲公司 共接触部半导体器件封装

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EP1466363A4 (en) 2007-08-15
US20030137040A1 (en) 2003-07-24
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US6677669B2 (en) 2004-01-13

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